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[/] [System09/] [rev_86/] [rtl/] [VHDL/] [datram.vhd] - Blame information for rev 186

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1 19 dilbert57 
--===========================================================================--
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--
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--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
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--
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--  www.OpenCores.Org - December 2002
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--  This core adheres to the GNU public license
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--
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-- File name      : datram.vhd
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--
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-- entity name    : dat_ram
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--
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-- Purpose        : Implements a Dynamic Address Translation RAM module
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--                  Maps the high order 4 address bits to 8 address lines
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--                  extending the memory addressing range to 1 Mbytes
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--                  Memory segments are mapped on 4 KByte boundaries
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--                  The DAT registers map to the top of memory
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--                  ($FFF0 - $FFFF) and are write only so can map behind ROM.
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--                  Since the DAT is not supported by SWTBUG for the 6800,
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--                  the resgisters reset state map the bottom 64K of RAM.
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--
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-- Author         : John E. Kent
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--
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--===========================================================================----
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--
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-- Revision History:
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--
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-- Date          Revision  Author
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-- 10 Nov 2002   0.1       John Kent
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--
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-- 21 Nov 2006   0.2       John Kent
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-- Inverted bottom 4 bits of dat_addr
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-- so that it is compatible with SWTPc MP-09 card.
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-- DAT is initializedas follows:
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--
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-- DAT    Dat           Logical Physical
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-- Reg    Val           Addr    Addr
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--      fff0 - 0f - page 0 - $0xxx = $00xxx (RAM)
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--      fff1 - 0e - page 1 - $1xxx = $01xxx (RAM)
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--      fff2 - 0d - page 0 - $2xxx = $02xxx (RAM)
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--      fff3 - 0c - page 0 - $3xxx = $03xxx (RAM)
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--      fff4 - 0b - page 0 - $4xxx = $04xxx (RAM)
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--      fff5 - 0a - page 0 - $5xxx = $05xxx (RAM)
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--      fff6 - 09 - page 0 - $6xxx = $06xxx (RAM)
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--      fff7 - 08 - page 0 - $7xxx = $07xxx (RAM)
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--      fff8 - 07 - page 0 - $8xxx = $08xxx (RAM)
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--      fff9 - 06 - page 0 - $9xxx = $09xxx (RAM)
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--      fffa - 05 - page 0 - $axxx = $0axxx (RAM)
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--      fffb - 04 - page 0 - $bxxx = $0bxxx (RAM)
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--      fffc - 03 - page 0 - $cxxx = $0cxxx (RAM)
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--      fffd - 02 - page 0 - $dxxx = $0dxxx (RAM)
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--      fffe - f1 - page 0 - $exxx = $fexxx (I/O)
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--      ffff - f0 - page 0 - $fxxx = $ffxxx (ROM/DMFA2)
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-- 25 Feb 2007   0.3      John Kent
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-- modify the sensitivity lists
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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library unisim;
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  use unisim.vcomponents.all;
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entity dat_ram is
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr_hi   : in  std_logic_vector(3 downto 0);
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    addr_lo   : in  std_logic_vector(3 downto 0);
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    data_in   : in  std_logic_vector(7 downto 0);
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         data_out  : out std_logic_vector(7 downto 0));
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end dat_ram;
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architecture rtl of dat_ram is
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signal dat_reg0 : std_logic_vector(7 downto 0);
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signal dat_reg1 : std_logic_vector(7 downto 0);
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signal dat_reg2 : std_logic_vector(7 downto 0);
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signal dat_reg3 : std_logic_vector(7 downto 0);
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signal dat_reg4 : std_logic_vector(7 downto 0);
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signal dat_reg5 : std_logic_vector(7 downto 0);
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signal dat_reg6 : std_logic_vector(7 downto 0);
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signal dat_reg7 : std_logic_vector(7 downto 0);
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signal dat_reg8 : std_logic_vector(7 downto 0);
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signal dat_reg9 : std_logic_vector(7 downto 0);
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signal dat_reg10 : std_logic_vector(7 downto 0);
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signal dat_reg11 : std_logic_vector(7 downto 0);
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signal dat_reg12 : std_logic_vector(7 downto 0);
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signal dat_reg13 : std_logic_vector(7 downto 0);
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signal dat_reg14 : std_logic_vector(7 downto 0);
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signal dat_reg15 : std_logic_vector(7 downto 0);
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begin
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---------------------------------
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--
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-- Write DAT RAM
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--
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---------------------------------
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--dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
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dat_write : process( clk )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      dat_reg0  <= "00001111";
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      dat_reg1  <= "00001110";
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      dat_reg2  <= "00001101";
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      dat_reg3  <= "00001100";
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      dat_reg4  <= "00001011";
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      dat_reg5  <= "00001010";
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      dat_reg6  <= "00001001";
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      dat_reg7  <= "00001000";
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      dat_reg8  <= "00000111";
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      dat_reg9  <= "00000110";
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      dat_reg10 <= "00000101";
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      dat_reg11 <= "00000100";
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      dat_reg12 <= "00000011";
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      dat_reg13 <= "00000010";
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      dat_reg14 <= "11110001";
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      dat_reg15 <= "11110000";
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    else
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           if cs = '1' and rw = '0' then
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        case addr_lo is
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             when "0000" =>
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                    dat_reg0 <= data_in;
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             when "0001" =>
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                    dat_reg1 <= data_in;
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             when "0010" =>
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                    dat_reg2 <= data_in;
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             when "0011" =>
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                    dat_reg3 <= data_in;
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             when "0100" =>
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                    dat_reg4 <= data_in;
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             when "0101" =>
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                    dat_reg5 <= data_in;
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             when "0110" =>
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                    dat_reg6 <= data_in;
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             when "0111" =>
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                    dat_reg7 <= data_in;
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             when "1000" =>
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                    dat_reg8 <= data_in;
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             when "1001" =>
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                    dat_reg9 <= data_in;
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             when "1010" =>
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                    dat_reg10 <= data_in;
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             when "1011" =>
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                    dat_reg11 <= data_in;
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             when "1100" =>
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                    dat_reg12 <= data_in;
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             when "1101" =>
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                    dat_reg13 <= data_in;
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             when "1110" =>
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                    dat_reg14 <= data_in;
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             when "1111" =>
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                    dat_reg15 <= data_in;
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        when others =>
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                    null;
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                  end case;
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           end if;
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         end if;
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  end if;
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end process;
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dat_read : process(  addr_hi,
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                     dat_reg0, dat_reg1, dat_reg2, dat_reg3,
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                     dat_reg4, dat_reg5, dat_reg6, dat_reg7,
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                     dat_reg8, dat_reg9, dat_reg10, dat_reg11,
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                     dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
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variable phy_addr : std_logic_vector( 7 downto 0 );
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begin
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      case addr_hi is
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             when "0000" =>
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                    phy_addr := dat_reg0;
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             when "0001" =>
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                    phy_addr := dat_reg1;
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             when "0010" =>
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                    phy_addr := dat_reg2;
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             when "0011" =>
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                    phy_addr := dat_reg3;
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             when "0100" =>
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                    phy_addr := dat_reg4;
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             when "0101" =>
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                    phy_addr := dat_reg5;
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             when "0110" =>
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                    phy_addr := dat_reg6;
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             when "0111" =>
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                    phy_addr := dat_reg7;
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             when "1000" =>
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                    phy_addr := dat_reg8;
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             when "1001" =>
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                    phy_addr := dat_reg9;
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             when "1010" =>
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                    phy_addr := dat_reg10;
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             when "1011" =>
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                    phy_addr := dat_reg11;
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             when "1100" =>
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                    phy_addr := dat_reg12;
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             when "1101" =>
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                    phy_addr := dat_reg13;
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             when "1110" =>
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                    phy_addr := dat_reg14;
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             when "1111" =>
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                    phy_addr := dat_reg15;
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        when others =>
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                    null;
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                end case;
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      data_out( 7 downto 4 ) <= phy_addr( 7 downto 4 );
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      data_out( 3 downto 0 ) <= not( phy_addr( 3 downto 0 ) );
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end process;
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end rtl;
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