OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [rev_86/] [rtl/] [VHDL/] [spp.vhd] - Blame information for rev 161

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 65 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    spp - Simple Parallel Port
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : spp.vhd
9
--
10
-- Purpose        : Simple Parallel Port for System09
11
--
12
-- Dependencies   : ieee.Std_Logic_1164
13
--                  ieee.std_logic_unsigned
14
--
15
-- Uses           : None
16
--
17
-- Author         : John E. Kent      
18
--                  dilbert57@opencores.org      
19
--
20
--===========================================================================----
21
--
22
-- Revision History:
23
--===========================================================================--
24
--
25
-- Version 0.1 - 6th Sep 2008
26
--  Generated from ioport.vhd
27
--
28
--===========================================================================
29
--
30
--  Parallel printer port pin assignment
31
-- 
32
--  Pin No (DB25) SPP Signal      EPP Signal    Direction Register  Bit Inverted
33
--  1             nStrobe            Write_n       Out       Control-0 Yes
34
--  2             Data0           Data0         In/Out    Data-0        No
35
--  3             Data1           Data1         In/Out    Data-1        No
36
--  4             Data2           Data2         In/Out    Data-2        No
37
--  5             Data3           Data3         In/Out    Data-3        No
38
--  6             Data4           Data4         In/Out    Data-4        No
39
--  7             Data5           Data5         In/Out    Data-5        No
40
--  8             Data6           Data6         In/Out    Data-6        No
41
--  9             Data7           Data7         In/Out    Data-7        No
42
--  10            nAck            Interrupt     In        Status-6  No
43
--  11            Busy            Wait          In        Status-7  Yes
44
--  12            Paper-Out       Spare         In        Status-5  No
45
--  13            Select          Spare         In        Status-4  No
46
-- 
47
--  14            Linefeed        Data_Strobe_n Out       Control-1 Yes
48
--  15            nError          Spare         In        Status-3  No
49
--  16             nInitialize     Reset         Out       Control-2 No
50
--  17             nSelect-Printer Addr_Strobe_n Out       Control-3 Yes
51
--  18-25          Ground          Ground        -         -         -
52
-- 
53
--  Address                              MSB                         LSB
54
--                                 Bit:    7   6   5   4   3   2   1   0
55
-- Base   (SPP Data port)    Write Pin:          9   8   7   6   5   4   3   2
56
-- Base+1 (SPP Status port)  Read  Pin:  ~11  10  12  13  15                            
57
-- Base+2 (SPP Control port) Write Pin:                  ~17  16 ~14  ~1
58
-- Base+3 (EPP Address port) R/W
59
-- Base+4 (EPP Data port)    R/W
60
-- 
61
--  ~ indicates a hardware inversion of the bit.
62
-- 
63
 
64
library ieee;
65
  use ieee.std_logic_1164.all;
66
  use ieee.std_logic_unsigned.all;
67
 
68
entity spp is
69
        port (
70
         clk       : in  std_logic;
71
    rst       : in  std_logic;
72
    cs        : in  std_logic;
73
    rw        : in  std_logic;
74
    addr      : in  std_logic_vector(2 downto 0);
75
    data_in   : in  std_logic_vector(7 downto 0);
76
         data_out  : out std_logic_vector(7 downto 0);
77
         spp_data  : out std_logic_vector(7 downto 0);
78
         spp_stat  : in  std_logic_vector(7 downto 3);
79
         spp_ctrl  : out std_logic_vector(3 downto 0);
80
         hold      : out std_logic;
81
    irq       : out std_logic
82
         );
83
end;
84
 
85
architecture rtl of spp is
86
 
87
signal spp_data_reg : std_logic_vector(7 downto 0);
88
signal spp_stat_reg : std_logic_vector(7 downto 3);
89
signal spp_ctrl_reg : std_logic_vector(3 downto 0);
90
 
91
begin
92
 
93
 
94
--------------------------------
95
--
96
-- read I/O port
97
--
98
--------------------------------
99
 
100
spp_read : process( addr,
101
                    spp_data_reg, spp_stat_reg, spp_ctrl_reg,
102
                                                  spp_stat )
103
begin
104
      spp_stat_reg(6 downto 3) <=     spp_stat(6 downto 3);
105
      spp_stat_reg(7)          <= not spp_stat(7);
106
      case addr is
107
             when "000" =>
108
          data_out <= spp_data_reg;
109
 
110
                  when "001" =>
111
          data_out <= spp_stat_reg & "000";
112
 
113
             when "010" =>
114
                    data_out <= "0000" & spp_ctrl_reg;
115
 
116
                  when others =>
117
                    data_out <= (others=> '0');
118
                end case;
119
      hold <= '0';
120
                irq  <= '0';
121
end process;
122
 
123
---------------------------------
124
--
125
-- Write I/O ports
126
--
127
---------------------------------
128
 
129
spp_write : process( clk, rst, addr, cs, rw, data_in,
130
                     spp_data_reg, spp_ctrl_reg )
131
begin
132
  if clk'event and clk = '0' then
133
    if rst = '1' then
134
      spp_data_reg <= "00000000";
135
      spp_ctrl_reg <= "0000";
136
    elsif cs = '1' and rw = '0' then
137
      case addr is
138
             when "000" =>
139
                    spp_data_reg <= data_in;
140
                  when "010" =>
141
                    spp_ctrl_reg <= data_in(3 downto 0);
142
                  when others =>
143
                    null;
144
                end case;
145
         end if;
146
  end if;
147
  spp_data    <=     spp_data_reg;
148
  spp_ctrl(0) <= not spp_ctrl_reg(0);
149
  spp_ctrl(1) <= not spp_ctrl_reg(1);
150
  spp_ctrl(2) <=     spp_ctrl_reg(2);
151
  spp_ctrl(3) <= not spp_ctrl_reg(3);
152
end process;
153
 
154
end rtl;
155
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.