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[/] [System09/] [rev_86/] [rtl/] [VHDL/] [vdu8.vhd] - Blame information for rev 141

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1 19 dilbert57
-- ---------------------------------------------------
2
-- Video Display terminal
3
-- ---------------------------------------------------
4
-- John Kent
5
-- 3th September 2004
6
-- Assumes a pixel clock input of 25 MHz
7
--
8
-- Display Format is:
9
-- 80 characters across by 25 characters down.
10
-- 8 horizontal pixels / character
11
-- 16 vertical scan lines / character (2 scan lines/row)
12
--
13
-- Modified by Bert Cuzeau for compliance and code cleanliness
14
-- The effort is not over.
15
-- There are still signal initialized, which is BAD.\
16
--
17
-- 7th Februaury 2007 - John Kent
18
-- Added generics for VGA Timing
19
--
20
 
21
Library IEEE;
22
  use IEEE.std_logic_1164.all;
23
  use IEEE.numeric_std.all;
24
Library unisim;
25
  use unisim.vcomponents.all;
26
 
27
Entity vdu8 is
28
  generic(
29
        VDU_CLOCK_FREQUENCY    : integer := 12500000; -- HZ
30
        VGA_CLOCK_FREQUENCY    : integer := 25000000; -- HZ
31
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
32
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
33
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
34
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
35
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
36
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
37
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
38
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
39
             VGA_VER_SYNC           : integer := 1;  -- LINES
40
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
41
  );
42
  port(
43
    -- control register interface
44
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
45
    vdu_rst      : in  std_logic;
46
    vdu_cs       : in  std_logic;
47
    vdu_rw       : in  std_logic;
48
    vdu_addr     : in  std_logic_vector(2 downto 0);
49
    vdu_data_in  : in  std_logic_vector(7 downto 0);
50
    vdu_data_out : out std_logic_vector(7 downto 0);
51
 
52
    -- vga port connections
53
    vga_clk      : in  std_logic;       -- 25MHz clock
54
    vga_red_o    : out std_logic;
55
    vga_green_o  : out std_logic;
56
    vga_blue_o   : out std_logic;
57
    vga_hsync_o  : out std_logic;
58
    vga_vsync_o  : out std_logic
59
    );
60
end vdu8;
61
 
62
Architecture RTL of vdu8 is
63
  --
64
  -- Synchronisation constants
65
  --
66
  -- Displayed Characters per row
67
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
68
  -- Last horizontal pixel displayed
69
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_PIXELS_PER_CHAR) - 1;
70
  -- Start of horizontal synch pulse
71
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_BACK_PORCH;
72
  -- End of Horizontal Synch pulse
73
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
74
  -- Last pixel in scan line
75
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_FRONT_PORCH;
76
 
77
  -- Displayed Characters per Column
78
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
79
  -- last row displayed
80
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_LINES_PER_CHAR) - 1;
81
  -- start of vertical synch pulse
82
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_BACK_PORCH;
83
  -- end of vertical synch pulse
84
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
85
  -- Last scan row in the frame
86
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_FRONT_PORCH;
87
 
88
  signal horiz_sync    : std_logic := '1';
89
  signal vert_sync     : std_logic := '1';
90
  signal cursor_on_v   : std_logic;
91
  signal cursor_on_h   : std_logic;
92
  signal video_on_v    : std_logic := '0';
93
  signal video_on_h    : std_logic := '0';
94
  signal h_count       : std_logic_vector(9 downto 0) := (others=>'0');
95
  signal v_count       : std_logic_vector(8 downto 0) := (others=>'0');  -- 0 to VER_SCAN_END
96
  signal blink_count   : std_logic_vector(22 downto 0):= (others=>'1');
97
  --
98
  -- Character generator ROM
99
  --
100
  signal char_addr     : std_logic_vector(10 downto 0);
101
  signal char_data_out : std_logic_vector(7 downto 0);
102
 
103
  --
104
  -- Control Registers
105
  --
106
  signal reg_character : std_logic_vector(7 downto 0);
107
  signal reg_colour    : std_logic_vector(7 downto 0);
108
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
109
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
110
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
111
  --
112
  -- Video Shift register
113
  --
114
  signal vga_shift     : std_logic_vector(7 downto 0);
115
  signal vga_fg_colour : std_logic_vector(2 downto 0);
116
  signal vga_bg_colour : std_logic_vector(2 downto 0);
117
  signal cursor_on     : std_logic;
118
  signal cursor_on1    : std_logic;
119
  signal video_on      : std_logic := '0';
120
  signal video_on1     : std_logic := '0';
121
  signal video_on2     : std_logic := '0';
122
  --
123
  -- vga character ram access bus
124
  --
125
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
126
  signal row_addr      : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 -1)
127
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
128
  signal row1_addr     : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
129
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
130
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
131
  signal vga0_cs       : std_logic;
132
  signal vga0_rw       : std_logic;
133
  signal vga1_cs       : std_logic;
134
  signal vga1_rw       : std_logic;
135
  signal vga2_cs       : std_logic;
136
  signal vga2_rw       : std_logic;
137
  signal vga_cs        : std_logic;
138
  signal vga_rw        : std_logic;
139
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
140
  signal vga_data_out  : std_logic_vector(7 downto 0);
141
  signal attr_data_out : std_logic_vector(7 downto 0);
142
  --
143
  -- Character write handshake signals
144
  --
145
  signal req_write     : std_logic;     -- request character write
146
  signal ack_write     : std_logic;
147
 
148
  --
149
  -- Block Ram Character gen
150
  --
151
  component char_rom
152
    port (
153
      clk   : in  std_logic;
154
      rst   : in  std_logic;
155
      cs    : in  std_logic;
156
      rw    : in  std_logic;
157
      addr  : in  std_logic_vector (10 downto 0);
158
      wdata : in std_logic_vector (7 downto 0);
159
      rdata : out std_logic_vector (7 downto 0)
160
      );
161
  end component;
162
 
163
  component ram_2k
164
    port (
165
      clk   : in  std_logic;
166
      rst   : in  std_logic;
167
      cs    : in  std_logic;
168
--      r_wn  : in  std_logic;
169
      rw    : in  std_logic;
170
      addr  : in  std_logic_vector (10 downto 0);
171
      wdata : in  std_logic_vector (7 downto 0);
172
      rdata : out std_logic_vector (7 downto 0)
173
      );
174
  end component;
175
 
176
begin
177
 
178
--
179
-- instantiate Character generator ROM
180
--
181
vdu_char_rom : char_rom port map(
182
    clk   => vga_clk,
183
         rst   => vdu_rst,
184
         cs    => '1',
185
         rw    => '1',
186
    addr  => char_addr,
187
    wdata => "00000000",
188
    rdata => char_data_out
189
    );
190
 
191
--
192
-- Character buffer RAM
193
--
194
char_buff_ram : ram_2k port map(
195
    clk   => vga_clk,
196
    rst   => vdu_rst,
197
    cs    => vga_cs,
198
--    r_wn  => vga_rw,
199
    rw    => vga_rw,
200
    addr  => vga_addr,
201
    wdata => reg_character,
202
    rdata => vga_data_out
203
    );
204
 
205
--
206
-- Attribute buffer RAM
207
--
208
  attr_buff_ram : ram_2k port map(
209
    clk   => vga_clk,
210
    rst   => vdu_rst,
211
    cs    => vga_cs,
212
--    r_wn  => vga_rw,
213
    rw    => vga_rw,
214
    addr  => vga_addr,
215
    wdata => reg_colour,
216
    rdata => attr_data_out
217
    );
218
 
219
--
220
-- CPU Write interface
221
--
222
  vga_cpu_write : process(vdu_clk, vdu_rst)
223
  begin
224
    if vdu_rst = '1' then
225
      reg_character <= "00000000";
226
      reg_colour    <= "00000111";
227
      reg_hcursor   <= "0000000";
228
      reg_vcursor   <= "00000";
229
      reg_voffset   <= "00000";
230
      req_write     <= '0';
231
 
232
    elsif vdu_clk'event and vdu_clk = '0' then
233
      if (vdu_cs = '1') and (vdu_rw = '0') then
234
        case vdu_addr is
235
          when "000" =>
236
            reg_character <= vdu_data_in;
237
            req_write     <= '1';
238
          when "001" =>
239
            reg_colour    <= vdu_data_in;
240
          when "010" =>
241
            reg_hcursor   <= vdu_data_in(6 downto 0);
242
          when "011" =>
243
            reg_vcursor   <= vdu_data_in(4 downto 0);
244
          when others =>
245
            reg_voffset   <= vdu_data_in(4 downto 0);
246
        end case;
247
      else
248
 
249
        if (req_write = '1') and (ack_write = '1') then
250
          req_write <= '0';
251
        else
252
          req_write <= req_write;
253
        end if;
254
 
255
      end if;
256
    end if;
257
  end process;
258
--
259
-- CPU Read interface
260
--
261
  vga_cpu_read : process(vdu_addr, vdu_cs,
262
                          reg_character, reg_colour,
263
                          reg_hcursor, reg_vcursor, reg_voffset)
264
  begin
265
    case vdu_addr is
266
      when "000" =>
267
        vdu_data_out <= reg_character;
268
      when "001" =>
269
        vdu_data_out <= reg_colour;
270
      when "010" =>
271
        vdu_data_out <= "0" & reg_hcursor;
272
      when "011" =>
273
        vdu_data_out <= "000" & reg_vcursor;
274
      when others =>
275
        vdu_data_out <= "000" & reg_voffset;
276
    end case;
277
  end process;
278
 
279
--
280
-- Video memory access
281
--
282
  vga_addr_proc : process(vga_clk, vdu_rst)
283
  begin
284
 
285
    if vdu_rst = '1' then
286
      vga0_cs   <= '0';
287
      vga0_rw   <= '1';
288
      row_addr  <= "000000";
289
      col_addr  <= "0000000";
290
      --
291
      vga1_cs   <= '0';
292
      vga1_rw   <= '1';
293
      row1_addr <= "000000";
294
      col1_addr <= "0000000";
295
      --
296
      vga2_cs   <= '0';
297
      vga2_rw   <= '1';
298
      ver_addr  <= "0000000";
299
      hor_addr  <= "0000000";
300
      --
301
      vga_cs    <= '0';
302
      vga_rw    <= '1';
303
      vga_addr  <= "00000000000";
304
 
305
    elsif vga_clk'event and vga_clk = '0' then
306
      --
307
      -- on h_count = 0 initiate character write.
308
      -- all other cycles are reads.
309
      --
310
      case h_count(2 downto 0) is
311
        when "000" =>                   -- pipeline character write
312
          vga0_cs  <= req_write;
313
          vga0_rw  <= '0';
314
          col_addr <= reg_hcursor(6 downto 0);
315
          row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
316
        when others =>                  -- other 6 cycles free
317
          vga0_cs  <= '1';
318
          vga0_rw  <= '1';
319
          col_addr <= h_count(9 downto 3);
320
          row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
321
      end case;
322
      --
323
      -- on vga_clk + 1 round off row address
324
      --
325
      vga1_cs <= vga0_cs;
326
      vga1_rw <= vga0_rw;
327
      if row_addr < VER_DISP_CHR then
328
        row1_addr <= row_addr;
329
      else
330
        row1_addr <= row_addr - VER_DISP_CHR;
331
      end if;
332
      col1_addr <= col_addr;
333
      --
334
      -- on vga_clk + 2 calculate vertical address
335
      --
336
      vga2_cs   <= vga1_cs;
337
      vga2_rw   <= vga1_rw;
338
      ver_addr  <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
339
      hor_addr  <= col1_addr;
340
      --
341
      -- on vga_clk + 3 calculate memory address
342
      --
343
      vga_cs    <= vga2_cs;
344
      vga_rw    <= vga2_rw;
345
      vga_addr  <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
346
    end if;
347
  end process;
348
--
349
-- Video shift register
350
--
351
  vga_shift_proc : process( vga_clk, vdu_rst)
352
  begin
353
    if vdu_rst = '1' then
354
      ack_write     <= '0';
355
      video_on2     <= '0';
356
      video_on      <= '0';
357
      cursor_on     <= '0';
358
      vga_bg_colour <= "000";
359
      vga_fg_colour <= "111";
360
      vga_shift     <= "00000000";
361
      vga_red_o     <= '0';
362
      vga_green_o   <= '0';
363
      vga_blue_o    <= '0';
364
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
365
 
366
    elsif vga_clk'event and vga_clk = '0' then
367
      -- Character Data valid on 1 count
368
      if h_count(2 downto 0) = "000" then
369
        if (req_write = '1') and (ack_write = '0') then
370
          ack_write <= '1';
371
        elsif (req_write = '0') and (ack_write = '1') then
372
          ack_write <= '0';
373
        else
374
          ack_write <= ack_write;
375
        end if;
376
        video_on2     <= video_on1;
377
        video_on      <= video_on2;
378
        cursor_on     <= (cursor_on1 or attr_data_out(3)) and blink_count(22);
379
        vga_fg_colour <= attr_data_out(2 downto 0);
380
        vga_bg_colour <= attr_data_out(6 downto 4);
381
        if attr_data_out(7) = '0' then
382
          vga_shift <= char_data_out;
383
        else
384
          case v_count(3 downto 2) is
385
            when "00" =>
386
              vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
387
              vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
388
            when "01" =>
389
              vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
390
              vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
391
            when "10" =>
392
              vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
393
              vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
394
            when others =>
395
              vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
396
              vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
397
          end case;
398
        end if;
399
      else
400
        vga_shift <= vga_shift(6 downto 0) & '0';
401
      end if;
402
 
403
      --
404
      -- Colour mask is
405
      --  7  6  5  4  3  2  1  0
406
      --  X BG BB BR  X FG FB FR
407
      --
408
      if vga_shift(7) = (not cursor_on) then
409
        vga_red_o   <= video_on and vga_fg_colour(0);
410
        vga_green_o <= video_on and vga_fg_colour(1);
411
        vga_blue_o  <= video_on and vga_fg_colour(2);
412
      else
413
        vga_red_o   <= video_on and vga_bg_colour(0);
414
        vga_green_o <= video_on and vga_bg_colour(1);
415
        vga_blue_o  <= video_on and vga_bg_colour(2);
416
      end if;
417
    end if;
418
  end process;
419
 
420
 
421
--
422
-- Sync generator & timing process
423
-- Generate Horizontal and Vertical Timing Signals for Video Signal
424
--
425
  vga_sync : process(vga_clk)
426
  begin
427
    if vga_clk'event and vga_clk = '0' then
428
      --
429
      -- H_count counts pixels (640 + extra time for sync signals)
430
      --
431
      --  Horiz_sync  -----------------------------__________--------
432
      --  H_count       0                640      659       755    799
433
      --
434
      if unsigned(h_count) = HOR_SCAN_END then
435
        h_count <= (others=>'0');
436
      else
437
        h_count <= std_logic_vector(unsigned(h_count) + 1);
438
      end if;
439
--
440
-- Generate Horizontal Sync Signal using H_count
441
--
442
      if unsigned(h_count) = HOR_SYNC_BEG then
443
        horiz_sync <= '0';
444
      elsif unsigned(h_count) = HOR_SYNC_END then
445
        horiz_sync <= '1';
446
      else
447
        horiz_sync <= horiz_sync;
448
      end if;
449
--
450
-- V_count counts rows of pixels
451
-- 400 lines + extra time for sync signals
452
-- 25 rows * 16 scan lines
453
--
454
--  Vert_sync      ---------------------------------_______------------
455
--  V_count         0                       400    413     414        444
456
--
457
      if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
458
        v_count <= "000000000";
459
      elsif unsigned(h_count) = HOR_SYNC_END then
460
        v_count <= std_logic_vector(unsigned(v_count) + 1);
461
      end if;
462
--
463
-- Generate Vertical Sync Signal using V_count
464
--
465
      if unsigned(v_count) = VER_SYNC_BEG then
466
        vert_sync <= '0';
467
      elsif unsigned(v_count) = VER_SYNC_END then
468
        vert_sync <= '1';
469
      else
470
        vert_sync <= vert_sync;
471
      end if;
472
 
473
-- Generate Video on Screen Signals for Pixel Data
474
      if unsigned(h_count) = HOR_SCAN_END then
475
        video_on_h <= '1';
476
      elsif unsigned(h_count) = HOR_DISP_END then
477
        video_on_h <= '0';
478
      else
479
        video_on_h <= video_on_h;
480
      end if;
481
 
482
      if unsigned(v_count) = VER_SCAN_END then
483
        video_on_v <= '1';
484
      elsif unsigned(v_count) = VER_DISP_END then
485
        video_on_v <= '0';
486
      else
487
        video_on_v <= video_on_v;
488
      end if;
489
 
490
 
491
      if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
492
        cursor_on_h <= '1';
493
      else
494
        cursor_on_h <= '0';
495
      end if;
496
 
497
      if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
498
        cursor_on_v <= '1';
499
      else
500
        cursor_on_v <= '0';
501
      end if;
502
 
503
      -- cursor_on is only active when on selected character
504
      blink_count <= std_logic_vector(unsigned(blink_count) + 1);
505
    end if;
506
 
507
  end process;
508
 
509
  -- video_on is high only when RGB data is displayed
510
  vga_hsync_o <= horiz_sync;
511
  vga_vsync_o <= vert_sync;
512
  video_on1   <= video_on_H and video_on_V;
513
  cursor_on1  <= cursor_on_h and cursor_on_v;
514
 
515
--
516
-- Here to look up character ROM
517
-- This will take one clock cycle
518
-- and should be performed on h_count = "111"
519
--
520
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
521
  char_addr(3 downto 0)  <= v_count(3 downto 0);
522
 
523
end RTL;

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