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[/] [System09/] [rev_86/] [src/] [upld/] [upld_cf8.asm] - Blame information for rev 203

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*
** FLEX 9 DISK DRIVERS
*
* FOR SYS09BUG ON THE DIGILENT SPARTAN 3 STARTER BOARD
* WITH I/O MAPPED AT $XE000
* AND ROM MAPPED AT $XF000
* THE DIGILENT SPARTAN 3 STARTER BOARD HAS 1MBYTE OF SRAM
* THE FIRST 64K IS USED BY FLEX,
* THE SECOND 128K IS USED AS A ROM DISK
* THE REMAINING RAM IS USED FOR A RAM DISK
*
*
CFLAG   EQU $01     CARRY FLAG
VFLAG   EQU $02     OVERFLOW FLAG
ZFLAG   EQU $04     ZERO FLAG
NFLAG   EQU $08     NEGATIVE FLAG
IFLAG   EQU $10     IRQ MASK CC
HFLAG   EQU $20     HALF CARRY
FFLAG   EQU $40     FIRQ MASK CC
EFLAG   EQU $80     ENTIRE FLAG
*
MAPPAG  EQU $00     PAGE $0000 DAT ADDRESS
*
* Serial Port
*
ACIAS   EQU $E000
ACIAC1  EQU ACIAS
ACIAD1  EQU ACIAS+1
DELCON  EQU 1250    Delay (Processor clock in MHz * 50)
*
* XMODEM Control characters
*
SOH     EQU $01
EOT     EQU $04
ACK     EQU $06
NAK     EQU $15
CAN     EQU $18
*
* Some dummy Constants
*
RMAXTRK EQU 48
RMAXSEC EQU 14
RTOTSEC EQU RMAXTRK*RMAXSEC-RMAXSEC
*
* Start
*
        ORG $0100
START   LBSR  UXSUB
        JMP  [$F800]  Jump to monitor on Completion.
*
*
* RAM SPACE
*
DRVNUM  FCB  0
TRACK   FCB  0
SECTOR  FCB  0
CHKSUM  FCB  0
BLKNUM  FCB  0 Xmodem block number
BYTCNT  FCB  0 Xmodem byte count
XSTATE  FDB  0 Xmodem State Vector
DELCNT  FCB  $00,$00,$00 Xmodem Poll timer
MAXTRK  FCB  0
MAXSEC  FCB  0
        ORG  $0200
*
* SECTOR BUFFER
*
BUFFER  RMB  256
*
* ACIA INPUT TEST
*
INTEST  LDA ACIAC1
        BITA #$01
        RTS
*
* RESET ACIA
*
ACIRST  LDA #$03 master reset
        STA  ACIAC1
        LDA #$11
        STA ACIAC1
        RTS
*
* ACIA INPUT
*
INTER   LDA  #16
        STA  DELCNT+0
        CLR  DELCNT+1
        CLR  DELCNT+2
INTER0  LDA  ACIAC1
        BITA #$01
        BNE  INTER1
        BITA #$78
        BEQ  INTER2
        BSR  ACIRST
        BRA  INTER
*
INTER1  LDA  ACIAD1
        ANDCC #$FF-VFLAG
        RTS
*
INTER2  DEC  DELCNT+2
        BNE  INTER0
        DEC  DELCNT+1
        BNE  INTER0
        DEC  DELCNT+0
        BNE  INTER0
        CLRA
        ORCC #VFLAG
        RTS
*
* ACIA OUTPUT
*
OUTTER  PSHS A
*
OUTTE1  LDA ACIAC1
        BITA #$02
        BNE  OUTTE2
        BITA #$78
        BEQ  OUTTE1
        BSR  ACIRST
        BRA  OUTTE1
*
OUTTE2  PULS A
        STA ACIAD1
        RTS
*
* Print Data
*
PDATA0  BSR  OUTTER
PDATA1  LDA  ,X+
        CMPA #$04
        BNE  PDATA0
        RTS
*
** 'UX' Xmodem ROM Disk upload
*
UXMES0  FCB $0D,$0A
        FCC 'Xmodem ROM Disk Upload'
        FCB 4
UXMES1  FCB $0D,$0A
        FCC 'Upload Complete'
        FCB 4
UXMES2  FCB $0D,$0A
        FCC 'Upload Error'
        FCB 4
UXMSG3  FCB $0D,$0A
        FCC 'Drive Number :'
        FCB 4
UXMSG4  FCB $0D,$0A
        FCC 'Are You Sure ? (Y/N)'
        FCB 4
*
* Print Banner
*
UXSUB   LDX #UXMES0
        LBSR PDATA1
*
* Prompt for Disk drive number (0 to 3)
*
        LDX #UXMSG3
        LBSR PDATA1
UXSUB1  LBSR INTER
        BVS  UXSUB1
        LBSR OUTTER
        CMPA #'0
        LBLO UXEXIT
        CMPA #'3
        LBHI UXEXIT
        SUBA #'0
        STA  DRVNUM
*
* Report selected drive
*
        LDX #UXMSG3
        LBSR PDATA1
        LDA  DRVNUM
        ADDA #'0
        LBSR OUTTER
*
* Ask for confirmation (Y/N)
*
        LDX #UXMSG4
        LBSR PDATA1
UXSUB2  LBSR INTER
        BVS  UXSUB2
        LBSR OUTTER
        ANDA #$5F
        CMPA #'N
        LBEQ UXEXIT
        CMPA #'Y
        BNE  UXSUB
*
* We have confirmation ... now load the disk image
*
        LBSR INITDR
        LDU  #XSTST
        STU  XSTATE
        LDA  #1
        STA  BLKNUM
*
* Sector1
*
        LDX  #BUFFER
*
        CLRA         TRACK 0
        LDB  #$01    SECTOR 1
        STA  TRACK
        STB  SECTOR
*
        LBSR XREAD
        LBCS UXERR
        LBSR XACK
        LBSR XREAD
        LBCS UXERR
*
        LDX  #BUFFER
        LDA  TRACK
        LDB  SECTOR
        LBSR WRITSC
        LBSR XACK
*
* Sector 2
*
        LDX  #BUFFER
*
        LDA  TRACK
        LDB  SECTOR
        INCB
        STA  TRACK
        STB  SECTOR
*
        LBSR XREAD
        LBCS UXERR
        LBSR XACK
        LBSR XREAD
        LBCS UXERR
*
        LDX  #BUFFER
        LDA  TRACK
        LDB  SECTOR
        LBSR WRITSC
*
        LBSR XACK
*
* Sector 3 - SIR
*
        LDX  #BUFFER
*
        LDA  TRACK
        LDB  SECTOR
        INCB
        STA  TRACK
        STB  SECTOR
*
        LBSR XREAD
        LBCS UXERR
        LBSR XACK
        LBSR XREAD
        LBCS UXERR
*
        LDX  #BUFFER
        LDA  38,X
        INCA
        STA  MAXTRK
        LDB  39,X
        INCB
        STB  MAXSEC
        LDA  TRACK
        LDB  SECTOR
        LBSR WRITSC
*
        LBSR XACK
*
* Sector 4 to Last Track & Sector
*
*
        LDA  TRACK
        LDB  SECTOR
        INCB
*
UXLOOP  LDX  #BUFFER
        STA  TRACK
        STB  SECTOR
*
        LBSR XREAD
        LBCS UXERR
        LBSR XACK
        LBSR XREAD
        LBCS UXERR
*
        LDX  #BUFFER
        LDA  TRACK
        LDB  SECTOR
        LBSR WRITSC
        LBSR XACK
*
        LDA  TRACK
        LDB  SECTOR
        INCB
        CMPB MAXSEC
        BNE  UXLOOP
        LDB  #1
        INCA
        CMPA MAXTRK
        BNE  UXLOOP
*
*
*  Write Boot sector
*
        LDX  #$C000
        CLRA         TRACK 0
        LDB  #$01    SECTOR 1
        STA  TRACK
        STB  SECTOR
        LBSR WRITSC
*
UXEXIT  LDX  #UXMES1
        JMP  PDATA1
*
UXERR   LDX  #UXMES2
        LBRA PDATA1
*
* Get a Byte using XModem protocol
* Carry clear => no errors
* Carry set   => errors
*
XREAD   PSHS U
        LDU  XSTATE
*
XBYTE0  LBSR INTER
        BVC  XBYTE1
        LDA  #NAK
        LBSR OUTTER
        LDU  #XSTST
        BRA  XBYTE0
*
XBYTE1  JSR  ,U
        BNE  XBYTE0
        STU  XSTATE
        PULS U,PC
*
* START - LOOK FOR SOH (START OF HEADER) = $01
*
XSTST   CMPA #SOH
        BNE  XSTST1
        LDU  #XSTBL
        ANDCC #$FF-CFLAG-ZFLAG No abort, no valid data (no exit)
        RTS
*
XSTST1  CMPA #EOT
        BNE  XSTST2
        LDA  #ACK
        LBSR OUTTER
        ORCC  #CFLAG+ZFLAG  Set (c)=1 abort & exit
        RTS
*
XSTST2  CMPA #CAN
        BNE  XSTST3
        ORCC  #CFLAG+ZFLAG  Set (c)=1 abort & exit
        RTS
*
XSTST3  ANDCC #$FF-CFLAG-ZFLAG
        RTS
*
* Got SOH
* Now get block number
*
XSTBL   CMPA BLKNUM
        BNE  XSTBLE
        LDU  #XSTCOM
        ANDCC #$FF-CFLAG-ZFLAG No abort, No valid data (no exit)
        RTS
*
* Error in block number
*
XSTBLE  LDA  #NAK
        LBSR OUTTER
        LDU  #XSTST
        ANDCC #$FF-CFLAG-ZFLAG No abort, No valid data (no exit)
        RTS
*
* Get complement of block number
*
XSTCOM  COMA
        CMPA BLKNUM
        BNE  XSTBLE
        CLR  CHKSUM
        LDA  #128
        STA  BYTCNT
        LDU  #XSTDA
        ANDCC #$FF-CFLAG-ZFLAG No abort, No valid data (no exit)
        RTS
*
* Get data bytes
*
XSTDA   PSHS A
        ADDA CHKSUM
        STA  CHKSUM
        PULS A
        DEC  BYTCNT
        BNE  XSTDA1
        LDU  #XSTCK
XSTDA1  STA  ,X+
        ANDCC #$FF-CFLAG-ZFLAG No abort, no valid data (no exit)
        RTS
*
* Byte count reached zero
* Check checksum byte
*
XSTCK   CMPA CHKSUM
        BNE  XSTCK1 retry if wrong checksum
*
* Checksum OK ...
* increment block number
* Don't send ACK until data written to CF
*
        INC  BLKNUM
        LDU  #XSTST
        ANDCC #$FF-CFLAG No abort
        ORCC #ZFLAG      Valid data (exit)
        RTS
*
* Checksum Error detected ...
* Reset Sector counter in ACCB to last 128 byte boundary
* and send NAK
*
XSTCK1  PSHS B
        TFR  X,D
        DECB
        ANDB #128
        TFR  D,X
        PULS B
        LDA  #NAK
XSTCK2  LBSR OUTTER
        LDU  #XSTST
        ANDCC #$FF-CFLAG-ZFLAG No abort, no valid data (no exit)
        RTS
*
* Acknowledge Data Received
*
XACK    PSHS A
        LDA  #ACK
        LBSR OUTTER
        PULS A,PC
*
*
** FLEX 9 COMPACT FLASH DISK DRIVERS
*
* FOR SYS09BUG 1.2 ON THE BURCHED B5-X300
* WITH I/O MAPPED AT $XE000
* AND ROM MAPPED AT $XF000
* THE BURCHED B5-X300 HAS 256KBYTES OF SRAM
* THE FIRST 64K IS USED BY FLEX,
* THE SECOND 192K MAY BE USED AS A RAM DISK
*
*
IMASK  EQU $10     IRQ MASK CC
FMASK  EQU $40     FIRQ MASK CC
DATREG EQU $FFF0   DAT REGISTERS
*
CF_BASE    EQU $E040
CF_DATA    EQU CF_BASE+0
CF_ERROR   EQU CF_BASE+1 ; read error
CF_FEATURE EQU CF_BASE+1 ; write feature
CF_SCNT    EQU CF_BASE+2
CF_SNUM    EQU CF_BASE+3
CF_CLO     EQU CF_BASE+4
CF_CHI     EQU CF_BASE+5
CF_HEAD    EQU CF_BASE+6
CF_STATUS  EQU CF_BASE+7 ; read status
CF_COMAND  EQU CF_BASE+7 ; write command
*
* Command Equates
*
CMDREAD    EQU $20 ; Read Single sector
CMDWRITE   EQU $30 ; Write Single sector
CMDFEATURE EQU $EF
FEAT8BIT   EQU $01 ; enable 8 bit transfers
HEADLBA    EQU $E0
*
* Status bit equates
*
BSY        EQU $80
DRDY       EQU $40
DRQ        EQU $08
ERR        EQU $01
*
*
* INITIALIZE CF CARD FOR 8 BIT LBA MODE
*
INITDR BSR WAITRDY
       LDA  #HEADLBA
       STA  CF_HEAD
       LDA #FEAT8BIT
       STA CF_FEATURE
       LDA #CMDFEATURE
       STA CF_COMAND
       BRA WAITRDY
*
* Seek track and sector
* A holds track number (0 - ??)
* B holds sector number (1 - ??)
* Sector numbers starts from 1
* subtract 1 to start from sector 0 on CF
*
SEEKTS DECB
       STB  CF_SNUM
       STA  CF_CLO
       LDB  DRVNUM
       STB  CF_CHI
       LDB  #$01
       STB  CF_SCNT
       CLRB
       RTS
*
* READ SECTORS FROM CF
*
*
READSC BSR  SEEKTS
       LDA  #CMDREAD ; IDE READ MULTIPLE
       STA  CF_COMAND
       BSR  WAITRDY
*
* READ LOOP
*
       CLRB
RDLP1  BSR  WAITDRQ
       LDA  CF_DATA
       STA  ,X+
       DECB
       BNE  RDLP1
*
       CLRB
RDLP2  BSR  WAITDRQ
       LDA  CF_DATA
       DECB
       BNE  RDLP2
*
       BSR  WAITRDY
       CLRB
       RTS
*
* WRITE SECTOR TO CF
*
WRITSC BSR  SEEKTS   ; SEEK TRACK & SECTOR
       LDA  #CMDWRITE ; IDE WRITE MULTIPLE
       STA  CF_COMAND
       BSR  WAITRDY
*
* WRITE LOOP
*
       CLRB
WRTLP1 BSR  WAITDRQ
       LDA  ,X+
       STA  CF_DATA
       DECB
       BNE  WRTLP1
*
       CLRB
WRTLP2 BSR  WAITDRQ
       CLRA
       STA  CF_DATA
       DECB
       BNE WRTLP2
*
       BSR  WAITRDY
       CLRB
       RTS
*
* CHECK FOR BUSY
* Doubles as VERIFY
*
BUSY   CLRB            Never busy
       RTS
*
* DRIVE SELECT DISK DRIVER
*
DRVSEL LDA   3,X       GET DRIVE # FROM FCB
       CMPA  #3
       BLS   DRVS2     IF > 3, SET IT TO 0
       CLRA
DRVS2  STA   DRVNUM
       CLRB            ; SET Z, CLEAR C
       RTS
*
* CHECK DRIVE READY DISK DRIVER
*
CHKDRV LDA  3,X
       CLRB             ; CLEAR C, SET Z
       RTS
*
* WAIT UNTIL READY
*
WAITRDY LDA  CF_STATUS
        BITA #BSY
        BNE  WAITRDY
        LDA  CF_STATUS
        BITA #DRDY
        BEQ  WAITRDY
        RTS
*
* WAIT FOR DATA REQUEST
*
WAITDRQ LDA  CF_STATUS
        BITA #DRQ
        BEQ  WAITDRQ
        RTS
*
*******************************************************
*
* Bootstrap FLEX Loader
*
* SBUG1.8 loads the bootstap loader at $C000
* however the Flex adaption manual has the
* bootstrap loader residing at $C100
*
******************************************************
*
* Equates
*
STACK   EQU $C0FF
SCTBUF  EQU $C300
*
* Start of Utility
*
        ORG $C000
BOOT    BRA LOAD0
        FCB 0,0,0
TRK     FCB 0        File start track
SCT     FCB 0        File start sector
DNS     FCB 0        Density Flag (not used)
TADR    FDB $C000    Transfer address
LADR    FDB 0        Load Address
DRNUM   FCB 0        Drive number 0
*
LOAD0   LDS  #STACK   Set up stack
        LDD  TRK      Set up start track and sector
        STD  SCTBUF
        LDY  #SCTBUF+256
*
* Perform actual file load
*
LOAD1   BSR GETCH    Get acharcater
        CMPA #$02    Data record hearder ?
        BEQ  LOAD2   Skip, is so
        CMPA #$16    Xfr address hearder ?
        BNE LOAD1    Loop if neither
*
* Get transfer address
*
        BSR  GETCH
        STA  TADR
        BSR  GETCH
        STA  TADR+1
        BRA  LOAD1
*
* Load data record
*
LOAD2  BSR  GETCH  Get load address
       STA  LADR
       BSR  GETCH
       STA  LADR+1
       BSR  GETCH  Get Bytes count
       TFR  A,B
       TSTB
       BEQ  LOAD1 Loop if count = 0
       LDX  LADR  Get load address
LOAD3  PSHS B,X
       BSR  GETCH  Get data character
       PULS B,X
       STA  ,X+    Store at load address
       DECB
       BNE  LOAD3  Loop until count = 0
       BRA  LOAD1
*
* Get Character routine
* Reads a sector if needed
*
GETCH  CMPY #SCTBUF+256 out of data ?
       BNE  GETCH4      Go read Character if not
GETCH2 LDX  #SCTBUF     Point to buffer
       LDD  0,X         Get forward Link
       BEQ  GO          if zero, file is loaded
       BSR  READ        Read next sector
       BNE  BOOT        start over if error
       LDY  #SCTBUF+4   Point past link
GETCH4 LDA  ,Y+         Else, get a character
       RTS
*
* File is loaded, Jump to it
*
GO     JMP  [TADR]      Jump to transfer address
 
*
** FLEX 9 COMPACT FLASH DISK DRIVERS
*
* FOR SYS09BUG 1.2 ON THE BURCHED B5-X300
* WITH I/O MAPPED AT $XE000
* AND ROM MAPPED AT $XF000
* THE BURCHED B5-X300 HAS 256KBYTES OF SRAM
* THE FIRST 64K IS USED BY FLEX,
* THE SECOND 192K MAY BE USED AS A RAM DISK
*
*
*IMASK  EQU $10     IRQ MASK CC
*FMASK  EQU $40     FIRQ MASK CC
*DATREG EQU $FFF0   DAT REGISTERS
*
*CF_BASE    EQU $E040
*CF_DATA    EQU CF_BASE+0
*CF_ERROR   EQU CF_BASE+1 ; read error
*CF_FEATURE EQU CF_BASE+1 ; write feature
*CF_SCNT  EQU CF_BASE+2
*CF_SNUM  EQU CF_BASE+3
*CF_CLO   EQU CF_BASE+4
*CF_CHI   EQU CF_BASE+5
*CF_HEAD    EQU CF_BASE+6
*CF_STATUS  EQU CF_BASE+7 ; read status
*CF_COMAND  EQU CF_BASE+7 ; write command
*
* Command Equates
*
*CMDREAD    EQU $20 ; Read Single sector
*CMDWRITE   EQU $30 ; Write Single sector
*CMDFEATURE EQU $EF
*FEAT8BIT   EQU $01 ; enable 8 bit transfers
*HEADLBA    EQU $E0
*
* Status bit equates
*
*BSY        EQU $80
*DRDY       EQU $40
*DRQ        EQU $08
*ERR        EQU $01
*
* Seek track and sector
* A holds track number (0 - ??)
* B holds sector number (1 - ??)
* Sector numbers starts from 1
* subtract 1 to start from sector 0 on CF
*
SEEK   DECB
       STB  CF_SNUM
       STA  CF_CLO
       LDB  DRNUM
       STB  CF_CHI
       LDB  #$01
       STB  CF_SCNT
       CLRB
       RTS
*
* READ SECTORS FROM CF
*
*
READ   BSR  SEEK
       LDA  #CMDREAD ; IDE READ MULTIPLE
       STA  CF_COMAND
       BSR  WTRDY
*
* READ LOOP
*
       CLRB
READ1  BSR  WTDRQ
       LDA  CF_DATA
       STA  ,X+
       DECB
       BNE  READ1
*
       CLRB
READ2  BSR  WTDRQ
       LDA  CF_DATA
       DECB
       BNE  READ2
*
       BSR  WTRDY
       CLRB
       RTS
*
* WAIT UNTIL READY
*
WTRDY   LDA  CF_STATUS
        BITA #BSY
        BNE  WTRDY
        LDA  CF_STATUS
        BITA #DRDY
        BEQ  WTRDY
        RTS
*
* WAIT FOR DATA REQUEST
*
WTDRQ   LDA  CF_STATUS
        BITA #DRQ
        BEQ  WTDRQ
        RTS
*
       END START

Line No.	Rev	Author	Line
1	59	davidgb	`*`
2			`** FLEX 9 DISK DRIVERS`
3			`*`
4			`* FOR SYS09BUG ON THE DIGILENT SPARTAN 3 STARTER BOARD`
5			`* WITH I/O MAPPED AT $XE000`
6			`* AND ROM MAPPED AT $XF000`
7			`* THE DIGILENT SPARTAN 3 STARTER BOARD HAS 1MBYTE OF SRAM`
8			`* THE FIRST 64K IS USED BY FLEX,`
9			`* THE SECOND 128K IS USED AS A ROM DISK`
10			`* THE REMAINING RAM IS USED FOR A RAM DISK`
11			`*`
12			`*`
13			`CFLAG EQU $01 CARRY FLAG`
14			`VFLAG EQU $02 OVERFLOW FLAG`
15			`ZFLAG EQU $04 ZERO FLAG`
16			`NFLAG EQU $08 NEGATIVE FLAG`
17			`IFLAG EQU $10 IRQ MASK CC`
18			`HFLAG EQU $20 HALF CARRY`
19			`FFLAG EQU $40 FIRQ MASK CC`
20			`EFLAG EQU $80 ENTIRE FLAG`
21			`*`
22			`MAPPAG EQU $00 PAGE $0000 DAT ADDRESS`
23			`*`
24			`* Serial Port`
25			`*`
26			`ACIAS EQU $E000`
27			`ACIAC1 EQU ACIAS`
28			`ACIAD1 EQU ACIAS+1`
29			`DELCON EQU 1250 Delay (Processor clock in MHz * 50)`
30			`*`
31			`* XMODEM Control characters`
32			`*`
33			`SOH EQU $01`
34			`EOT EQU $04`
35			`ACK EQU $06`
36			`NAK EQU $15`
37			`CAN EQU $18`
38			`*`
39			`* Some dummy Constants`
40			`*`
41			`RMAXTRK EQU 48`
42			`RMAXSEC EQU 14`
43			`RTOTSEC EQU RMAXTRK*RMAXSEC-RMAXSEC`
44			`*`
45			`* Start`
46			`*`
47			`ORG $0100`
48			`START LBSR UXSUB`
49			`JMP [$F800] Jump to monitor on Completion.`
50			`*`
51			`*`
52			`* RAM SPACE`
53			`*`
54			`DRVNUM FCB 0`
55			`TRACK FCB 0`
56			`SECTOR FCB 0`
57			`CHKSUM FCB 0`
58			`BLKNUM FCB 0 Xmodem block number`
59			`BYTCNT FCB 0 Xmodem byte count`
60			`XSTATE FDB 0 Xmodem State Vector`
61			`DELCNT FCB $00,$00,$00 Xmodem Poll timer`
62			`MAXTRK FCB 0`
63			`MAXSEC FCB 0`
64			`ORG $0200`
65			`*`
66			`* SECTOR BUFFER`
67			`*`
68			`BUFFER RMB 256`
69			`*`
70			`* ACIA INPUT TEST`
71			`*`
72			`INTEST LDA ACIAC1`
73			`BITA #$01`
74			`RTS`
75			`*`
76			`* RESET ACIA`
77			`*`
78			`ACIRST LDA #$03 master reset`
79			`STA ACIAC1`
80			`LDA #$11`
81			`STA ACIAC1`
82			`RTS`
83			`*`
84			`* ACIA INPUT`
85			`*`
86			`INTER LDA #16`
87			`STA DELCNT+0`
88			`CLR DELCNT+1`
89			`CLR DELCNT+2`
90			`INTER0 LDA ACIAC1`
91			`BITA #$01`
92			`BNE INTER1`
93			`BITA #$78`
94			`BEQ INTER2`
95			`BSR ACIRST`
96			`BRA INTER`
97			`*`
98			`INTER1 LDA ACIAD1`
99			`ANDCC #$FF-VFLAG`
100			`RTS`
101			`*`
102			`INTER2 DEC DELCNT+2`
103			`BNE INTER0`
104			`DEC DELCNT+1`
105			`BNE INTER0`
106			`DEC DELCNT+0`
107			`BNE INTER0`
108			`CLRA`
109			`ORCC #VFLAG`
110			`RTS`
111			`*`
112			`* ACIA OUTPUT`
113			`*`
114			`OUTTER PSHS A`
115			`*`
116			`OUTTE1 LDA ACIAC1`
117			`BITA #$02`
118			`BNE OUTTE2`
119			`BITA #$78`
120			`BEQ OUTTE1`
121			`BSR ACIRST`
122			`BRA OUTTE1`
123			`*`
124			`OUTTE2 PULS A`
125			`STA ACIAD1`
126			`RTS`
127			`*`
128			`* Print Data`
129			`*`
130			`PDATA0 BSR OUTTER`
131			`PDATA1 LDA ,X+`
132			`CMPA #$04`
133			`BNE PDATA0`
134			`RTS`
135			`*`
136			`** 'UX' Xmodem ROM Disk upload`
137			`*`
138			`UXMES0 FCB $0D,$0A`
139			`FCC 'Xmodem ROM Disk Upload'`
140			`FCB 4`
141			`UXMES1 FCB $0D,$0A`
142			`FCC 'Upload Complete'`
143			`FCB 4`
144			`UXMES2 FCB $0D,$0A`
145			`FCC 'Upload Error'`
146			`FCB 4`
147			`UXMSG3 FCB $0D,$0A`
148			`FCC 'Drive Number :'`
149			`FCB 4`
150			`UXMSG4 FCB $0D,$0A`
151			`FCC 'Are You Sure ? (Y/N)'`
152			`FCB 4`
153			`*`
154			`* Print Banner`
155			`*`
156			`UXSUB LDX #UXMES0`
157			`LBSR PDATA1`
158			`*`
159			`* Prompt for Disk drive number (0 to 3)`
160			`*`
161			`LDX #UXMSG3`
162			`LBSR PDATA1`
163			`UXSUB1 LBSR INTER`
164			`BVS UXSUB1`
165			`LBSR OUTTER`
166			`CMPA #'0`
167			`LBLO UXEXIT`
168			`CMPA #'3`
169			`LBHI UXEXIT`
170			`SUBA #'0`
171			`STA DRVNUM`
172			`*`
173			`* Report selected drive`
174			`*`
175			`LDX #UXMSG3`
176			`LBSR PDATA1`
177			`LDA DRVNUM`
178			`ADDA #'0`
179			`LBSR OUTTER`
180			`*`
181			`* Ask for confirmation (Y/N)`
182			`*`
183			`LDX #UXMSG4`
184			`LBSR PDATA1`
185			`UXSUB2 LBSR INTER`
186			`BVS UXSUB2`
187			`LBSR OUTTER`
188			`ANDA #$5F`
189			`CMPA #'N`
190			`LBEQ UXEXIT`
191			`CMPA #'Y`
192			`BNE UXSUB`
193			`*`
194			`* We have confirmation ... now load the disk image`
195			`*`
196			`LBSR INITDR`
197			`LDU #XSTST`
198			`STU XSTATE`
199			`LDA #1`
200			`STA BLKNUM`
201			`*`
202			`* Sector1`
203			`*`
204			`LDX #BUFFER`
205			`*`
206			`CLRA TRACK 0`
207			`LDB #$01 SECTOR 1`
208			`STA TRACK`
209			`STB SECTOR`
210			`*`
211			`LBSR XREAD`
212			`LBCS UXERR`
213			`LBSR XACK`
214			`LBSR XREAD`
215			`LBCS UXERR`
216			`*`
217			`LDX #BUFFER`
218			`LDA TRACK`
219			`LDB SECTOR`
220			`LBSR WRITSC`
221			`LBSR XACK`
222			`*`
223			`* Sector 2`
224			`*`
225			`LDX #BUFFER`
226			`*`
227			`LDA TRACK`
228			`LDB SECTOR`
229			`INCB`
230			`STA TRACK`
231			`STB SECTOR`
232			`*`
233			`LBSR XREAD`
234			`LBCS UXERR`
235			`LBSR XACK`
236			`LBSR XREAD`
237			`LBCS UXERR`
238			`*`
239			`LDX #BUFFER`
240			`LDA TRACK`
241			`LDB SECTOR`
242			`LBSR WRITSC`
243			`*`
244			`LBSR XACK`
245			`*`
246			`* Sector 3 - SIR`
247			`*`
248			`LDX #BUFFER`
249			`*`
250			`LDA TRACK`
251			`LDB SECTOR`
252			`INCB`
253			`STA TRACK`
254			`STB SECTOR`
255			`*`
256			`LBSR XREAD`
257			`LBCS UXERR`
258			`LBSR XACK`
259			`LBSR XREAD`
260			`LBCS UXERR`
261			`*`
262			`LDX #BUFFER`
263			`LDA 38,X`
264			`INCA`
265			`STA MAXTRK`
266			`LDB 39,X`
267			`INCB`
268			`STB MAXSEC`
269			`LDA TRACK`
270			`LDB SECTOR`
271			`LBSR WRITSC`
272			`*`
273			`LBSR XACK`
274			`*`
275			`* Sector 4 to Last Track & Sector`
276			`*`
277			`*`
278			`LDA TRACK`
279			`LDB SECTOR`
280			`INCB`
281			`*`
282			`UXLOOP LDX #BUFFER`
283			`STA TRACK`
284			`STB SECTOR`
285			`*`
286			`LBSR XREAD`
287			`LBCS UXERR`
288			`LBSR XACK`
289			`LBSR XREAD`
290			`LBCS UXERR`
291			`*`
292			`LDX #BUFFER`
293			`LDA TRACK`
294			`LDB SECTOR`
295			`LBSR WRITSC`
296			`LBSR XACK`
297			`*`
298			`LDA TRACK`
299			`LDB SECTOR`
300			`INCB`
301			`CMPB MAXSEC`
302			`BNE UXLOOP`
303			`LDB #1`
304			`INCA`
305			`CMPA MAXTRK`
306			`BNE UXLOOP`
307			`*`
308			`*`
309			`* Write Boot sector`
310			`*`
311			`LDX #$C000`
312			`CLRA TRACK 0`
313			`LDB #$01 SECTOR 1`
314			`STA TRACK`
315			`STB SECTOR`
316			`LBSR WRITSC`
317			`*`
318			`UXEXIT LDX #UXMES1`
319			`JMP PDATA1`
320			`*`
321			`UXERR LDX #UXMES2`
322			`LBRA PDATA1`
323			`*`
324			`* Get a Byte using XModem protocol`
325			`* Carry clear => no errors`
326			`* Carry set => errors`
327			`*`
328			`XREAD PSHS U`
329			`LDU XSTATE`
330			`*`
331			`XBYTE0 LBSR INTER`
332			`BVC XBYTE1`
333			`LDA #NAK`
334			`LBSR OUTTER`
335			`LDU #XSTST`
336			`BRA XBYTE0`
337			`*`
338			`XBYTE1 JSR ,U`
339			`BNE XBYTE0`
340			`STU XSTATE`
341			`PULS U,PC`
342			`*`
343			`* START - LOOK FOR SOH (START OF HEADER) = $01`
344			`*`
345			`XSTST CMPA #SOH`
346			`BNE XSTST1`
347			`LDU #XSTBL`
348			`ANDCC #$FF-CFLAG-ZFLAG No abort, no valid data (no exit)`
349			`RTS`
350			`*`
351			`XSTST1 CMPA #EOT`
352			`BNE XSTST2`
353			`LDA #ACK`
354			`LBSR OUTTER`
355			`ORCC #CFLAG+ZFLAG Set (c)=1 abort & exit`
356			`RTS`
357			`*`
358			`XSTST2 CMPA #CAN`
359			`BNE XSTST3`
360			`ORCC #CFLAG+ZFLAG Set (c)=1 abort & exit`
361			`RTS`
362			`*`
363			`XSTST3 ANDCC #$FF-CFLAG-ZFLAG`
364			`RTS`
365			`*`
366			`* Got SOH`
367			`* Now get block number`
368			`*`
369			`XSTBL CMPA BLKNUM`
370			`BNE XSTBLE`
371			`LDU #XSTCOM`
372			`ANDCC #$FF-CFLAG-ZFLAG No abort, No valid data (no exit)`
373			`RTS`
374			`*`
375			`* Error in block number`
376			`*`
377			`XSTBLE LDA #NAK`
378			`LBSR OUTTER`
379			`LDU #XSTST`
380			`ANDCC #$FF-CFLAG-ZFLAG No abort, No valid data (no exit)`
381			`RTS`
382			`*`
383			`* Get complement of block number`
384			`*`
385			`XSTCOM COMA`
386			`CMPA BLKNUM`
387			`BNE XSTBLE`
388			`CLR CHKSUM`
389			`LDA #128`
390			`STA BYTCNT`
391			`LDU #XSTDA`
392			`ANDCC #$FF-CFLAG-ZFLAG No abort, No valid data (no exit)`
393			`RTS`
394			`*`
395			`* Get data bytes`
396			`*`
397			`XSTDA PSHS A`
398			`ADDA CHKSUM`
399			`STA CHKSUM`
400			`PULS A`
401			`DEC BYTCNT`
402			`BNE XSTDA1`
403			`LDU #XSTCK`
404			`XSTDA1 STA ,X+`
405			`ANDCC #$FF-CFLAG-ZFLAG No abort, no valid data (no exit)`
406			`RTS`
407			`*`
408			`* Byte count reached zero`
409			`* Check checksum byte`
410			`*`
411			`XSTCK CMPA CHKSUM`
412			`BNE XSTCK1 retry if wrong checksum`
413			`*`
414			`* Checksum OK ...`
415			`* increment block number`
416			`* Don't send ACK until data written to CF`
417			`*`
418			`INC BLKNUM`
419			`LDU #XSTST`
420			`ANDCC #$FF-CFLAG No abort`
421			`ORCC #ZFLAG Valid data (exit)`
422			`RTS`
423			`*`
424			`* Checksum Error detected ...`
425			`* Reset Sector counter in ACCB to last 128 byte boundary`
426			`* and send NAK`
427			`*`
428			`XSTCK1 PSHS B`
429			`TFR X,D`
430			`DECB`
431			`ANDB #128`
432			`TFR D,X`
433			`PULS B`
434			`LDA #NAK`
435			`XSTCK2 LBSR OUTTER`
436			`LDU #XSTST`
437			`ANDCC #$FF-CFLAG-ZFLAG No abort, no valid data (no exit)`
438			`RTS`
439			`*`
440			`* Acknowledge Data Received`
441			`*`
442			`XACK PSHS A`
443			`LDA #ACK`
444			`LBSR OUTTER`
445			`PULS A,PC`
446			`*`
447			`*`
448			`** FLEX 9 COMPACT FLASH DISK DRIVERS`
449			`*`
450			`* FOR SYS09BUG 1.2 ON THE BURCHED B5-X300`
451			`* WITH I/O MAPPED AT $XE000`
452			`* AND ROM MAPPED AT $XF000`
453			`* THE BURCHED B5-X300 HAS 256KBYTES OF SRAM`
454			`* THE FIRST 64K IS USED BY FLEX,`
455			`* THE SECOND 192K MAY BE USED AS A RAM DISK`
456			`*`
457			`*`
458			`IMASK EQU $10 IRQ MASK CC`
459			`FMASK EQU $40 FIRQ MASK CC`
460			`DATREG EQU $FFF0 DAT REGISTERS`
461			`*`
462			`CF_BASE EQU $E040`
463			`CF_DATA EQU CF_BASE+0`
464			`CF_ERROR EQU CF_BASE+1 ; read error`
465			`CF_FEATURE EQU CF_BASE+1 ; write feature`
466			`CF_SCNT EQU CF_BASE+2`
467			`CF_SNUM EQU CF_BASE+3`
468			`CF_CLO EQU CF_BASE+4`
469			`CF_CHI EQU CF_BASE+5`
470			`CF_HEAD EQU CF_BASE+6`
471			`CF_STATUS EQU CF_BASE+7 ; read status`
472			`CF_COMAND EQU CF_BASE+7 ; write command`
473			`*`
474			`* Command Equates`
475			`*`
476			`CMDREAD EQU $20 ; Read Single sector`
477			`CMDWRITE EQU $30 ; Write Single sector`
478			`CMDFEATURE EQU $EF`
479			`FEAT8BIT EQU $01 ; enable 8 bit transfers`
480			`HEADLBA EQU $E0`
481			`*`
482			`* Status bit equates`
483			`*`
484			`BSY EQU $80`
485			`DRDY EQU $40`
486			`DRQ EQU $08`
487			`ERR EQU $01`
488			`*`
489			`*`
490			`* INITIALIZE CF CARD FOR 8 BIT LBA MODE`
491			`*`
492			`INITDR BSR WAITRDY`
493			`LDA #HEADLBA`
494			`STA CF_HEAD`
495			`LDA #FEAT8BIT`
496			`STA CF_FEATURE`
497			`LDA #CMDFEATURE`
498			`STA CF_COMAND`
499			`BRA WAITRDY`
500			`*`

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