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[/] [System09/] [tags/] [V10/] [rtl/] [vhdl/] [System09.vhd] - Blame information for rev 66

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--===========================================================================----
--
--  S Y N T H E Z I A B L E    System09 - SOC.
--
--  www.OpenCores.Org - September 2003
--  This core adheres to the GNU public license  
--
-- File name      : System09.vhd
--
-- Purpose        : Top level file for 6809 compatible system on a chip
--                  Designed with Xilinx XC2S300e Spartan 2+ FPGA.
--                  Implemented With BurchED B5-X300 FPGA board,
--                  B3-SRAM module, B5-CF module and B3-FPGA-CPU-IO module
--
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_arith
--                  ieee.numeric_std
--
-- Uses           : boot_rom (sbug.vhd)       Monitor ROM
--                  cpu09    (cpu09.vhd)      CPU core
--                  dat_ram  (datram.vhd)     Dynamic Address Translation
--                  miniuart (minitUART2.vhd) ACIA / MiniUART
--                           (rxunit2.vhd)
--                           (tx_unit2.vhd)
--                           (clkunit2.vhd)
--                  timer    (timer.vhd)      Timer module
-- 
-- Author         : John E. Kent      
--                  dilbert57@opencores.org      
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
-- Version 0.6 - 5 September 2003
-- Runs SBUG
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
--===========================================================================--
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
 
entity System09 is
  port(
    SysClk      : in  Std_Logic;  -- System Clock input
         Reset_n     : in  Std_logic;  -- Master Reset input (active low)
    LED         : out std_logic;  -- Diagnostic LED Flasher
 
    -- Memory Interface signals
    ram_csn     : out Std_Logic;
    ram_wrln    : out Std_Logic;
    ram_wrun    : out Std_Logic;
    ram_addr    : out Std_Logic_Vector(16 downto 0);
    ram_data    : inout Std_Logic_Vector(15 downto 0);
 
         -- Stuff on the peripheral board
--  aux_clock   : in  Std_Logic;  -- FPGA-CPU-IO clock
 
         -- PS/2 Mouse interface
--       mouse_clock : in  Std_Logic;
--       mouse_data  : in  Std_Logic;
 
         -- Uart Interface
    rxbit       : in  Std_Logic;
         txbit       : out Std_Logic;
    rts_n       : out Std_Logic;
    cts_n       : in  Std_Logic;
 
         -- CRTC output signals
--         v_drive     : out Std_Logic;
--    h_drive     : out Std_Logic;
--    blue_lo     : out std_logic;
--    blue_hi     : out std_logic;
--    green_lo    : out std_logic;
--    green_hi    : out std_logic;
--    red_lo      : out std_logic;
--    red_hi      : out std_logic;
--         buzzer      : out std_logic;
 
-- Compact Flash
    cf_rst_n     : out std_logic;
         cf_cs0_n     : out std_logic;
         cf_cs1_n     : out std_logic;
    cf_rd_n      : out std_logic;
    cf_wr_n      : out std_logic;
         cf_cs16_n    : out std_logic;
    cf_a         : out std_logic_vector(2 downto 0);
    cf_d         : inout std_logic_vector(15 downto 0);
 
-- Parallel I/O port
--    porta        : inout std_logic_vector(7 downto 0);
--    portb        : inout std_logic_vector(7 downto 0);
--    timer_out    : out std_logic;
 
-- Test Pins
         test_alu    : out std_logic_vector(15 downto 0);
         test_cc     : out std_logic_vector(7 downto 0)
         );
end System09;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of System09 is
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  -- BOOT ROM
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
 
  -- UART Interface signals
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
  signal uart_cs       : Std_Logic;
  signal uart_irq      : Std_Logic;
 
  -- timer
--  signal timer_data_out : std_logic_vector(7 downto 0);
--  signal timer_cs    : std_logic;
--  signal timer_irq   : std_logic;
 
  -- Parallel I/O port
--  signal ioport_data_out : std_logic_vector(7 downto 0);
--  signal ioport_cs    : std_logic;
 
  -- compact flash port
  signal cf_data_out : std_logic_vector(7 downto 0);
  signal cf_cs       : std_logic;
  signal cf_rd       : std_logic;
  signal cf_wr       : std_logic;
 
  -- RAM
  signal ram_cs      : std_logic; -- memory chip select
  signal ram_wrl     : std_logic; -- memory write lower
  signal ram_wru     : std_logic; -- memory write upper
  signal ram_data_out    : std_logic_vector(7 downto 0);
 
  -- CPU Interface signals
  signal cpu_reset   : Std_Logic;
  signal cpu_clk     : Std_Logic;
  signal cpu_rw      : std_logic;
  signal cpu_vma     : std_logic;
  signal cpu_halt    : std_logic;
  signal cpu_hold    : std_logic;
  signal cpu_firq    : std_logic;
  signal cpu_irq     : std_logic;
  signal cpu_nmi     : std_logic;
  signal cpu_addr    : std_logic_vector(15 downto 0);
  signal cpu_data_in : std_logic_vector(7 downto 0);
  signal cpu_data_out: std_logic_vector(7 downto 0);
 
  -- Dynamic address translation
  signal dat_cs      : std_logic;
  signal dat_addr    : std_logic_vector(7 downto 0);
 
  -- Boot ROM Map switch
--  signal map_cs      : Std_Logic;
--  signal map_sw      : Std_Logic;
 
  -- synchronous RAM
--  signal xram_data_out : std_logic_vector(7 downto 0);
--  signal xram_cs       : std_logic;
 
  -- Flashing Led test signals
  signal countL      : std_logic_vector(23 downto 0);
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
  port (
         clk:        in std_logic;
    rst:      in        std_logic;
    rw:      out        std_logic;              -- Asynchronous memory interface
    vma:             out        std_logic;
    address:  out       std_logic_vector(15 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         halt:     in  std_logic;
         hold:     in  std_logic;
         irq:      in  std_logic;
         nmi:      in  std_logic;
         firq:     in  std_logic;
         test_alu: out std_logic_vector(15 downto 0);
         test_cc:  out std_logic_vector(7 downto 0)
  );
end component;
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
 
component miniUART
  port (
     SysClk   : in  Std_Logic;  -- System Clock
     rst      : in  Std_Logic;  -- Reset input
     cs       : in  Std_Logic;
     rw       : in  Std_Logic;
     RxD      : in  Std_Logic;
     TxD      : out Std_Logic;
     CTS_n    : in  Std_Logic;
     RTS_n    : out Std_Logic;
     Irq      : out Std_logic;
     Addr     : in  Std_Logic;
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- 
     DataOut  : out Std_Logic_Vector(7 downto 0)); -- 
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
--component timer
--  port (
--     clk       : in std_logic;
--     rst       : in std_logic;
--     cs        : in std_logic;
--     rw        : in std_logic;
--     addr      : in std_logic;
--     data_in   : in std_logic_vector(7 downto 0);
--        data_out  : out std_logic_vector(7 downto 0);
--        irq       : out std_logic;
--     timer_in  : in std_logic;
--        timer_out : out std_logic
--        );
--end component;
 
----------------------------------------
--
-- Dual 8 bit Parallel I/O module
--
----------------------------------------
--component ioport
--      port (  
--       clk       : in  std_logic;
--    rst       : in  std_logic;
--    cs        : in  std_logic;
--    rw        : in  std_logic;
--    addr      : in  std_logic_vector(1 downto 0);
--    data_in   : in  std_logic_vector(7 downto 0);
--       data_out  : out std_logic_vector(7 downto 0);
--       porta_io  : inout std_logic_vector(7 downto 0);
--       portb_io  : inout std_logic_vector(7 downto 0)
--       );
--end component;
 
----------------------------------------
--
-- SBUG Slice Monitor ROM
--
----------------------------------------
component boot_rom
  port (
    addr  : in  Std_Logic_Vector(10 downto 0);  -- 2K byte boot rom
         data  : out Std_Logic_Vector(7 downto 0));
end component;
 
----------------------------------------
--
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
--component sbug_rom
--    Port (
--       MEMclk   : in std_logic;
--       MEMaddr  : in std_logic_vector (10 downto 0);
--       MEMrdata : out std_logic_vector (7 downto 0)
--    );
--end component;
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
component dat_ram
  port (
    clk:      in  std_logic;
         rst:      in  std_logic;
         cs:       in  std_logic;
         rw:       in  std_logic;
         addr_lo:  in  std_logic_vector(3 downto 0);
         addr_hi:  in  std_logic_vector(3 downto 0);
    data_in:  in  std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0)
         );
end component;
 
----------------------------------------
--
-- Block RAM module
--
----------------------------------------
-- component block_ram
--    Port (
--       MEMclk   : in  std_logic;
--               MEMcs    : in  std_logic;
--               MEMrw    : in  std_logic;
--       MEMaddr  : in  std_logic_vector (10 downto 0);
--       MEMrdata : out std_logic_vector (7 downto 0);
--       MEMwdata : in  std_logic_vector (7 downto 0)
--    );
--end component;
 
 
-- component BUFG 
--  port (
--     i: in std_logic;
--        o: out std_logic
--  );
-- end component;
 
begin
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
my_cpu : cpu09  port map (
         clk         => SysClk,
    rst       => cpu_reset,
    rw       => cpu_rw,
    vma       => cpu_vma,
    address   => cpu_addr(15 downto 0),
    data_in   => cpu_data_in,
         data_out  => cpu_data_out,
         halt      => cpu_halt,
         hold      => cpu_hold,
         irq       => cpu_irq,
         nmi       => cpu_nmi,
         firq      => cpu_firq,
         test_alu  => test_alu,
         test_cc   => test_cc
  );
 
 
my_uart  : miniUART port map (
    SysClk    => SysClk,
         rst       => cpu_reset,
    cs        => uart_cs,
         rw        => cpu_rw,
         RxD       => rxbit,
         TxD       => txbit,
         CTS_n     => cts_n,
         RTS_n     => rts_n,
    Irq       => uart_irq,
    Addr      => cpu_addr(0),
         Datain    => cpu_data_out,
         DataOut   => uart_data_out
         );
 
--my_timer  : timer port map (
--    clk       => SysClk,
--       rst       => cpu_reset,
--    cs        => timer_cs,
--       rw        => cpu_rw,
--    addr      => cpu_addr(0),
--       data_in   => cpu_data_out,
--       data_out  => timer_data_out,
--    irq       => timer_irq,
--       timer_in  => CountL(5),
--       timer_out => timer_out
--    );
 
--my_ioport  : ioport port map (
--       clk       => SysClk,
--    rst       => cpu_reset,
--    cs        => ioport_cs,
--    rw        => cpu_rw,
--    addr      => cpu_addr(1 downto 0),
--    data_in   => cpu_data_out,
--       data_out  => ioport_data_out,
--       porta_io  => porta,
--       portb_io  => portb
--       );
 
my_rom : boot_rom port map (
         addr       => cpu_addr(10 downto 0),
    data       => rom_data_out
         );
 
--my_rom : sbug_rom port map (
--       MEMclk   => SysClk,
--       MEMaddr  => cpu_addr(10 downto 0),
--       MEMrdata => rom_data_out
--    );
 
my_dat : dat_ram port map (
    clk        => SysClk,
         rst        => cpu_reset,
         cs         => dat_cs,
         rw         => cpu_rw,
         addr_hi    => cpu_addr(15 downto 12),
         addr_lo    => cpu_addr(3 downto 0),
    data_in    => cpu_data_out,
         data_out   => dat_addr(7 downto 0)
         );
 
--my_ram : block_ram port map (
--       MEMclk   => SysClk,
--       MEMcs    => xram_cs,
--               MEMrw    => cpu_rw,
--       MEMaddr  => cpu_addr(10 downto 0),
--       MEMwdata => cpu_data_out,
--       MEMrdata => xram_data_out
--    );
 
--  clk_buffer : BUFG port map(
--    i => e_clk,
--         o => cpu_clk
--    );         
 
----------------------------------------------------------------------
--
-- Process to decode memory map
--
----------------------------------------------------------------------
 
mem_decode: process( SysClk, Reset_n,
                     cpu_addr, cpu_rw, cpu_vma,
                                              dat_cs, dat_addr,
--                                                 map_cs, map_sw,
                                              rom_data_out, ram_data_out,
--                                                 xram_data_out,
                                              cf_data_out,
--                                                 timer_data_out, ioport_data_out,
                                                   uart_data_out )
begin
    case cpu_addr(15 downto 11) is
           --
                -- SBUG Monitor ROM $F800 - $FFFF
                --
                when "11111" => -- $F800 - $FFFF
                   cpu_data_in <= rom_data_out;       -- read ROM
                        dat_cs    <= cpu_vma;              -- write DAT
                        ram_cs    <= '0';
                        uart_cs   <= '0';
                        cf_cs     <= '0';
--                      timer_cs  <= '0';
--                      ioport_cs <= '0';
--                      xram_cs   <= '0';
--                      map_cs    <= '0';
 
           --
                -- Shadow RAM Monitor switch
                --
--              when "11101" => -- $E800 - $EFFF
--              when "11111" => -- $F800 - $FFFF
--                 if map_sw = '1' then
--                   cpu_data_in <= rom_data_out;     -- read ROM
--                        dat_cs    <= '0';                -- disable write to DAT
--                        ram_cs    <= cpu_vma;            -- enable write to RAM
--                      else
--                        cpu_data_in <= ram_data_out;     -- read RAM
--                        dat_cs    <= cpu_vma;            -- enable write DAT
--                        ram_cs    <= cpu_vma and cpu_rw; -- disable write to RAM
--                      end if;
--                      uart_cs   <= '0';
--                      cf_cs     <= '0';
--                      timer_cs  <= '0';
--                      ioport_cs <= '0';
--                      xram_cs   <= cpu_vma;
--                      map_cs    <= '0';
 
        --
                  -- Synchronous Block RAM $F000 - $F7FF
                  --
--      when "11110" => -- $F000 - $F7FF
--            cpu_data_in <= xram_data_out;
--                      dat_cs    <= '0';
--                      ram_cs    <= '0';
--                      uart_cs   <= '0';
--                      cf_cs     <= '0';
--                      timer_cs  <= '0';
--                      ioport_cs <= '0';
--                      xram_cs   <= cpu_vma;
--                      map_cs    <= '0';
 
      --
                -- IO Devices $E000 - $E7FF
                --
                when "11100" => -- $E000 - $E7FF
                   dat_cs    <= '0';
                        ram_cs    <= '0';
--                      xram_cs   <= '0';
                   case cpu_addr(7 downto 4) is
                        --
                        -- UART / ACIA $E000
                        --
                        when "0000" => -- $E000
                     cpu_data_in <= uart_data_out;
                          uart_cs     <= cpu_vma;
                          cf_cs       <= '0';
--                        timer_cs    <= '0';
--                        ioport_cs   <= '0';
--                        map_cs      <= '0';
         --
                        -- Compact Flash $E010 - $E01F
                        --
                        when "0001" => -- $E010
           cpu_data_in <= cf_data_out;
                          uart_cs     <= '0';
           cf_cs       <= cpu_vma;
--                        timer_cs    <= '0';
--                        ioport_cs   <= '0';
--                        map_cs      <= '0';
         --
         -- Timer $E020 - $E02F
                        --
--                      when "0010" => -- $E020
--           cpu_data_in <= timer_data_out;
--                        uart_cs     <= '0';
--                        cf_cs       <= '0';
--           timer_cs    <= cpu_vma;
--                        ioport_cs   <= '0';
--                        map_cs      <= '0';
 
         --
                        -- ROM Map switch $E030
                        --
--                      when "0011" => -- $E030
--           cpu_data_in <= "00000000";
--                        uart_cs     <= '0';
--                        cf_cs       <= '0';
--           timer_cs    <= '0';
--                        ioport_cs   <= '0';
--                        map_cs      <= cpu_vma;
 
         --
         -- I/O port $E040 - $E04F
                        --
--                      when "0100" => -- $E040
--           cpu_data_in <= ioport_data_out;
--                        uart_cs     <= '0';
--                        cf_cs       <= '0';
--           timer_cs    <= '0';
--                        ioport_cs   <= cpu_vma;
--                        map_cs      <= '0';
 
                        when others => -- $E040 to $E7FF
           cpu_data_in <= "00000000";
                          uart_cs     <= '0';
                          cf_cs       <= '0';
--                        timer_cs    <= '0';
--                        ioport_cs   <= '0';
--                        map_cs      <= '0';
                   end case;
                --
                -- Everything else is RAM
                --
                when others =>
                  cpu_data_in <= ram_data_out;
                  ram_cs      <= cpu_vma;
                  dat_cs      <= '0';
                  uart_cs     <= '0';
                  cf_cs       <= '0';
--                timer_cs    <= '0';
--                ioport_cs   <= '0';
--                xram_cs     <= '0';
--                map_cs      <= '0';
         end case;
end process;
 
--
-- B3-SRAM Control
-- Processes to read and write memory based on bus signals
--
ram_process: process( SysClk, Reset_n,
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
                                               dat_addr,
                      ram_cs, ram_wrl, ram_wru, ram_data_out )
begin
    ram_csn <= not( ram_cs and Reset_n );
         ram_wrl  <= (not dat_addr(5)) and (not cpu_rw) and SysClk;
         ram_wrln <= not (ram_wrl);
    ram_wru  <= dat_addr(5) and (not cpu_rw) and SysClk;
         ram_wrun <= not (ram_wru);
         ram_addr(16 downto 12) <= dat_addr(4 downto 0);
         ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
 
    if ram_wrl = '1' then
                ram_data(7 downto 0) <= cpu_data_out;
         else
      ram_data(7 downto 0)  <= "ZZZZZZZZ";
         end if;
 
         if ram_wru = '1' then
                ram_data(15 downto 8) <= cpu_data_out;
         else
      ram_data(15 downto 8)  <= "ZZZZZZZZ";
    end if;
 
         if dat_addr(5) = '1' then
      ram_data_out <= ram_data(15 downto 8);
         else
      ram_data_out <= ram_data(7 downto 0);
    end if;
end process;
 
--
-- Compact Flash Control
--
compact_flash: process( SysClk, Reset_n,
                 cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
                                          cf_cs, cf_rd, cf_wr, cf_data_out )
begin
         cf_rst_n  <= Reset_n;
         cf_cs0_n  <= not( cf_cs ) or cpu_addr(3);
         cf_cs1_n  <= not( cf_cs and cpu_addr(3));
         cf_cs16_n <= '1';
         cf_wr     <= cf_cs and (not cpu_rw);
         cf_rd     <= cf_cs and cpu_rw;
         cf_wr_n   <= not cf_wr;
         cf_rd_n   <= not cf_rd;
         cf_a      <= cpu_addr(2 downto 0);
         if cf_wr = '1' then
           cf_d(7 downto 0) <= cpu_data_out;
         else
           cf_d(7 downto 0) <= "ZZZZZZZZ";
         end if;
         cf_data_out <= cf_d(7 downto 0);
         cf_d(15 downto 8) <= "ZZZZZZZZ";
end process;
 
--
-- ROM Map switch
-- The Map switch output is initially set
-- On a Write to the Map Switch port, clear the Map Switch
-- and map the RAM in place of the boot ROM.
--
--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )
--begin
--  if SysClk'event and SysClk = '0' then
--    if Reset_n = '0' then
--          map_sw <= '1';
--       else
--          if (map_cs = '1') and (cpu_rw = '0') then
--                 map_sw <= '0';
--               else
--                 map_sw <= map_sw;
--               end if;
--       end if;
--  end if;
--end process;
 
--
-- Interrupts and other bus control signals
--
interrupts : process( Reset_n, uart_irq
--                    ,timer_irq
                                                         )
begin
         cpu_reset <= not Reset_n; -- CPU reset is active high
    cpu_irq  <= uart_irq;
--       cpu_nmi  <= timer_irq;
         cpu_nmi  <= '0';
         cpu_firq <= '0';
         cpu_halt <= '0';
         cpu_hold <= '0';
end process;
 
  --
  -- flash led to indicate code is working
  --
increment: process (SysClk, CountL )
begin
    if(SysClk'event and SysClk = '0') then
      countL <= countL + 1;
    end if;
         LED <= countL(21);
end process;
 
end my_computer; --===================== End of architecture =======================--
 

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[/] [System09/] [tags/] [V10/] [rtl/] [vhdl/] [System09.vhd] - Blame information for rev 66

Line No.	Rev	Author	Line
1	2	dilbert57	`--===========================================================================----`
2			`--`
3			`-- S Y N T H E Z I A B L E System09 - SOC.`
4			`--`
5			`-- www.OpenCores.Org - September 2003`
6			`-- This core adheres to the GNU public license`
7			`--`
8			`-- File name : System09.vhd`
9			`--`
10			`-- Purpose : Top level file for 6809 compatible system on a chip`
11			`-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.`
12			`-- Implemented With BurchED B5-X300 FPGA board,`
13			`-- B3-SRAM module, B5-CF module and B3-FPGA-CPU-IO module`
14			`--`
15			`-- Dependencies : ieee.Std_Logic_1164`
16			`-- ieee.std_logic_unsigned`
17			`-- ieee.std_logic_arith`
18			`-- ieee.numeric_std`
19			`--`
20			`-- Uses : boot_rom (sbug.vhd) Monitor ROM`
21			`-- cpu09 (cpu09.vhd) CPU core`
22			`-- dat_ram (datram.vhd) Dynamic Address Translation`
23			`-- miniuart (minitUART2.vhd) ACIA / MiniUART`
24			`-- (rxunit2.vhd)`
25			`-- (tx_unit2.vhd)`
26			`-- (clkunit2.vhd)`
27			`-- timer (timer.vhd) Timer module`
28			`--`
29			`-- Author : John E. Kent`
30			`-- dilbert57@opencores.org`
31			`--`
32			`--===========================================================================----`
33			`--`
34			`-- Revision History:`
35			`--===========================================================================--`
36			`-- Version 0.1 - 20 March 2003`
37			`-- Version 0.2 - 30 March 2003`
38			`-- Version 0.3 - 29 April 2003`
39			`-- Version 0.4 - 29 June 2003`
40			`-- Version 0.5 - 19 July 2003`
41			`-- prints out "Hello World"`
42			`-- Version 0.6 - 5 September 2003`
43			`-- Runs SBUG`
44			`-- Version 1.0- 6 Sep 2003 - John Kent`
45			`-- Inverted SysClk`
46			`-- Initial release to Open Cores`
47			`--`
48			`--===========================================================================--`
49			`library ieee;`
50			`use ieee.std_logic_1164.all;`
51			`use IEEE.STD_LOGIC_ARITH.ALL;`
52			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
53			`use ieee.numeric_std.all;`
54
55			`entity System09 is`
56			`port(`
57			`SysClk : in Std_Logic; -- System Clock input`
58			`Reset_n : in Std_logic; -- Master Reset input (active low)`
59			`LED : out std_logic; -- Diagnostic LED Flasher`
60
61			`-- Memory Interface signals`
62			`ram_csn : out Std_Logic;`
63			`ram_wrln : out Std_Logic;`
64			`ram_wrun : out Std_Logic;`
65			`ram_addr : out Std_Logic_Vector(16 downto 0);`
66			`ram_data : inout Std_Logic_Vector(15 downto 0);`
67
68			`-- Stuff on the peripheral board`
69			`-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock`
70
71			`-- PS/2 Mouse interface`
72			`-- mouse_clock : in Std_Logic;`
73			`-- mouse_data : in Std_Logic;`
74
75			`-- Uart Interface`
76			`rxbit : in Std_Logic;`
77			`txbit : out Std_Logic;`
78			`rts_n : out Std_Logic;`
79			`cts_n : in Std_Logic;`
80
81			`-- CRTC output signals`
82			`-- v_drive : out Std_Logic;`
83			`-- h_drive : out Std_Logic;`
84			`-- blue_lo : out std_logic;`
85			`-- blue_hi : out std_logic;`
86			`-- green_lo : out std_logic;`
87			`-- green_hi : out std_logic;`
88			`-- red_lo : out std_logic;`
89			`-- red_hi : out std_logic;`
90			`-- buzzer : out std_logic;`
91
92			`-- Compact Flash`
93			`cf_rst_n : out std_logic;`
94			`cf_cs0_n : out std_logic;`
95			`cf_cs1_n : out std_logic;`
96			`cf_rd_n : out std_logic;`
97			`cf_wr_n : out std_logic;`
98			`cf_cs16_n : out std_logic;`
99			`cf_a : out std_logic_vector(2 downto 0);`
100			`cf_d : inout std_logic_vector(15 downto 0);`
101
102			`-- Parallel I/O port`
103			`-- porta : inout std_logic_vector(7 downto 0);`
104			`-- portb : inout std_logic_vector(7 downto 0);`
105			`-- timer_out : out std_logic;`
106
107			`-- Test Pins`
108			`test_alu : out std_logic_vector(15 downto 0);`
109			`test_cc : out std_logic_vector(7 downto 0)`
110			`);`
111			`end System09;`
112
113			`-------------------------------------------------------------------------------`
114			`-- Architecture for memio Controller Unit`
115			`-------------------------------------------------------------------------------`
116			`architecture my_computer of System09 is`
117			`-----------------------------------------------------------------------------`
118			`-- Signals`
119			`-----------------------------------------------------------------------------`
120			`-- BOOT ROM`
121			`signal rom_data_out : Std_Logic_Vector(7 downto 0);`
122
123			`-- UART Interface signals`
124			`signal uart_data_out : Std_Logic_Vector(7 downto 0);`
125			`signal uart_cs : Std_Logic;`
126			`signal uart_irq : Std_Logic;`
127
128			`-- timer`
129			`-- signal timer_data_out : std_logic_vector(7 downto 0);`
130			`-- signal timer_cs : std_logic;`
131			`-- signal timer_irq : std_logic;`
132
133			`-- Parallel I/O port`
134			`-- signal ioport_data_out : std_logic_vector(7 downto 0);`
135			`-- signal ioport_cs : std_logic;`
136
137			`-- compact flash port`
138			`signal cf_data_out : std_logic_vector(7 downto 0);`
139			`signal cf_cs : std_logic;`
140			`signal cf_rd : std_logic;`
141			`signal cf_wr : std_logic;`
142
143			`-- RAM`
144			`signal ram_cs : std_logic; -- memory chip select`
145			`signal ram_wrl : std_logic; -- memory write lower`
146			`signal ram_wru : std_logic; -- memory write upper`
147			`signal ram_data_out : std_logic_vector(7 downto 0);`
148
149			`-- CPU Interface signals`
150			`signal cpu_reset : Std_Logic;`
151			`signal cpu_clk : Std_Logic;`
152			`signal cpu_rw : std_logic;`
153			`signal cpu_vma : std_logic;`
154			`signal cpu_halt : std_logic;`
155			`signal cpu_hold : std_logic;`
156			`signal cpu_firq : std_logic;`
157			`signal cpu_irq : std_logic;`
158			`signal cpu_nmi : std_logic;`
159			`signal cpu_addr : std_logic_vector(15 downto 0);`
160			`signal cpu_data_in : std_logic_vector(7 downto 0);`
161			`signal cpu_data_out: std_logic_vector(7 downto 0);`
162
163			`-- Dynamic address translation`
164			`signal dat_cs : std_logic;`
165			`signal dat_addr : std_logic_vector(7 downto 0);`
166
167			`-- Boot ROM Map switch`
168			`-- signal map_cs : Std_Logic;`
169			`-- signal map_sw : Std_Logic;`
170
171			`-- synchronous RAM`
172			`-- signal xram_data_out : std_logic_vector(7 downto 0);`
173			`-- signal xram_cs : std_logic;`
174
175			`-- Flashing Led test signals`
176			`signal countL : std_logic_vector(23 downto 0);`
177
178			`-----------------------------------------------------------------`
179			`--`
180			`-- CPU09 CPU core`
181			`--`
182			`-----------------------------------------------------------------`
183
184			`component cpu09`
185			`port (`
186			`clk: in std_logic;`
187			`rst: in std_logic;`
188			`rw: out std_logic; -- Asynchronous memory interface`
189			`vma: out std_logic;`
190			`address: out std_logic_vector(15 downto 0);`
191			`data_in: in std_logic_vector(7 downto 0);`
192			`data_out: out std_logic_vector(7 downto 0);`
193			`halt: in std_logic;`
194			`hold: in std_logic;`
195			`irq: in std_logic;`
196			`nmi: in std_logic;`
197			`firq: in std_logic;`
198			`test_alu: out std_logic_vector(15 downto 0);`
199			`test_cc: out std_logic_vector(7 downto 0)`
200			`);`
201			`end component;`
202
203			`-----------------------------------------------------------------`
204			`--`
205			`-- Open Cores Mini UART`
206			`--`
207			`-----------------------------------------------------------------`
208
209			`component miniUART`
210			`port (`
211			`SysClk : in Std_Logic; -- System Clock`
212			`rst : in Std_Logic; -- Reset input`
213			`cs : in Std_Logic;`
214			`rw : in Std_Logic;`
215			`RxD : in Std_Logic;`
216			`TxD : out Std_Logic;`
217			`CTS_n : in Std_Logic;`
218			`RTS_n : out Std_Logic;`
219			`Irq : out Std_logic;`
220			`Addr : in Std_Logic;`
221			`DataIn : in Std_Logic_Vector(7 downto 0); --`
222			`DataOut : out Std_Logic_Vector(7 downto 0)); --`
223			`end component;`
224
225			`----------------------------------------`
226			`--`
227			`-- Timer module`
228			`--`
229			`----------------------------------------`
230
231			`--component timer`
232			`-- port (`
233			`-- clk : in std_logic;`
234			`-- rst : in std_logic;`
235			`-- cs : in std_logic;`
236			`-- rw : in std_logic;`
237			`-- addr : in std_logic;`
238			`-- data_in : in std_logic_vector(7 downto 0);`
239			`-- data_out : out std_logic_vector(7 downto 0);`
240			`-- irq : out std_logic;`
241			`-- timer_in : in std_logic;`
242			`-- timer_out : out std_logic`
243			`-- );`
244			`--end component;`
245
246			`----------------------------------------`
247			`--`
248			`-- Dual 8 bit Parallel I/O module`
249			`--`
250			`----------------------------------------`
251			`--component ioport`
252			`-- port (`
253			`-- clk : in std_logic;`
254			`-- rst : in std_logic;`
255			`-- cs : in std_logic;`
256			`-- rw : in std_logic;`
257			`-- addr : in std_logic_vector(1 downto 0);`
258			`-- data_in : in std_logic_vector(7 downto 0);`
259			`-- data_out : out std_logic_vector(7 downto 0);`
260			`-- porta_io : inout std_logic_vector(7 downto 0);`
261			`-- portb_io : inout std_logic_vector(7 downto 0)`
262			`-- );`
263			`--end component;`
264
265			`----------------------------------------`
266			`--`
267			`-- SBUG Slice Monitor ROM`
268			`--`
269			`----------------------------------------`
270			`component boot_rom`
271			`port (`
272			`addr : in Std_Logic_Vector(10 downto 0); -- 2K byte boot rom`
273			`data : out Std_Logic_Vector(7 downto 0));`
274			`end component;`
275
276			`----------------------------------------`
277			`--`
278			`-- SBUG Block RAM Monitor ROM`
279			`--`
280			`----------------------------------------`
281			`--component sbug_rom`
282			`-- Port (`
283			`-- MEMclk : in std_logic;`
284			`-- MEMaddr : in std_logic_vector (10 downto 0);`
285			`-- MEMrdata : out std_logic_vector (7 downto 0)`
286			`-- );`
287			`--end component;`
288
289			`----------------------------------------`
290			`--`
291			`-- Dynamic Address Translation Registers`
292			`--`
293			`----------------------------------------`
294			`component dat_ram`
295			`port (`
296			`clk: in std_logic;`
297			`rst: in std_logic;`
298			`cs: in std_logic;`
299			`rw: in std_logic;`
300			`addr_lo: in std_logic_vector(3 downto 0);`
301			`addr_hi: in std_logic_vector(3 downto 0);`
302			`data_in: in std_logic_vector(7 downto 0);`
303			`data_out: out std_logic_vector(7 downto 0)`
304			`);`
305			`end component;`
306
307			`----------------------------------------`
308			`--`
309			`-- Block RAM module`
310			`--`
311			`----------------------------------------`
312			`-- component block_ram`
313			`-- Port (`
314			`-- MEMclk : in std_logic;`
315			`-- MEMcs : in std_logic;`
316			`-- MEMrw : in std_logic;`
317			`-- MEMaddr : in std_logic_vector (10 downto 0);`
318			`-- MEMrdata : out std_logic_vector (7 downto 0);`
319			`-- MEMwdata : in std_logic_vector (7 downto 0)`
320			`-- );`
321			`--end component;`
322
323
324			`-- component BUFG`
325			`-- port (`
326			`-- i: in std_logic;`
327			`-- o: out std_logic`
328			`-- );`
329			`-- end component;`
330
331			`begin`
332			`-----------------------------------------------------------------------------`
333			`-- Instantiation of internal components`
334			`-----------------------------------------------------------------------------`
335
336			`my_cpu : cpu09 port map (`
337			`clk => SysClk,`
338			`rst => cpu_reset,`
339			`rw => cpu_rw,`
340			`vma => cpu_vma,`
341			`address => cpu_addr(15 downto 0),`
342			`data_in => cpu_data_in,`
343			`data_out => cpu_data_out,`
344			`halt => cpu_halt,`
345			`hold => cpu_hold,`
346			`irq => cpu_irq,`
347			`nmi => cpu_nmi,`
348			`firq => cpu_firq,`
349			`test_alu => test_alu,`
350			`test_cc => test_cc`
351			`);`
352
353
354			`my_uart : miniUART port map (`
355			`SysClk => SysClk,`
356			`rst => cpu_reset,`
357			`cs => uart_cs,`
358			`rw => cpu_rw,`
359			`RxD => rxbit,`
360			`TxD => txbit,`
361			`CTS_n => cts_n,`
362			`RTS_n => rts_n,`
363			`Irq => uart_irq,`
364			`Addr => cpu_addr(0),`
365			`Datain => cpu_data_out,`
366			`DataOut => uart_data_out`
367			`);`
368
369			`--my_timer : timer port map (`
370			`-- clk => SysClk,`
371			`-- rst => cpu_reset,`
372			`-- cs => timer_cs,`
373			`-- rw => cpu_rw,`
374			`-- addr => cpu_addr(0),`
375			`-- data_in => cpu_data_out,`
376			`-- data_out => timer_data_out,`
377			`-- irq => timer_irq,`
378			`-- timer_in => CountL(5),`
379			`-- timer_out => timer_out`
380			`-- );`
381
382			`--my_ioport : ioport port map (`
383			`-- clk => SysClk,`
384			`-- rst => cpu_reset,`
385			`-- cs => ioport_cs,`
386			`-- rw => cpu_rw,`
387			`-- addr => cpu_addr(1 downto 0),`
388			`-- data_in => cpu_data_out,`
389			`-- data_out => ioport_data_out,`
390			`-- porta_io => porta,`
391			`-- portb_io => portb`
392			`-- );`
393
394			`my_rom : boot_rom port map (`
395			`addr => cpu_addr(10 downto 0),`
396			`data => rom_data_out`
397			`);`
398
399			`--my_rom : sbug_rom port map (`
400			`-- MEMclk => SysClk,`
401			`-- MEMaddr => cpu_addr(10 downto 0),`
402			`-- MEMrdata => rom_data_out`
403			`-- );`
404
405			`my_dat : dat_ram port map (`
406			`clk => SysClk,`
407			`rst => cpu_reset,`
408			`cs => dat_cs,`
409			`rw => cpu_rw,`
410			`addr_hi => cpu_addr(15 downto 12),`
411			`addr_lo => cpu_addr(3 downto 0),`
412			`data_in => cpu_data_out,`
413			`data_out => dat_addr(7 downto 0)`
414			`);`
415
416			`--my_ram : block_ram port map (`
417			`-- MEMclk => SysClk,`
418			`-- MEMcs => xram_cs,`
419			`-- MEMrw => cpu_rw,`
420			`-- MEMaddr => cpu_addr(10 downto 0),`
421			`-- MEMwdata => cpu_data_out,`
422			`-- MEMrdata => xram_data_out`
423			`-- );`
424
425			`-- clk_buffer : BUFG port map(`
426			`-- i => e_clk,`
427			`-- o => cpu_clk`
428			`-- );`
429
430			`----------------------------------------------------------------------`
431			`--`
432			`-- Process to decode memory map`
433			`--`
434			`----------------------------------------------------------------------`
435
436			`mem_decode: process( SysClk, Reset_n,`
437			`cpu_addr, cpu_rw, cpu_vma,`
438			`dat_cs, dat_addr,`
439			`-- map_cs, map_sw,`
440			`rom_data_out, ram_data_out,`
441			`-- xram_data_out,`
442			`cf_data_out,`
443			`-- timer_data_out, ioport_data_out,`
444			`uart_data_out )`
445			`begin`
446			`case cpu_addr(15 downto 11) is`
447			`--`
448			`-- SBUG Monitor ROM $F800 - $FFFF`
449			`--`
450			`when "11111" => -- $F800 - $FFFF`
451			`cpu_data_in <= rom_data_out; -- read ROM`
452			`dat_cs <= cpu_vma; -- write DAT`
453			`ram_cs <= '0';`
454			`uart_cs <= '0';`
455			`cf_cs <= '0';`
456			`-- timer_cs <= '0';`
457			`-- ioport_cs <= '0';`
458			`-- xram_cs <= '0';`
459			`-- map_cs <= '0';`
460
461			`--`
462			`-- Shadow RAM Monitor switch`
463			`--`
464			`-- when "11101" => -- $E800 - $EFFF`
465			`-- when "11111" => -- $F800 - $FFFF`
466			`-- if map_sw = '1' then`
467			`-- cpu_data_in <= rom_data_out; -- read ROM`
468			`-- dat_cs <= '0'; -- disable write to DAT`
469			`-- ram_cs <= cpu_vma; -- enable write to RAM`
470			`-- else`
471			`-- cpu_data_in <= ram_data_out; -- read RAM`
472			`-- dat_cs <= cpu_vma; -- enable write DAT`
473			`-- ram_cs <= cpu_vma and cpu_rw; -- disable write to RAM`
474			`-- end if;`
475			`-- uart_cs <= '0';`
476			`-- cf_cs <= '0';`
477			`-- timer_cs <= '0';`
478			`-- ioport_cs <= '0';`
479			`-- xram_cs <= cpu_vma;`
480			`-- map_cs <= '0';`
481
482			`--`
483			`-- Synchronous Block RAM $F000 - $F7FF`
484			`--`
485			`-- when "11110" => -- $F000 - $F7FF`
486			`-- cpu_data_in <= xram_data_out;`
487			`-- dat_cs <= '0';`
488			`-- ram_cs <= '0';`
489			`-- uart_cs <= '0';`
490			`-- cf_cs <= '0';`
491			`-- timer_cs <= '0';`
492			`-- ioport_cs <= '0';`
493			`-- xram_cs <= cpu_vma;`
494			`-- map_cs <= '0';`
495
496			`--`
497			`-- IO Devices $E000 - $E7FF`
498			`--`
499			`when "11100" => -- $E000 - $E7FF`
500			`dat_cs <= '0';`
501			`ram_cs <= '0';`
502			`-- xram_cs <= '0';`
503			`case cpu_addr(7 downto 4) is`
504			`--`
505			`-- UART / ACIA $E000`
506			`--`
507			`when "0000" => -- $E000`
508			`cpu_data_in <= uart_data_out;`
509			`uart_cs <= cpu_vma;`
510			`cf_cs <= '0';`
511			`-- timer_cs <= '0';`
512			`-- ioport_cs <= '0';`
513			`-- map_cs <= '0';`
514			`--`
515			`-- Compact Flash $E010 - $E01F`
516			`--`
517			`when "0001" => -- $E010`
518			`cpu_data_in <= cf_data_out;`
519			`uart_cs <= '0';`
520			`cf_cs <= cpu_vma;`
521			`-- timer_cs <= '0';`
522			`-- ioport_cs <= '0';`
523			`-- map_cs <= '0';`
524			`--`
525			`-- Timer $E020 - $E02F`
526			`--`
527			`-- when "0010" => -- $E020`
528			`-- cpu_data_in <= timer_data_out;`
529			`-- uart_cs <= '0';`
530			`-- cf_cs <= '0';`
531			`-- timer_cs <= cpu_vma;`
532			`-- ioport_cs <= '0';`
533			`-- map_cs <= '0';`
534
535			`--`
536			`-- ROM Map switch $E030`
537			`--`
538			`-- when "0011" => -- $E030`
539			`-- cpu_data_in <= "00000000";`
540			`-- uart_cs <= '0';`
541			`-- cf_cs <= '0';`
542			`-- timer_cs <= '0';`
543			`-- ioport_cs <= '0';`
544			`-- map_cs <= cpu_vma;`
545
546			`--`
547			`-- I/O port $E040 - $E04F`
548			`--`
549			`-- when "0100" => -- $E040`
550			`-- cpu_data_in <= ioport_data_out;`
551			`-- uart_cs <= '0';`
552			`-- cf_cs <= '0';`
553			`-- timer_cs <= '0';`
554			`-- ioport_cs <= cpu_vma;`
555			`-- map_cs <= '0';`
556
557			`when others => -- $E040 to $E7FF`
558			`cpu_data_in <= "00000000";`
559			`uart_cs <= '0';`
560			`cf_cs <= '0';`
561			`-- timer_cs <= '0';`
562			`-- ioport_cs <= '0';`
563			`-- map_cs <= '0';`
564			`end case;`
565			`--`
566			`-- Everything else is RAM`
567			`--`
568			`when others =>`
569			`cpu_data_in <= ram_data_out;`
570			`ram_cs <= cpu_vma;`
571			`dat_cs <= '0';`
572			`uart_cs <= '0';`
573			`cf_cs <= '0';`
574			`-- timer_cs <= '0';`
575			`-- ioport_cs <= '0';`
576			`-- xram_cs <= '0';`
577			`-- map_cs <= '0';`
578			`end case;`
579			`end process;`
580
581			`--`
582			`-- B3-SRAM Control`
583			`-- Processes to read and write memory based on bus signals`
584			`--`
585			`ram_process: process( SysClk, Reset_n,`
586			`cpu_addr, cpu_rw, cpu_vma, cpu_data_out,`
587			`dat_addr,`
588			`ram_cs, ram_wrl, ram_wru, ram_data_out )`
589			`begin`
590			`ram_csn <= not( ram_cs and Reset_n );`
591			`ram_wrl <= (not dat_addr(5)) and (not cpu_rw) and SysClk;`
592			`ram_wrln <= not (ram_wrl);`
593			`ram_wru <= dat_addr(5) and (not cpu_rw) and SysClk;`
594			`ram_wrun <= not (ram_wru);`
595			`ram_addr(16 downto 12) <= dat_addr(4 downto 0);`
596			`ram_addr(11 downto 0) <= cpu_addr(11 downto 0);`
597
598			`if ram_wrl = '1' then`
599			`ram_data(7 downto 0) <= cpu_data_out;`
600			`else`
601			`ram_data(7 downto 0) <= "ZZZZZZZZ";`
602			`end if;`
603
604			`if ram_wru = '1' then`
605			`ram_data(15 downto 8) <= cpu_data_out;`
606			`else`
607			`ram_data(15 downto 8) <= "ZZZZZZZZ";`
608			`end if;`
609
610			`if dat_addr(5) = '1' then`
611			`ram_data_out <= ram_data(15 downto 8);`
612			`else`
613			`ram_data_out <= ram_data(7 downto 0);`
614			`end if;`
615			`end process;`
616
617			`--`
618			`-- Compact Flash Control`
619			`--`
620			`compact_flash: process( SysClk, Reset_n,`
621			`cpu_addr, cpu_rw, cpu_vma, cpu_data_out,`
622			`cf_cs, cf_rd, cf_wr, cf_data_out )`
623			`begin`
624			`cf_rst_n <= Reset_n;`
625			`cf_cs0_n <= not( cf_cs ) or cpu_addr(3);`
626			`cf_cs1_n <= not( cf_cs and cpu_addr(3));`
627			`cf_cs16_n <= '1';`
628			`cf_wr <= cf_cs and (not cpu_rw);`
629			`cf_rd <= cf_cs and cpu_rw;`
630			`cf_wr_n <= not cf_wr;`
631			`cf_rd_n <= not cf_rd;`
632			`cf_a <= cpu_addr(2 downto 0);`
633			`if cf_wr = '1' then`
634			`cf_d(7 downto 0) <= cpu_data_out;`
635			`else`
636			`cf_d(7 downto 0) <= "ZZZZZZZZ";`
637			`end if;`
638			`cf_data_out <= cf_d(7 downto 0);`
639			`cf_d(15 downto 8) <= "ZZZZZZZZ";`
640			`end process;`
641
642			`--`
643			`-- ROM Map switch`
644			`-- The Map switch output is initially set`
645			`-- On a Write to the Map Switch port, clear the Map Switch`
646			`-- and map the RAM in place of the boot ROM.`
647			`--`
648			`--map_proc : process( SysClk, Reset_n, map_cs, cpu_rw )`
649			`--begin`
650			`-- if SysClk'event and SysClk = '0' then`
651			`-- if Reset_n = '0' then`
652			`-- map_sw <= '1';`
653			`-- else`
654			`-- if (map_cs = '1') and (cpu_rw = '0') then`
655			`-- map_sw <= '0';`
656			`-- else`
657			`-- map_sw <= map_sw;`
658			`-- end if;`
659			`-- end if;`
660			`-- end if;`
661			`--end process;`
662
663			`--`
664			`-- Interrupts and other bus control signals`
665			`--`
666			`interrupts : process( Reset_n, uart_irq`
667			`-- ,timer_irq`
668			`)`
669			`begin`
670			`cpu_reset <= not Reset_n; -- CPU reset is active high`
671			`cpu_irq <= uart_irq;`
672			`-- cpu_nmi <= timer_irq;`
673			`cpu_nmi <= '0';`
674			`cpu_firq <= '0';`
675			`cpu_halt <= '0';`
676			`cpu_hold <= '0';`
677			`end process;`
678
679			`--`
680			`-- flash led to indicate code is working`
681			`--`
682			`increment: process (SysClk, CountL )`
683			`begin`
684			`if(SysClk'event and SysClk = '0') then`
685			`countL <= countL + 1;`
686			`end if;`
687			`LED <= countL(21);`
688			`end process;`
689
690			`end my_computer; --===================== End of architecture =======================--`
691