1 |
2 |
dilbert57 |
--===========================================================================--
|
2 |
|
|
--
|
3 |
|
|
-- S Y N T H E Z I A B L E miniUART C O R E
|
4 |
|
|
--
|
5 |
|
|
-- www.OpenCores.Org - January 2000
|
6 |
|
|
-- This core adheres to the GNU public license
|
7 |
|
|
--
|
8 |
|
|
-- Design units : miniUART core for the System68
|
9 |
|
|
--
|
10 |
|
|
-- File name : rxunit2.vhd
|
11 |
|
|
--
|
12 |
|
|
-- Purpose : Implements an miniUART device for communication purposes
|
13 |
|
|
-- between the cpu68 cpu and the Host computer through
|
14 |
|
|
-- an RS-232 communication protocol.
|
15 |
|
|
--
|
16 |
|
|
-- Dependencies : ieee.std_logic_1164.all;
|
17 |
|
|
-- ieee.numeric_std.all;
|
18 |
|
|
--
|
19 |
|
|
--===========================================================================--
|
20 |
|
|
-------------------------------------------------------------------------------
|
21 |
|
|
-- Revision list
|
22 |
|
|
-- Version Author Date Changes
|
23 |
|
|
--
|
24 |
|
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
25 |
|
|
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
|
26 |
|
|
-- olupas@opencores.org
|
27 |
|
|
--
|
28 |
|
|
-- 3.0 John Kent 5 January 2003 Added 6850 word format control
|
29 |
|
|
-- 3.1 John Kent 12 January 2003 Significantly revamped receive code.
|
30 |
|
|
-- 3.3 John Kent 6 September 2003 Changed Clock Edge.
|
31 |
|
|
-- dilbert57@opencores.org
|
32 |
|
|
-------------------------------------------------------------------------------
|
33 |
|
|
-- Description : Implements the receive unit of the miniUART core. Samples
|
34 |
|
|
-- 16 times the RxD line and retain the value in the middle of
|
35 |
|
|
-- the time interval.
|
36 |
|
|
library ieee;
|
37 |
|
|
use ieee.std_logic_1164.all;
|
38 |
|
|
use ieee.std_logic_unsigned.all;
|
39 |
|
|
|
40 |
|
|
-------------------------------------------------------------------------------
|
41 |
|
|
-- Receive unit
|
42 |
|
|
-------------------------------------------------------------------------------
|
43 |
|
|
entity RxUnit is
|
44 |
|
|
port (
|
45 |
|
|
Clk : in Std_Logic; -- system clock signal
|
46 |
|
|
Reset : in Std_Logic; -- Reset input
|
47 |
|
|
Enable : in Std_Logic; -- Enable input
|
48 |
|
|
RxD : in Std_Logic; -- RS-232 data input
|
49 |
|
|
ReadD : in Std_Logic; -- Read data signal
|
50 |
|
|
Format : in Std_Logic_Vector(2 downto 0);
|
51 |
|
|
FRErr : out Std_Logic; -- Status signal
|
52 |
|
|
ORErr : out Std_Logic; -- Status signal
|
53 |
|
|
PAErr : out Std_logic; -- Status Signal
|
54 |
|
|
DARdy : out Std_Logic; -- Status signal
|
55 |
|
|
DAOut : out Std_Logic_Vector(7 downto 0)
|
56 |
|
|
);
|
57 |
|
|
end; --================== End of entity ==============================--
|
58 |
|
|
-------------------------------------------------------------------------------
|
59 |
|
|
-- Architecture for receive Unit
|
60 |
|
|
-------------------------------------------------------------------------------
|
61 |
|
|
architecture Behaviour of RxUnit is
|
62 |
|
|
-----------------------------------------------------------------------------
|
63 |
|
|
-- Signals
|
64 |
|
|
-----------------------------------------------------------------------------
|
65 |
|
|
signal RxStart : Std_Logic; -- Start Receive Request
|
66 |
|
|
signal RxFinish : Std_Logic; -- Receive finished
|
67 |
|
|
signal RxValid : Std_Logic; -- Receive data valid
|
68 |
|
|
signal RxFalse : Std_Logic; -- False start flag
|
69 |
|
|
signal tmpRxD : Std_Logic; -- RxD buffer
|
70 |
|
|
signal tmpRxC : Std_Logic; -- Rx clock
|
71 |
|
|
signal tmpDRdy : Std_Logic; -- Data Ready flag
|
72 |
|
|
signal tmpRxVal : Std_Logic; -- Rx Data Valid
|
73 |
|
|
signal tmpRxFin : Std_Logic; -- Rx Finish
|
74 |
|
|
signal outErr : Std_Logic; -- Over run error bit
|
75 |
|
|
signal frameErr : Std_Logic; -- Framing error bit
|
76 |
|
|
signal ParityErr : Std_Logic; -- Parity Error Bit
|
77 |
|
|
signal RxParity : Std_Logic; -- Calculated RX parity bit
|
78 |
|
|
signal RxState : Std_Logic_Vector(3 downto 0); -- receive bit state
|
79 |
|
|
signal SampleCnt : Std_Logic_Vector(3 downto 0); -- samples on one bit counter
|
80 |
|
|
signal ShtReg : Std_Logic_Vector(7 downto 0); -- Shift Register
|
81 |
|
|
signal DataOut : Std_Logic_Vector(7 downto 0); -- Data Output register
|
82 |
|
|
|
83 |
|
|
constant CntOne : Std_Logic_Vector(3 downto 0):= "0001";
|
84 |
|
|
constant CntZero : Std_Logic_Vector(3 downto 0):= "0000";
|
85 |
|
|
|
86 |
|
|
begin
|
87 |
|
|
---------------------------------------------------------------------
|
88 |
|
|
-- Receiver Read process
|
89 |
|
|
---------------------------------------------------------------------
|
90 |
|
|
RcvRead : process(Clk, Reset, ReadD, RxValid, tmpRxVal, tmpDRdy )
|
91 |
|
|
begin
|
92 |
|
|
if Clk'event and Clk='0' then
|
93 |
|
|
if Reset = '1' then
|
94 |
|
|
tmpDRdy <= '0';
|
95 |
|
|
tmpRxVal <= '0';
|
96 |
|
|
else
|
97 |
|
|
if ReadD = '1' then
|
98 |
|
|
tmpDRdy <= '0'; -- Data was read
|
99 |
|
|
tmpRxVal <= tmpRxVal;
|
100 |
|
|
else
|
101 |
|
|
if RxValid = '1' and tmpRxVal = '0' then
|
102 |
|
|
tmpDRdy <= '1'; -- Data was received
|
103 |
|
|
tmpRxVal <= '1';
|
104 |
|
|
else
|
105 |
|
|
tmpDRdy <= tmpDRdy;
|
106 |
|
|
if RxValid = '0' and tmpRxVal = '1' then
|
107 |
|
|
tmpRxVal <= '0';
|
108 |
|
|
else
|
109 |
|
|
tmpRxVal <= tmpRxVal;
|
110 |
|
|
end if;
|
111 |
|
|
end if; -- RxValid
|
112 |
|
|
end if; -- ReadD
|
113 |
|
|
end if; -- reset
|
114 |
|
|
end if; -- clk
|
115 |
|
|
end process;
|
116 |
|
|
|
117 |
|
|
---------------------------------------------------------------------
|
118 |
|
|
-- Receiver Synchronisation process
|
119 |
|
|
---------------------------------------------------------------------
|
120 |
|
|
RcvSync : process(Clk, Reset, Enable, RxStart, RxFalse, RxFinish, RxD, SampleCnt )
|
121 |
|
|
variable CntIni : Std_Logic_Vector(3 downto 0);
|
122 |
|
|
variable CntAdd : Std_Logic_Vector(3 downto 0);
|
123 |
|
|
begin
|
124 |
|
|
if Clk'event and Clk='0' then
|
125 |
|
|
if Reset = '1' then
|
126 |
|
|
RxStart <= '0';
|
127 |
|
|
SampleCnt <= "0000";
|
128 |
|
|
CntIni := SampleCnt;
|
129 |
|
|
CntAdd := CntZero;
|
130 |
|
|
else
|
131 |
|
|
if Enable = '1' then
|
132 |
|
|
if RxFinish = '1' and RxStart = '0' then -- Are we looking for a start bit ?
|
133 |
|
|
if RxD = '0' then -- yes, look for Start Edge
|
134 |
|
|
RxStart <= '1'; -- we have a start edge
|
135 |
|
|
CntIni := CntZero;
|
136 |
|
|
CntAdd := CntZero;
|
137 |
|
|
else
|
138 |
|
|
RxStart <= '0'; -- no start, spin sample count
|
139 |
|
|
CntIni := SampleCnt;
|
140 |
|
|
CntAdd := CntOne;
|
141 |
|
|
end if;
|
142 |
|
|
else
|
143 |
|
|
if RxFinish = '0' and RxStart = '1' then -- have we received a start bit ?
|
144 |
|
|
RxStart <= '0'; -- yes, reset start request
|
145 |
|
|
else
|
146 |
|
|
if RxFalse = '1' and RxStart = '1' then -- false start ?
|
147 |
|
|
RxStart <= '0'; -- yep, reset start request
|
148 |
|
|
else
|
149 |
|
|
RxStart <= RxStart;
|
150 |
|
|
end if;
|
151 |
|
|
end if;
|
152 |
|
|
CntIni := SampleCnt;
|
153 |
|
|
CntAdd := CntOne;
|
154 |
|
|
end if; -- RxStart
|
155 |
|
|
else
|
156 |
|
|
CntIni := SampleCnt;
|
157 |
|
|
CntAdd := CntZero;
|
158 |
|
|
RxStart <= RxStart;
|
159 |
|
|
end if; -- enable
|
160 |
|
|
end if; -- reset
|
161 |
|
|
SampleCnt <= CntIni + CntAdd;
|
162 |
|
|
end if; -- clk
|
163 |
|
|
end process;
|
164 |
|
|
|
165 |
|
|
|
166 |
|
|
---------------------------------------------------------------------
|
167 |
|
|
-- Receiver Clock process
|
168 |
|
|
---------------------------------------------------------------------
|
169 |
|
|
RcvClock : process(Clk, Reset, SampleCnt, RxD, tmpRxD )
|
170 |
|
|
begin
|
171 |
|
|
if Clk'event and Clk='0' then
|
172 |
|
|
if Reset = '1' then
|
173 |
|
|
tmpRxC <= '0';
|
174 |
|
|
tmpRxD <= '1';
|
175 |
|
|
else
|
176 |
|
|
if SampleCnt = "1000" then
|
177 |
|
|
tmpRxD <= RxD;
|
178 |
|
|
else
|
179 |
|
|
tmpRxD <= tmpRxD;
|
180 |
|
|
end if;
|
181 |
|
|
|
182 |
|
|
if SampleCnt = "1111" then
|
183 |
|
|
tmpRxC <= '1';
|
184 |
|
|
else
|
185 |
|
|
tmpRxC <= '0';
|
186 |
|
|
end if;
|
187 |
|
|
end if; -- reset
|
188 |
|
|
end if; -- clk
|
189 |
|
|
end process;
|
190 |
|
|
|
191 |
|
|
---------------------------------------------------------------------
|
192 |
|
|
-- Receiver process
|
193 |
|
|
---------------------------------------------------------------------
|
194 |
|
|
RcvProc : process(Clk, Reset, RxState, tmpRxC, Enable, tmpRxD, RxStart,
|
195 |
|
|
frameErr, outErr, DataOut, tmpDRdy,
|
196 |
|
|
ShtReg, RxParity, parityErr, Format,
|
197 |
|
|
RxValid, RxFalse, RxFinish
|
198 |
|
|
)
|
199 |
|
|
begin
|
200 |
|
|
if Clk'event and Clk='0' then
|
201 |
|
|
if Reset = '1' then
|
202 |
|
|
frameErr <= '0';
|
203 |
|
|
outErr <= '0';
|
204 |
|
|
parityErr <= '0';
|
205 |
|
|
|
206 |
|
|
ShtReg <= "00000000"; -- Shift register
|
207 |
|
|
RxParity <= '0'; -- Parity bit
|
208 |
|
|
RxFinish <= '1'; -- Data RX finish flag
|
209 |
|
|
RxValid <= '0'; -- Data RX data valid flag
|
210 |
|
|
RxFalse <= '0';
|
211 |
|
|
RxState <= "1111";
|
212 |
|
|
DataOut <= "00000000";
|
213 |
|
|
else
|
214 |
|
|
if tmpRxC = '1' and Enable = '1' then
|
215 |
|
|
case RxState is
|
216 |
|
|
when "0000" | "0001" | "0010" | "0011" |
|
217 |
|
|
"0100" | "0101" | "0110" => -- data bits 0 to 6
|
218 |
|
|
ShtReg <= tmpRxD & ShtReg(7 downto 1);
|
219 |
|
|
RxParity <= RxParity xor tmpRxD;
|
220 |
|
|
parityErr <= parityErr;
|
221 |
|
|
frameErr <= frameErr;
|
222 |
|
|
outErr <= outErr;
|
223 |
|
|
RxValid <= '0';
|
224 |
|
|
DataOut <= DataOut;
|
225 |
|
|
RxFalse <= '0';
|
226 |
|
|
RxFinish <= '0';
|
227 |
|
|
if RxState = "0110" then
|
228 |
|
|
if Format(2) = '0' then
|
229 |
|
|
RxState <= "1000"; -- 7 data + parity
|
230 |
|
|
else
|
231 |
|
|
RxState <= "0111"; -- 8 data bits
|
232 |
|
|
end if; -- Format(2)
|
233 |
|
|
else
|
234 |
|
|
RxState <= RxState + CntOne;
|
235 |
|
|
end if; -- RxState
|
236 |
|
|
when "0111" => -- data bit 7
|
237 |
|
|
ShtReg <= tmpRxD & ShtReg(7 downto 1);
|
238 |
|
|
RxParity <= RxParity xor tmpRxD;
|
239 |
|
|
parityErr <= parityErr;
|
240 |
|
|
frameErr <= frameErr;
|
241 |
|
|
outErr <= outErr;
|
242 |
|
|
RxValid <= '0';
|
243 |
|
|
DataOut <= DataOut;
|
244 |
|
|
RxFalse <= '0';
|
245 |
|
|
RxFinish <= '0';
|
246 |
|
|
if Format(1) = '1' then -- parity bit ?
|
247 |
|
|
RxState <= "1000"; -- yes, go to parity
|
248 |
|
|
else
|
249 |
|
|
RxState <= "1001"; -- no, must be 2 stop bit bits
|
250 |
|
|
end if;
|
251 |
|
|
when "1000" => -- parity bit
|
252 |
|
|
if Format(2) = '0' then
|
253 |
|
|
ShtReg <= tmpRxD & ShtReg(7 downto 1); -- 7 data + parity
|
254 |
|
|
else
|
255 |
|
|
ShtReg <= ShtReg; -- 8 data + parity
|
256 |
|
|
end if;
|
257 |
|
|
RxParity <= RxParity;
|
258 |
|
|
if Format(0) = '0' then -- parity polarity ?
|
259 |
|
|
if RxParity = tmpRxD then -- check even parity
|
260 |
|
|
parityErr <= '1';
|
261 |
|
|
else
|
262 |
|
|
parityErr <= '0';
|
263 |
|
|
end if;
|
264 |
|
|
else
|
265 |
|
|
if RxParity = tmpRxD then -- check for odd parity
|
266 |
|
|
parityErr <= '0';
|
267 |
|
|
else
|
268 |
|
|
parityErr <= '1';
|
269 |
|
|
end if;
|
270 |
|
|
end if;
|
271 |
|
|
frameErr <= frameErr;
|
272 |
|
|
outErr <= outErr;
|
273 |
|
|
RxValid <= '0';
|
274 |
|
|
DataOut <= DataOut;
|
275 |
|
|
RxFalse <= '0';
|
276 |
|
|
RxFinish <= '0';
|
277 |
|
|
RxState <= "1001";
|
278 |
|
|
when "1001" => -- stop bit (Only one required for RX)
|
279 |
|
|
ShtReg <= ShtReg;
|
280 |
|
|
RxParity <= RxParity;
|
281 |
|
|
parityErr <= parityErr;
|
282 |
|
|
if tmpRxD = '1' then -- stop bit expected
|
283 |
|
|
frameErr <= '0'; -- yes, no framing error
|
284 |
|
|
else
|
285 |
|
|
frameErr <= '1'; -- no, framing error
|
286 |
|
|
end if;
|
287 |
|
|
if tmpDRdy = '1' then -- Has previous data been read ?
|
288 |
|
|
outErr <= '1'; -- no, overrun error
|
289 |
|
|
else
|
290 |
|
|
outErr <= '0'; -- yes, no over run error
|
291 |
|
|
end if;
|
292 |
|
|
RxValid <= '1';
|
293 |
|
|
DataOut <= ShtReg;
|
294 |
|
|
RxFalse <= '0';
|
295 |
|
|
RxFinish <= '1';
|
296 |
|
|
RxState <= "1111";
|
297 |
|
|
when others => -- this is the idle state
|
298 |
|
|
ShtReg <= ShtReg;
|
299 |
|
|
RxParity <= RxParity;
|
300 |
|
|
parityErr <= parityErr;
|
301 |
|
|
frameErr <= frameErr;
|
302 |
|
|
outErr <= outErr;
|
303 |
|
|
RxValid <= '0';
|
304 |
|
|
DataOut <= DataOut;
|
305 |
|
|
if RxStart = '1' and tmpRxD = '0' then -- look for start request
|
306 |
|
|
RxFalse <= '0';
|
307 |
|
|
RxFinish <= '0';
|
308 |
|
|
RxState <= "0000"; -- yes, read data
|
309 |
|
|
else
|
310 |
|
|
if RxStart = '1' and tmpRxD = '1' then -- start request, but no start bit
|
311 |
|
|
RxFalse <= '1';
|
312 |
|
|
else
|
313 |
|
|
RxFalse <= '0';
|
314 |
|
|
end if;
|
315 |
|
|
RxFinish <= '1';
|
316 |
|
|
RxState <= "1111"; -- otherwise idle
|
317 |
|
|
end if;
|
318 |
|
|
end case; -- RxState
|
319 |
|
|
else
|
320 |
|
|
ShtReg <= ShtReg;
|
321 |
|
|
RxParity <= RxParity;
|
322 |
|
|
parityErr <= parityErr;
|
323 |
|
|
frameErr <= frameErr;
|
324 |
|
|
outErr <= outErr;
|
325 |
|
|
RxValid <= RxValid;
|
326 |
|
|
DataOut <= DataOut;
|
327 |
|
|
RxFalse <= RxFalse;
|
328 |
|
|
RxFinish <= RxFinish;
|
329 |
|
|
RxState <= RxState;
|
330 |
|
|
end if; -- tmpRxC
|
331 |
|
|
end if; -- reset
|
332 |
|
|
end if; -- clk
|
333 |
|
|
end process;
|
334 |
|
|
|
335 |
|
|
DARdy <= tmpDRdy;
|
336 |
|
|
DAOut <= DataOut;
|
337 |
|
|
FRErr <= frameErr;
|
338 |
|
|
ORErr <= outErr;
|
339 |
|
|
PAErr <= parityErr;
|
340 |
|
|
|
341 |
|
|
end Behaviour; --==================== End of architecture ====================--
|