OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [tags/] [V10/] [rtl/] [vhdl/] [testbench4.vhd] - Blame information for rev 201

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dilbert57 
--===========================================================================--
2 
--
3 
-- MC6809 Microprocessor Test Bench 4
4 
-- Test Software - SBUG ROM
5 
--
6 
--
7 
-- John Kent 12st April 2003
8 
--
9 
--
10 
-------------------------------------------------------------------------------
11 
library ieee;
12 
   use ieee.std_logic_1164.all;
13 
   use IEEE.STD_LOGIC_ARITH.ALL;
14 
   use ieee.numeric_std.all;
15 
 
16 
entity my_testbench is
17 
end my_testbench;
18 
 
19 
-------------------------------------------------------------------------------
20 
-- Architecture for memio Controller Unit
21 
-------------------------------------------------------------------------------
22 
architecture behavior of my_testbench is
23 
  -----------------------------------------------------------------------------
24 
  -- Signals
25 
  -----------------------------------------------------------------------------
26 
  signal cpu_irq    : std_Logic;
27 
  signal cpu_firq   : std_logic;
28 
  signal cpu_nmi    : std_logic;
29 
 
30 
  -- CPU Interface signals
31 
  signal SysClk      : Std_Logic;
32 
  signal cpu_reset   : Std_Logic;
33 
  signal cpu_rw      : Std_Logic;
34 
  signal cpu_vma     : Std_Logic;
35 
  signal cpu_addr    : Std_Logic_Vector(15 downto 0);
36 
  signal cpu_data_in : Std_Logic_Vector(7 downto 0);
37 
  signal cpu_data_out: Std_Logic_Vector(7 downto 0);
38 
  signal cpu_halt    : Std_logic;
39 
  signal cpu_hold    : Std_logic;
40 
  signal cpu_alu     : Std_Logic_Vector(15 downto 0);
41 
  signal cpu_cc      : Std_Logic_Vector(7 downto 0);
42 
  signal rom_data_out: Std_Logic_Vector(7 downto 0);
43 
  signal ram_data_out: Std_Logic_Vector(7 downto 0);
44 
  signal ram_cs      : Std_Logic;
45 
 
46 
component cpu09
47 
  port (
48 
         clk:        in std_logic;
49 
    rst:             in std_logic;
50 
    rw:      out        std_logic;              -- Asynchronous memory interface
51 
    vma:             out        std_logic;
52 
    address:  out       std_logic_vector(15 downto 0);
53 
    data_in:  in        std_logic_vector(7 downto 0);
54 
         data_out: out std_logic_vector(7 downto 0);
55 
         halt:     in  std_logic;
56 
         hold:     in  std_logic;
57 
         irq:      in  std_logic;
58 
         nmi:      in  std_logic;
59 
         firq:     in  std_logic;
60 
         test_alu: out std_logic_vector(15 downto 0);
61 
         test_cc:  out std_logic_vector(7 downto 0)
62 
  );
63 
end component;
64 
 
65 
 
66 
component sbug_rom
67 
    Port (
68 
       MEMclk   : in  std_logic;
69 
       MEMaddr  : in  std_logic_vector (10 downto 0);
70 
       MEMrdata : out std_logic_vector (7 downto 0)
71 
    );
72 
end component;
73 
 
74 
component block_ram
75 
    Port (
76 
       MEMclk   : in  std_logic;
77 
       MEMcs    : in  std_logic;
78 
                 MEMrw    : in  std_logic;
79 
       MEMaddr  : in  std_logic_vector (10 downto 0);
80 
       MEMrdata : out std_logic_vector (7 downto 0);
81 
       MEMwdata : in  std_logic_vector (7 downto 0)
82 
    );
83 
end component;
84 
 
85 
begin
86 
my_cpu : cpu09  port map (
87 
         clk         => SysClk,
88 
    rst      => cpu_reset,
89 
    rw       => cpu_rw,
90 
    vma       => cpu_vma,
91 
    address   => cpu_addr(15 downto 0),
92 
    data_in   => cpu_data_in,
93 
         data_out  => cpu_data_out,
94 
         halt      => cpu_halt,
95 
         hold      => cpu_hold,
96 
         irq       => cpu_irq,
97 
         nmi       => cpu_nmi,
98 
         firq      => cpu_firq,
99 
         test_alu  => cpu_alu,
100 
         test_cc   => cpu_cc
101 
  );
102 
 
103 
 
104 
my_ram : block_ram port map (
105 
       MEMclk   => SysClk,
106 
                 MEMcs    => ram_cs,
107 
                 MEMrw    => cpu_rw,
108 
       MEMaddr  => cpu_addr(10 downto 0),
109 
       MEMrdata => ram_data_out,
110 
       MEMwdata => cpu_data_out
111 
    );
112 
 
113 
my_rom : sbug_rom port map (
114 
       MEMclk   => SysClk,
115 
       MEMaddr  => cpu_addr(10 downto 0),
116 
       MEMrdata => rom_data_out
117 
    );
118 
 
119 
  -- *** Test Bench - User Defined Section ***
120 
   tb : PROCESS
121 
        variable count : integer;
122 
   BEGIN
123 
 
124 
        cpu_reset <= '0';
125 
        SysClk <= '0';
126 
   cpu_irq <= '0';
127 
   cpu_nmi <= '0';
128 
        cpu_firq <= '0';
129 
   cpu_halt <= '0';
130 
        cpu_hold <= '0';
131 
 
132 
                for count in 0 to 512 loop
133 
                        SysClk <= '0';
134 
                        if count = 0 then
135 
                                cpu_reset <= '1';
136 
                        elsif count = 1 then
137 
                                cpu_reset <= '0';
138 
                        end if;
139 
                        wait for 100 ns;
140 
                        SysClk <= '1';
141 
                        wait for 100 ns;
142 
                end loop;
143 
 
144 
      wait; -- will wait forever
145 
   END PROCESS;
146 
-- *** End Test Bench - User Defined Section ***
147 
 
148 
 
149 
  rom : PROCESS( cpu_addr, rom_data_out, ram_data_out )
150 
  begin
151 
    if( cpu_addr(15 downto 11) = "11111" ) then
152 
      cpu_data_in <= rom_data_out;
153 
                ram_cs <= '0';
154 
         else
155 
      cpu_data_in <= ram_data_out;
156 
                ram_cs <= '1';
157 
         end if;
158 
  end process;
159 
 
160 
end behavior; --===================== End of architecture =======================--
161 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.