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[/] [System09/] [tags/] [V10/] [rtl/] [vhdl/] [txunit2.vhd] - Blame information for rev 66

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1 2 dilbert57 
--===========================================================================--
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--
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--  S Y N T H E Z I A B L E    miniUART   C O R E
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--
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--  www.OpenCores.Org - January 2000
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--  This core adheres to the GNU public license
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--
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-- Design units   : miniUART core for the System68
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--
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-- File name      : txunit2.vhd
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--
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-- Purpose        : Implements an miniUART device for communication purposes
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--                  between the CPU68 processor and the Host computer through
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--                  an RS-232 communication protocol.
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--
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-- Dependencies   : IEEE.Std_Logic_1164
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--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-- Revision list
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-- Version   Author                 Date                        Changes
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--
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-- 0.1      Ovidiu Lupas       15 January 2000                 New model
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-- 2.0      Ovidiu Lupas       17 April   2000    unnecessary variable removed
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--  olupas@opencores.org
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--
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-- 3.0      John Kent           5 January 2003    added 6850 word format control
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-- 3.1      John Kent          12 January 2003    Rearranged state machine code
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-- 3.2      John Kent          30 March 2003      Revamped State machine
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-- 3.3      John Kent           6 September 2003  Changed Clock Edge.
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--
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--  dilbert57@opencores.org
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--
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-------------------------------------------------------------------------------
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-- Description    :
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-------------------------------------------------------------------------------
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-- Entity for the Tx Unit                                                    --
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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-- Transmitter unit
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-------------------------------------------------------------------------------
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entity TxUnit is
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  port (
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     Clk    : in  Std_Logic;  -- Clock signal
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     Reset  : in  Std_Logic;  -- Reset input
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     Enable : in  Std_Logic;  -- Enable input
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     LoadD  : in  Std_Logic;  -- Load transmit data
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          Format : in  Std_Logic_Vector(2 downto 0); -- word format
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     TxD    : out Std_Logic;  -- RS-232 data output
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     TBE    : out Std_Logic;  -- Tx buffer empty
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     DataO  : in  Std_Logic_Vector(7 downto 0));
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end; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-- Architecture for TxUnit
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-------------------------------------------------------------------------------
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architecture Behaviour of TxUnit is
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  type TxStateType is (TxReset_State, TxIdle_State, Start_State, Data_State, Parity_State, Stop_State );
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  -----------------------------------------------------------------------------
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  -- Signals
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  -----------------------------------------------------------------------------
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  signal TBuff    : Std_Logic_Vector(7 downto 0); -- transmit buffer
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  signal tmpTBufE : Std_Logic;                    -- Transmit Buffer Empty
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  signal TReg     : Std_Logic_Vector(7 downto 0); -- transmit register
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  signal TxParity : Std_logic;                    -- Parity Bit
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  signal DataCnt  : Std_Logic_Vector(3 downto 0); -- Data Bit Counter
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  signal tmpTRegE : Std_Logic;                    --  Transmit Register empty
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  signal TxState  : TxStateType;
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  signal NextTReg     : Std_Logic_Vector(7 downto 0); -- transmit register
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  signal NextTxParity : Std_logic;                    -- Parity Bit
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  signal NextDataCnt  : Std_Logic_Vector(3 downto 0); -- Data Bit Counter
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  signal NextTRegE    : Std_Logic;                    --  Transmit Register empty
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  signal NextTxState  : TxStateType;
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begin
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  ---------------------------------------------------------------------
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  -- Transmitter activation process
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  ---------------------------------------------------------------------
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  TxSync : process(Clk, Reset, Enable, LoadD, DataO, tmpTBufE, tmpTRegE, TBuff )
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  begin
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     if Clk'event and Clk = '0' then
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        if Reset = '1' then
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           tmpTBufE <= '1';
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                          TBuff    <= "00000000";
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        else
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                     if LoadD = '1' then
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                            TBuff <= DataO;
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             tmpTBufE <= '0';
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                          else
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                            TBuff <= TBuff;
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             if (Enable = '1') and (tmpTBufE = '0') and (tmpTRegE = '1') then
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               tmpTBufE <= '1';
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                                 else
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               tmpTBufE <= tmpTBufE;
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                                 end if;
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                          end if;
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        end if; -- reset
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    end if; -- clk
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    TBE <= tmpTBufE;
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  end process;
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  -----------------------------------------------------------------------------
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  -- Implements the Tx unit
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  -----------------------------------------------------------------------------
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 TxProc :  process(TxState, TBuff, TReg, TxParity, DataCnt, Format, tmpTRegE, tmpTBufE)
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  begin
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    case TxState is
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         when TxReset_State =>
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      TxD          <= '1';
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           NextTReg     <= "00000000";
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           NextTxParity <= '0';
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                NextDataCnt  <= "0000";
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                NextTRegE    <= '1';
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      NextTxState  <= TxIdle_State;
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    when Start_State =>
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      TxD          <= '0';           -- Start bit
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                NextTReg     <= TReg;
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           NextTxParity <= '0';
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                if Format(2) = '0' then
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                  NextDataCnt <= "0110";       -- 7 data + parity
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           else
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        NextDataCnt <= "0111";       -- 8 data
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           end if;
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      NextTRegE    <= '0';
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      NextTxState  <= Data_State;
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    when Data_State =>
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      TxD          <= TReg(0);
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      NextTReg     <= '1' & TReg(7 downto 1);
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      NextTxParity <= TxParity xor TReg(0);
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      NextTRegE    <= '0';
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                NextDataCnt  <= DataCnt - "0001";
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                if DataCnt = "0000" then
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             if (Format(2) = '1') and (Format(1) = '0') then
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                         if Format(0) = '0' then            -- 8 data bits
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            NextTxState <= Stop_State;       -- 2 stops
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                         else
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                                NextTxState <= TxIdle_State;     -- 1 stop
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                    end if;
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                  else
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                         NextTxState <= Parity_State;       -- parity
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                  end if;
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                else
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        NextTxState  <= Data_State;
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                end if;
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    when Parity_State =>           -- 7/8 data + parity bit
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           if Format(0) = '0' then
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                        TxD <= not( TxParity );   -- even parity
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                else
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                        TXD <= TxParity;          -- odd parity
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           end if;
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                NextTreg   <= Treg;
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                NextTxParity <= '0';
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      NextTRegE <= '0';
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                NextDataCnt <= "0000";
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                if Format(1) = '0' then
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                        NextTxState <= Stop_State; -- 2 stops
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                else
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                        NextTxState <= TxIdle_State; -- 1 stop
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                end if;
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    when Stop_State => -- first stop bit
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      TxD          <= '1';           -- 2 stop bits
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           NextTreg     <= Treg;
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                NextTxParity <= '0';
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                NextDataCnt  <= "0000";
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      NextTRegE    <= '0';
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                NextTxState  <= TxIdle_State;
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    when others =>  -- TxIdle_State (2nd Stop bit)
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      TxD          <= '1';
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           NextTreg     <= TBuff;
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                NextTxParity <= '0';
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                NextDataCnt  <= "0000";
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                if (tmpTBufE = '0') and (tmpTRegE = '1') then
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         NextTRegE   <= '0';
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         NextTxState <= Start_State;
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           else
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         NextTRegE   <= '1';
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         NextTxState <= TxIdle_State;
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                end if;
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    end case; -- TxState
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  end process;
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  --
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  -- Tx State Machine
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  -- Slowed down by "Enable"
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  --
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  TX_State_Machine: process( Clk, Reset, Enable,
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                             Treg,     NextTReg,
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                             TxParity, NextTxParity,
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                                                                          DataCnt,  NextDataCnt,
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                                                                          tmpTRegE, NextTRegE,
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                                                                     TxState,  NextTxState )
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  begin
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    if Clk'event and Clk = '0' then
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           if Reset = '1' then
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              Treg     <= "00000000";
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                   TxParity <= '0';
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                   DataCnt  <= "0000";
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         tmpTRegE <= '1';
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                   TxState  <= TxReset_State;
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                else
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                   if Enable = '1' then
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                Treg     <= NextTreg;
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                     TxParity <= NextTxParity;
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                     DataCnt  <= NextDataCnt;
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           tmpTRegE <= NextTRegE;
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                     TxState  <= NextTxState;
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                        else
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                Treg     <= Treg;
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                     TxParity <= TxParity;
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                     DataCnt  <= DataCnt;
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           tmpTRegE <= tmpTRegE;
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                          TxState  <= TxState;
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                        end if;
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                end if;
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         end if;
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  end process;
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end Behaviour; --=================== End of architecture ====================--

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