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[/] [System09/] [tags/] [pre_mkfiles_rev1_merge/] [rtl/] [System09_Xess_XSA-3S1000/] [System09_Xess_XSA-3S1000.vhd] - Blame information for rev 19

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1 19 dilbert57
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (ACIA_6850.vhd)      ACIA / UART
30
--                             (ACIA_RX.vhd)
31
--                             (ACIA_TX.vhd)
32
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
33
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
34
--                             (ps2_keyboard.vhd)
35
--                             (keymap_rom_slice.vhd) Key map table 
36
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
37
--                             (char_rom2k_b16.vhd)
38
--                             (ram2k_b16.vhd)
39
--                  timer      (timer.vhd)            Interrupt timer
40
--                  trap       (trap.vhd)             Bus condition trap logic
41
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
42
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
43
--                  
44
-- 
45
-- Author         : John E. Kent      
46
--                  dilbert57@opencores.org      
47
--
48
-- Memory Map     :
49
--
50
-- $0000 - User program RAM (32K Bytes)
51
-- $C000 - Flex Operating System memory (8K Bytes)
52
-- $E000 - ACIA (SWTPc)
53
-- $E010 - Reserved for FD1771 FDC (SWTPc)
54
-- $E020 - Keyboard
55
-- $E030 - VDU
56
-- $E040 - IDE / Compact Flash interface
57
-- $E050 - Timer
58
-- $E060 - Bus trap
59
-- $E070 - Reserced for Parallel I/O (B5-X300)
60
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
61
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
62
-- $F000 - Sys09Bug monitor Program (4K Bytes)
63
--
64
--===========================================================================----
65
--
66
-- Revision History:
67
--===========================================================================--
68
-- Version 0.1 - 20 March 2003
69
-- Version 0.2 - 30 March 2003
70
-- Version 0.3 - 29 April 2003
71
-- Version 0.4 - 29 June 2003
72
--
73
-- Version 0.5 - 19 July 2003
74
-- prints out "Hello World"
75
--
76
-- Version 0.6 - 5 September 2003
77
-- Runs SBUG
78
--
79
-- Version 1.0- 6 Sep 2003 - John Kent
80
-- Inverted SysClk
81
-- Initial release to Open Cores
82
--
83
-- Version 1.1 - 17 Jan 2004 - John Kent
84
-- Updated miniUart.
85
--
86
-- Version 1.2 - 25 Jan 2004 - John Kent
87
-- removed signals "test_alu" and "test_cc" 
88
-- Trap hardware re-instated.
89
--
90
-- Version 1.3 - 11 Feb 2004 - John Kent
91
-- Designed forked off to produce System09_VDU
92
-- Added VDU component
93
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
94
-- UART Runs at 57.6 Kbps
95
--
96
-- Version 2.0 - 2 September 2004 - John Kent
97
-- ported to Digilent Xilinx Spartan3 starter board
98
--      removed Compact Flash and Trap Logic.
99
-- Replaced SBUG with KBug9s
100
--
101
-- Version 3.0 - 29th August 2006 - John Kent
102
-- Adapted to XSA-3S1000 board.
103
-- Removed DAT and miniUART.
104
-- Used 32KBytes of Block RAM.
105
--
106
-- Version 3.1 - 15th January 2007 - John Kent
107
-- Modified vdu8 interface
108
-- Added a clock divider
109
--
110
-- Version 3.2 - 25th February 2007 - John Kent
111
-- reinstated ACIA_6850 and ACIA_Clock
112
-- Updated VDU8 & Keyboard with generic parameters
113
-- Defined Constants for clock speed calculations
114
--
115
-- Version 3.3 - 1st July 2007 - John Kent
116
-- Made VDU mono to save on one RAMB16
117
-- Used distributed memory for Key Map ROM to save one RAMB16
118
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
119
-- Added timer and trap logic
120
-- Added IDE Interface for Compact Flash
121
-- Replaced KBug9s and stack with Sys09Bug.
122
--
123
--===========================================================================--
124
library ieee;
125
   use ieee.std_logic_1164.all;
126
   use IEEE.STD_LOGIC_ARITH.ALL;
127
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
128
   use ieee.numeric_std.all;
129
library unisim;
130
   use unisim.vcomponents.all;
131
 
132
entity My_System09 is
133
  port(
134
    Clk100      : in  Std_Logic;  -- 100MHz Clock input
135
         SW2_N       : in  Std_logic;  -- Master Reset input (active low)
136
         SW3_N       : in  Std_logic;  -- Non Maskable Interrupt input (active low)
137
 
138
         -- PS/2 Keyboard
139
         ps2_clk     : inout Std_logic;
140
         ps2_dat     : inout Std_Logic;
141
 
142
         -- CRTC output signals
143
         vga_vsync_n : out Std_Logic;
144
    vga_hsync_n : out Std_Logic;
145
    vga_blue    : out std_logic_vector(2 downto 0);
146
    vga_green   : out std_logic_vector(2 downto 0);
147
    vga_red     : out std_logic_vector(2 downto 0);
148
 
149
    -- RS232 Port
150
         RS232_RXD   : in  Std_Logic;
151
         RS232_TXD   : out Std_Logic;
152
--  RS232_DCD   : in  Std_logic;
153
    RS232_CTS   : in  Std_Logic;
154
    RS232_RTS   : out Std_Logic;
155
 
156
         -- LEDS & Switches
157
         STATUS_LED  : out std_logic_vector(6 downto 0);
158
 
159
-- Compact Flash
160
--    ide_rst_n   : out std_logic;
161
         ide_cs0_n   : out std_logic;
162
         ide_cs1_n   : out std_logic;
163
    ide_ior_n    : out std_logic;
164
    ide_iow_n    : out std_logic;
165
--       ide_cs16_n  : out std_logic;
166
    ide_a       : out std_logic_vector(2 downto 0);
167
    ide_d       : inout std_logic_vector(15 downto 0);
168
--    ide_d       : inout std_logic_vector(7 downto 0);
169
 
170
         ethernet_cs_n : out std_logic
171
         );
172
end My_System09;
173
 
174
-------------------------------------------------------------------------------
175
-- Architecture for System09
176
-------------------------------------------------------------------------------
177
architecture rtl of My_System09 is
178
 
179
  -----------------------------------------------------------------------------
180
  -- constants
181
  -----------------------------------------------------------------------------
182
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
183
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
184
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
185
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
186
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
187
 
188
  type hold_state_type is ( hold_release_state, hold_request_state );
189
 
190
  -----------------------------------------------------------------------------
191
  -- Signals
192
  -----------------------------------------------------------------------------
193
  signal rst_n          :  Std_logic;  -- Master Reset input (active low)
194
  signal nmi_n          :  Std_logic;  -- Non Maskable Interrupt input (active low)
195
 
196
  -- BOOT ROM
197
  signal rom_cs         : Std_logic;
198
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
199
 
200
  -- Flex Memory & Monitor Stack
201
  signal flex_cs        : Std_logic;
202
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
203
 
204
  -- ACIA/UART Interface signals
205
  signal uart_data_out  : Std_Logic_Vector(7 downto 0);
206
  signal uart_cs        : Std_Logic;
207
  signal uart_irq       : Std_Logic;
208
  signal uart_clk       : Std_Logic;
209
  signal rxd            : Std_Logic;
210
  signal txd            : Std_Logic;
211
  signal DCD_n          : Std_Logic;
212
  signal RTS_n          : Std_Logic;
213
  signal CTS_n          : Std_Logic;
214
 
215
  -- keyboard port
216
  signal keyboard_data_out : std_logic_vector(7 downto 0);
217
  signal keyboard_cs       : std_logic;
218
  signal keyboard_irq      : std_logic;
219
 
220
  -- RAM
221
  signal ram_cs         : std_logic; -- memory chip select
222
  signal ram_data_out   : std_logic_vector(7 downto 0);
223
 
224
  -- CPU Interface signals
225
  signal cpu_reset      : Std_Logic;
226
  signal cpu_clk        : Std_Logic;
227
  signal cpu_rw         : std_logic;
228
  signal cpu_vma        : std_logic;
229
  signal cpu_halt       : std_logic;
230
  signal cpu_hold       : std_logic;
231
  signal cpu_firq       : std_logic;
232
  signal cpu_irq        : std_logic;
233
  signal cpu_nmi        : std_logic;
234
  signal cpu_addr       : std_logic_vector(15 downto 0);
235
  signal cpu_data_in    : std_logic_vector(7 downto 0);
236
  signal cpu_data_out   : std_logic_vector(7 downto 0);
237
 
238
  -- Video Display Unit
239
  signal vdu_cs         : std_logic;
240
  signal vdu_data_out   : std_logic_vector(7 downto 0);
241
  signal vga_red_o      : std_logic;
242
  signal vga_green_o    : std_logic;
243
  signal vga_blue_o     : std_logic;
244
 
245
  -- timer
246
  signal timer_data_out : std_logic_vector(7 downto 0);
247
  signal timer_cs       : std_logic;
248
  signal timer_irq      : std_logic;
249
  signal timer_out      : std_logic;
250
 
251
  -- trap
252
  signal trap_cs        : std_logic;
253
  signal trap_data_out  : std_logic_vector(7 downto 0);
254
  signal trap_irq       : std_logic;
255
 
256
  -- compact flash port
257
  signal ide_data_out   : std_logic_vector(7 downto 0);
258
  signal ide_cs         : std_logic;
259
  signal ide_ior        : std_logic;
260
  signal ide_iow        : std_logic;
261
  signal ide_hold       : std_logic;
262
  signal ide_release    : std_logic;
263
  signal ide_count      : std_logic_vector(3 downto 0);
264
  signal ide_hold_state : hold_state_type;
265
 
266
--  signal BaudCount    : std_logic_vector(5 downto 0);
267
  signal CountL         : std_logic_vector(23 downto 0);
268
  signal clk_count      : std_logic_vector(1 downto 0);
269
  signal Clk50          : std_logic;
270
  signal Clk25          : std_logic;
271
  signal SysClk         : std_logic; -- buffered 50 MHz clock
272
  signal pix_clk        : std_logic;
273
 
274
-----------------------------------------------------------------
275
--
276
-- CPU09 CPU core
277
--
278
-----------------------------------------------------------------
279
 
280
component cpu09
281
  port (
282
         clk:        in std_logic;
283
    rst:      in        std_logic;
284
    rw:      out        std_logic;              -- Asynchronous memory interface
285
    vma:             out        std_logic;
286
    address:  out       std_logic_vector(15 downto 0);
287
    data_in:  in        std_logic_vector(7 downto 0);
288
         data_out: out std_logic_vector(7 downto 0);
289
         halt:     in  std_logic;
290
         hold:     in  std_logic;
291
         irq:      in  std_logic;
292
         nmi:      in  std_logic;
293
         firq:     in  std_logic
294
  );
295
end component;
296
 
297
 
298
----------------------------------------
299
--
300
-- 4K Block RAM Monitor ROM
301
--
302
----------------------------------------
303
component mon_rom
304
    Port (
305
       clk   : in  std_logic;
306
                 rst   : in  std_logic;
307
                 cs    : in  std_logic;
308
                 rw    : in  std_logic;
309
       addr  : in  std_logic_vector (11 downto 0);
310
       rdata : out std_logic_vector (7 downto 0);
311
       wdata : in  std_logic_vector (7 downto 0)
312
    );
313
end component;
314
 
315
 
316
----------------------------------------
317
--
318
-- 8KBytes Block RAM for FLEX9
319
-- $C000 - $DFFF
320
--
321
----------------------------------------
322
component flex_ram
323
  Port (
324
    clk      : in  std_logic;
325
    rst      : in  std_logic;
326
    cs       : in  std_logic;
327
    rw       : in  std_logic;
328
    addr     : in  std_logic_vector (12 downto 0);
329
    rdata    : out std_logic_vector (7 downto 0);
330
    wdata    : in  std_logic_vector (7 downto 0)
331
    );
332
end component;
333
 
334
-----------------------------------------------------------------
335
--
336
-- 6850 Compatible ACIA / UART
337
--
338
-----------------------------------------------------------------
339
 
340
component ACIA_6850
341
  port (
342
     clk      : in  Std_Logic;  -- System Clock
343
     rst      : in  Std_Logic;  -- Reset input (active high)
344
     cs       : in  Std_Logic;  -- miniUART Chip Select
345
     rw       : in  Std_Logic;  -- Read / Not Write
346
     irq      : out Std_Logic;  -- Interrupt
347
     Addr     : in  Std_Logic;  -- Register Select
348
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
349
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
350
     RxC      : in  Std_Logic;  -- Receive Baud Clock
351
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
352
     RxD      : in  Std_Logic;  -- Receive Data
353
     TxD      : out Std_Logic;  -- Transmit Data
354
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
355
     CTS_n    : in  Std_Logic;  -- Clear To Send
356
     RTS_n    : out Std_Logic );  -- Request To send
357
end component;
358
 
359
 
360
-----------------------------------------------------------------
361
--
362
-- ACIA Clock divider
363
--
364
-----------------------------------------------------------------
365
 
366
component ACIA_Clock
367
  generic (
368
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
369
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
370
  );
371
  port (
372
     clk      : in  Std_Logic;  -- System Clock Input
373
          ACIA_clk : out Std_logic   -- ACIA Clock output
374
  );
375
end component;
376
 
377
 
378
----------------------------------------
379
--
380
-- PS/2 Keyboard
381
--
382
----------------------------------------
383
 
384
component keyboard
385
  generic(
386
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
387
  );
388
  port(
389
  clk             : in    std_logic;
390
  rst             : in    std_logic;
391
  cs              : in    std_logic;
392
  rw              : in    std_logic;
393
  addr            : in    std_logic;
394
  data_in         : in    std_logic_vector(7 downto 0);
395
  data_out        : out   std_logic_vector(7 downto 0);
396
  irq             : out   std_logic;
397
  kbd_clk         : inout std_logic;
398
  kbd_data        : inout std_logic
399
  );
400
end component;
401
 
402
----------------------------------------
403
--
404
-- Video Display Unit.
405
--
406
----------------------------------------
407
component vdu8_mono
408
      generic(
409
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
410
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
411
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
412
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
413
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
414
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
415
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
416
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
417
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
418
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
419
             VGA_VER_SYNC           : integer := 1;  -- LINES
420
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
421
      );
422
      port(
423
                -- control register interface
424
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
425
      vdu_rst      : in  std_logic;
426
                vdu_cs       : in  std_logic;
427
                vdu_rw       : in  std_logic;
428
                vdu_addr     : in  std_logic_vector(2 downto 0);
429
      vdu_data_in  : in  std_logic_vector(7 downto 0);
430
      vdu_data_out : out std_logic_vector(7 downto 0);
431
 
432
      -- vga port connections
433
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
434
      vga_red_o    : out std_logic;
435
      vga_green_o  : out std_logic;
436
      vga_blue_o   : out std_logic;
437
      vga_hsync_o  : out std_logic;
438
      vga_vsync_o  : out std_logic
439
   );
440
end component;
441
 
442
 
443
----------------------------------------
444
--
445
-- Timer module
446
--
447
----------------------------------------
448
 
449
component timer
450
  port (
451
     clk       : in std_logic;
452
     rst       : in std_logic;
453
     cs        : in std_logic;
454
     rw        : in std_logic;
455
     addr      : in std_logic;
456
     data_in   : in std_logic_vector(7 downto 0);
457
          data_out  : out std_logic_vector(7 downto 0);
458
          irq       : out std_logic;
459
     timer_in  : in std_logic;
460
          timer_out : out std_logic
461
          );
462
end component;
463
 
464
------------------------------------------------------------
465
--
466
-- Bus Trap logic
467
--
468
------------------------------------------------------------
469
 
470
component trap
471
        port (
472
         clk        : in  std_logic;
473
    rst        : in  std_logic;
474
    cs         : in  std_logic;
475
    rw         : in  std_logic;
476
    vma        : in  std_logic;
477
    addr       : in  std_logic_vector(15 downto 0);
478
    data_in    : in  std_logic_vector(7 downto 0);
479
         data_out   : out std_logic_vector(7 downto 0);
480
         irq        : out std_logic
481
  );
482
end component;
483
 
484
----------------------------------------
485
--
486
-- Block RAM program Memory
487
--
488
----------------------------------------
489
component ram_32k
490
    Port (
491
       clk   : in  std_logic;
492
                 rst   : in  std_logic;
493
                 cs    : in  std_logic;
494
                 rw    : in  std_logic;
495
       addr  : in  std_logic_vector (14 downto 0);
496
       rdata : out std_logic_vector (7 downto 0);
497
       wdata : in  std_logic_vector (7 downto 0)
498
    );
499
end component;
500
 
501
--
502
-- Clock buffer
503
--
504
component BUFG
505
   Port (
506
     i: in std_logic;
507
          o: out std_logic
508
  );
509
end component;
510
 
511
begin
512
  -----------------------------------------------------------------------------
513
  -- Instantiation of internal components
514
  -----------------------------------------------------------------------------
515
 
516
my_cpu : cpu09  port map (
517
         clk         => cpu_clk,
518
    rst       => cpu_reset,
519
    rw       => cpu_rw,
520
    vma       => cpu_vma,
521
    address   => cpu_addr(15 downto 0),
522
    data_in   => cpu_data_in,
523
         data_out  => cpu_data_out,
524
         halt      => cpu_halt,
525
         hold      => cpu_hold,
526
         irq       => cpu_irq,
527
         nmi       => cpu_nmi,
528
         firq      => cpu_firq
529
  );
530
 
531
my_rom : mon_rom port map (
532
       clk   => cpu_clk,
533
                 rst   => cpu_reset,
534
                 cs    => rom_cs,
535
                 rw    => '1',
536
       addr  => cpu_addr(11 downto 0),
537
       wdata => cpu_data_out,
538
       rdata => rom_data_out
539
    );
540
 
541
my_flex : flex_ram port map (
542
    clk       => cpu_clk,
543
    rst       => cpu_reset,
544
         cs        => flex_cs,
545
         rw        => cpu_rw,
546
    addr      => cpu_addr(12 downto 0),
547
    rdata     => flex_data_out,
548
    wdata     => cpu_data_out
549
    );
550
 
551
my_uart  : ACIA_6850 port map (
552
         clk         => cpu_clk,
553
         rst       => cpu_reset,
554
    cs        => uart_cs,
555
         rw        => cpu_rw,
556
    irq       => uart_irq,
557
    Addr      => cpu_addr(0),
558
         Datain    => cpu_data_out,
559
         DataOut   => uart_data_out,
560
         RxC       => uart_clk,
561
         TxC       => uart_clk,
562
         RxD       => rxd,
563
         TxD       => txd,
564
         DCD_n     => dcd_n,
565
         CTS_n     => cts_n,
566
         RTS_n     => rts_n
567
         );
568
 
569
 
570
my_ACIA_Clock : ACIA_Clock
571
  generic map(
572
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
573
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
574
  )
575
  port map(
576
    clk        => SysClk,
577
    acia_clk   => uart_clk
578
  );
579
 
580
----------------------------------------
581
--
582
-- PS/2 Keyboard Interface
583
--
584
----------------------------------------
585
my_keyboard : keyboard
586
   generic map (
587
        KBD_Clock_Frequency => CPU_Clock_frequency
588
        )
589
   port map(
590
        clk          => cpu_clk,
591
        rst          => cpu_reset,
592
        cs           => keyboard_cs,
593
        rw           => cpu_rw,
594
        addr         => cpu_addr(0),
595
        data_in      => cpu_data_out(7 downto 0),
596
        data_out     => keyboard_data_out(7 downto 0),
597
        irq          => keyboard_irq,
598
        kbd_clk      => ps2_clk,
599
        kbd_data     => ps2_dat
600
        );
601
 
602
----------------------------------------
603
--
604
-- Video Display Unit instantiation
605
--
606
----------------------------------------
607
my_vdu : vdu8_mono
608
  generic map(
609
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
610
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
611
           VGA_HOR_CHARS          => 80, -- CHARACTERS
612
           VGA_VER_CHARS          => 25, -- CHARACTERS
613
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
614
           VGA_LINES_PER_CHAR     => 16, -- LINES
615
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
616
           VGA_HOR_SYNC           => 96, -- PIXELS
617
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
618
           VGA_VER_BACK_PORCH     => 13, -- LINES
619
           VGA_VER_SYNC           => 1,  -- LINES
620
           VGA_VER_FRONT_PORCH    => 36  -- LINES
621
  )
622
  port map(
623
 
624
                -- Control Registers
625
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
626
      vdu_rst       => cpu_reset,
627
                vdu_cs        => vdu_cs,
628
                vdu_rw        => cpu_rw,
629
                vdu_addr      => cpu_addr(2 downto 0),
630
                vdu_data_in   => cpu_data_out,
631
                vdu_data_out  => vdu_data_out,
632
 
633
      -- vga port connections
634
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
635
      vga_red_o     => vga_red_o,
636
      vga_green_o   => vga_green_o,
637
      vga_blue_o    => vga_blue_o,
638
      vga_hsync_o   => vga_hsync_n,
639
      vga_vsync_o   => vga_vsync_n
640
   );
641
 
642
----------------------------------------
643
--
644
-- Timer Module
645
--
646
----------------------------------------
647
my_timer  : timer port map (
648
    clk       => cpu_clk,
649
         rst       => cpu_reset,
650
    cs        => timer_cs,
651
         rw        => cpu_rw,
652
    addr      => cpu_addr(0),
653
         data_in   => cpu_data_out,
654
         data_out  => timer_data_out,
655
    irq       => timer_irq,
656
         timer_in  => CountL(5),
657
         timer_out => timer_out
658
    );
659
 
660
----------------------------------------
661
--
662
-- Bus Trap Interrupt logic
663
--
664
----------------------------------------
665
my_trap : trap port map (
666
         clk        => cpu_clk,
667
    rst        => cpu_reset,
668
    cs         => trap_cs,
669
    rw         => cpu_rw,
670
         vma        => cpu_vma,
671
    addr       => cpu_addr,
672
    data_in    => cpu_data_out,
673
         data_out   => trap_data_out,
674
         irq        => trap_irq
675
    );
676
 
677
my_ram : ram_32k port map (
678
       clk   => cpu_clk,
679
                 rst   => cpu_reset,
680
                 cs    => ram_cs,
681
                 rw    => cpu_rw,
682
       addr  => cpu_addr(14 downto 0),
683
       rdata => ram_data_out,
684
       wdata => cpu_data_out
685
    );
686
 
687
sys_clk_buffer : BUFG port map(
688
    i => Clk50,
689
         o => SysClk
690
    );
691
 
692
cpu_clk_buffer : BUFG port map(
693
    i => Clk25,
694
         o => cpu_clk
695
    );
696
 
697
pix_clk_buffer : BUFG port map(
698
    i => Clk25,
699
         o => pix_clk
700
    );
701
 
702
----------------------------------------------------------------------
703
--
704
-- Process to decode memory map
705
--
706
----------------------------------------------------------------------
707
 
708
mem_decode: process( cpu_clk,
709
                     cpu_addr, cpu_rw, cpu_vma,
710
                                              rom_data_out,
711
                                                        flex_data_out,
712
                                                   uart_data_out,
713
                                                        keyboard_data_out,
714
                                                        vdu_data_out,
715
                                                        ide_data_out,
716
                                                        timer_data_out,
717
                                                        trap_data_out,
718
                                                        ram_data_out
719
                                                        )
720
begin
721
    case cpu_addr(15 downto 12) is
722
           --
723
                -- Sys09Bug Monitor ROM $F000 - $FFFF
724
                --
725
                when "1111" => -- $F800 - $FFFF
726
                   cpu_data_in <= rom_data_out;
727
                        rom_cs      <= cpu_vma;
728
                        flex_cs     <= '0';
729
                        uart_cs     <= '0';
730
                        keyboard_cs <= '0';
731
                        vdu_cs      <= '0';
732
                        ide_cs      <= '0';
733
                        timer_cs    <= '0';
734
                        trap_cs     <= '0';
735
                        ram_cs      <= '0';
736
 
737
      --
738
                -- IO Devices $E000 - $E7FF
739
                --
740
                when "1110" => -- $E000 - $E7FF
741
                        rom_cs    <= '0';
742
                        flex_cs   <= '0';
743
                        ram_cs    <= '0';
744
                   case cpu_addr(7 downto 4) is
745
                        --
746
                        -- UART / ACIA $E000
747
                        --
748
                        when "0000" => -- $E000
749
                     cpu_data_in <= uart_data_out;
750
                          uart_cs     <= cpu_vma;
751
                          keyboard_cs <= '0';
752
                          vdu_cs      <= '0';
753
                          ide_cs      <= '0';
754
                          timer_cs    <= '0';
755
                          trap_cs     <= '0';
756
 
757
         --
758
         -- Reserved
759
                        -- Floppy Disk Controller port $E010 - $E01F
760
                        --
761
                        when "0001" => -- $E010
762
           cpu_data_in <= "00000000";
763
                          uart_cs     <= '0';
764
                          keyboard_cs <= '0';
765
                          vdu_cs      <= '0';
766
                          ide_cs      <= '0';
767
                          timer_cs    <= '0';
768
                          trap_cs     <= '0';
769
 
770
         --
771
         -- Keyboard port $E020 - $E02F
772
                        --
773
                        when "0010" => -- $E020
774
           cpu_data_in <= keyboard_data_out;
775
                          uart_cs     <= '0';
776
                          keyboard_cs <= cpu_vma;
777
                          vdu_cs      <= '0';
778
                          ide_cs      <= '0';
779
                          timer_cs    <= '0';
780
                          trap_cs     <= '0';
781
 
782
         --
783
         -- VDU port $E030 - $E03F
784
                        --
785
                        when "0011" => -- $E030
786
           cpu_data_in <= vdu_data_out;
787
                          uart_cs     <= '0';
788
                          keyboard_cs <= '0';
789
                          vdu_cs      <= cpu_vma;
790
                          ide_cs      <= '0';
791
                          timer_cs    <= '0';
792
                          trap_cs     <= '0';
793
 
794
         --
795
                        -- Compact Flash $E040 - $E04F
796
                        --
797
                        when "0100" => -- $E040
798
           cpu_data_in <= ide_data_out;
799
                          uart_cs     <= '0';
800
                          keyboard_cs <= '0';
801
                          vdu_cs      <= '0';
802
           ide_cs      <= cpu_vma;
803
                          timer_cs    <= '0';
804
                          trap_cs     <= '0';
805
 
806
         --
807
         -- Timer $E050 - $E05F
808
                        --
809
                        when "0101" => -- $E050
810
           cpu_data_in <= timer_data_out;
811
                          uart_cs     <= '0';
812
                          keyboard_cs <= '0';
813
                          vdu_cs      <= '0';
814
                          ide_cs      <= '0';
815
           timer_cs    <= cpu_vma;
816
                          trap_cs     <= '0';
817
 
818
         --
819
         -- Bus Trap Logic $E060 - $E06F
820
                        --
821
                        when "0110" => -- $E060
822
           cpu_data_in <= trap_data_out;
823
                          uart_cs     <= '0';
824
                          keyboard_cs <= '0';
825
                          vdu_cs      <= '0';
826
                          ide_cs      <= '0';
827
           timer_cs    <= '0';
828
                          trap_cs     <= cpu_vma;
829
 
830
                        when others => -- $E070 to $E7FF
831
           cpu_data_in <= "00000000";
832
                          uart_cs     <= '0';
833
                          keyboard_cs <= '0';
834
                          vdu_cs      <= '0';
835
                          ide_cs      <= '0';
836
                          timer_cs    <= '0';
837
                          trap_cs     <= '0';
838
                   end case;
839
 
840
                --
841
                -- Flex RAM $C000 - $DFFF
842
                --
843
                when "1100" | "1101" => -- $C000 - $DFFF
844
                   cpu_data_in <= rom_data_out;
845
                        rom_cs      <= '0';
846
                        flex_cs     <= cpu_vma;
847
                        uart_cs     <= '0';
848
                        keyboard_cs <= '0';
849
                        vdu_cs      <= '0';
850
         ide_cs      <= '0';
851
         timer_cs    <= '0';
852
         trap_cs     <= '0';
853
                        ram_cs      <= '0';
854
                --
855
                -- Everything else is RAM
856
                --
857
                when others =>
858
                  cpu_data_in <= ram_data_out;
859
                  rom_cs      <= '0';
860
                  flex_cs     <= '0';
861
                  uart_cs     <= '0';
862
                  keyboard_cs <= '0';
863
                  vdu_cs      <= '0';
864
        ide_cs      <= '0';
865
        timer_cs    <= '0';
866
        trap_cs     <= '0';
867
                  ram_cs      <= cpu_vma;
868
         end case;
869
end process;
870
 
871
 
872
--
873
-- Compact Flash Control
874
--
875
compact_flash: process(
876
                 cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
877
                                          ide_cs, ide_ior, ide_iow, ide_d )
878
begin
879
--       ide_rst_n  <= rst_n;
880
         ide_cs0_n  <= not( ide_cs ) or cpu_addr(3);
881
         ide_cs1_n  <= not( ide_cs and cpu_addr(3));
882
--       ide_cs16_n <= '1';
883
         ide_iow     <= ide_cs and (not cpu_rw);
884
         ide_ior    <= ide_cs and cpu_rw;
885
         ide_iow_n  <= not ide_iow;
886
         ide_ior_n  <= not ide_ior;
887
         ide_a      <= cpu_addr(2 downto 0);
888
         if ide_iow = '1' then
889
           ide_d(7 downto 0) <= cpu_data_out;
890
         else
891
           ide_d(7 downto 0) <= "ZZZZZZZZ";
892
         end if;
893
         ide_data_out <= ide_d(7 downto 0);
894
         ide_d(15 downto 8) <= "ZZZZZZZZ";
895
end process;
896
 
897
--
898
-- Hold CF access       for a few cycles
899
--
900
ide_hold_proc: process( cpu_clk, rst_n )
901
begin
902
    if rst_n = '0' then
903
                 ide_release    <= '0';
904
                 ide_count      <= "0000";
905
            ide_hold_state <= hold_release_state;
906
         elsif cpu_clk'event and cpu_clk='0' then
907
            case ide_hold_state is
908
                 when hold_release_state =>
909
          ide_release <= '0';
910
                    if ide_cs = '1' then
911
                            ide_count      <= "0011";
912
                                 ide_hold_state <= hold_request_state;
913
                         end if;
914
 
915
                 when hold_request_state =>
916
                    ide_count <= ide_count - "0001";
917
                         if ide_count = "0000" then
918
             ide_release    <= '1';
919
                                 ide_hold_state <= hold_release_state;
920
                         end if;
921
       when others =>
922
                    null;
923
       end case;
924
         end if;
925
end process;
926
 
927
--
928
-- Interrupts and other bus control signals
929
--
930
interrupts : process( rst_n,
931
                                                         ide_cs, ide_hold, ide_release,
932
                      uart_irq,
933
                                                         keyboard_irq,
934
                                                         trap_irq,
935
                                                         timer_irq
936
                                                         )
937
begin
938
    ide_hold   <= ide_cs and (not ide_release);
939
         cpu_reset <= not rst_n; -- CPU reset is active high
940
    cpu_irq   <= uart_irq or keyboard_irq;
941
         cpu_nmi   <= trap_irq or not( nmi_n );
942
         cpu_firq  <= timer_irq;
943
         cpu_halt  <= '0';
944
         cpu_hold  <= ide_hold;
945
end process;
946
 
947
 
948
--
949
-- Flash 7 segment LEDS
950
--
951
my_led_flasher: process( SysClk, rst_n, CountL )
952
begin
953
    if rst_n = '0' then
954
                   CountL <= "000000000000000000000000";
955
    elsif(SysClk'event and SysClk = '0') then
956
                   CountL <= CountL + 1;
957
    end if;
958
         STATUS_LED(6 downto 0) <= CountL(23 downto 17);
959
end process;
960
 
961
--
962
-- Generate a 50 MHz Clock from 100 MHz
963
--
964
my_prescaler : process( Clk100, clk_count )
965
begin
966
  if Clk100'event and Clk100 = '0' then
967
    clk_count <= clk_count + "01";
968
  end if;
969
  Clk50 <= clk_count(0);
970
  Clk25 <= clk_count(1);
971
end process;
972
 
973
--
974
-- Push buttons
975
--
976
my_switch_assignments : process( SW2_N, SW3_N )
977
begin
978
  rst_n    <= SW2_N;
979
  nmi_n    <= SW3_N;
980
  --
981
  -- Disable the ethernet controller
982
  --
983
  ethernet_cs_n <= '1';
984
end process;
985
 
986
--
987
-- RS232 signals:
988
--
989
my_uart_assignments : process( RS232_RXD, RS232_CTS, rxd, rts_n )
990
begin
991
  rxd       <= RS232_RXD;
992
  cts_n     <= RS232_CTS;
993
  dcd_n     <= '0';
994
  RS232_TXD <= txd;
995
  RS232_RTS <= rts_n;
996
end process;
997
 
998
--
999
-- VGA ouputs
1000
--
1001
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
1002
begin
1003
  VGA_red(0)   <= vga_red_o;
1004
  VGA_red(1)   <= vga_red_o;
1005
  VGA_red(2)   <= vga_red_o;
1006
  VGA_green(0) <= vga_green_o;
1007
  VGA_green(1) <= vga_green_o;
1008
  VGA_green(2) <= vga_green_o;
1009
  VGA_blue(0)  <= vga_blue_o;
1010
  VGA_blue(1)  <= vga_blue_o;
1011
  VGA_blue(2)  <= vga_blue_o;
1012
end process;
1013
 
1014
 
1015
end rtl; --===================== End of architecture =======================--
1016
 

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