OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Cyclone2/] [ram2k.vhd] - Blame information for rev 117

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 116 dilbert57
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
 
4
LIBRARY altera_mf;
5
USE altera_mf.all;
6
 
7
ENTITY spram IS
8
        GENERIC
9
        (
10
                INIT_FILE               : string        := "";
11
                WORD_COUNT              : natural       := 2048;
12
                ADDR_WIDTH              : natural       := 11;
13
                DATA_WIDTH              : natural       := 8;
14
                REG_OUT                 : string        := "UNREGISTERED"
15
        );
16
        PORT
17
        (
18
                clk                             : IN  STD_LOGIC ;
19
                rst                             : IN  STD_LOGIC ;
20
                cs                              : IN  STD_LOGIC ;
21
                addr                    : IN  STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
22
                rw                              : IN  STD_LOGIC ;
23
                data_in                 : IN  STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
24
                data_out                : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0)
25
        );
26
END spram;
27
 
28
ARCHITECTURE SYN OF spram IS
29
 
30
        COMPONENT altsyncram
31
        GENERIC (
32
                clock_enable_input_a    : STRING;
33
                clock_enable_output_a   : STRING;
34
                init_file                               : STRING;
35
                intended_device_family  : STRING;
36
                lpm_hint                                : STRING;
37
                lpm_type                                : STRING;
38
                numwords_a                              : NATURAL;
39
                operation_mode                  : STRING;
40
                outdata_aclr_a                  : STRING;
41
                outdata_reg_a                   : STRING;
42
                power_up_uninitialized  : STRING;
43
                widthad_a                               : NATURAL;
44
                width_a                                 : NATURAL;
45
                width_byteena_a                 : NATURAL
46
        );
47
        PORT (
48
                clock0          : IN  STD_LOGIC ;
49
                wren_a          : IN  STD_LOGIC ;
50
                address_a       : IN  STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
51
                data_a          : IN  STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
52
                q_a                     : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0)
53
        );
54
        END COMPONENT;
55
 
56
BEGIN
57
 
58
        altsyncram_component : altsyncram
59
        GENERIC MAP (
60
                clock_enable_input_a    => "BYPASS",
61
                clock_enable_output_a   => "BYPASS",
62
                init_file                               => INIT_FILE,
63
                intended_device_family  => "Cyclone II",
64
                lpm_hint                                => "ENABLE_RUNTIME_MOD=NO",
65
                lpm_type                                => "altsyncram",
66
                numwords_a                              => WORD_COUNT,
67
                operation_mode                  => "SINGLE_PORT",
68
                outdata_aclr_a                  => "NONE",
69
                outdata_reg_a                   => REG_OUT,
70
                power_up_uninitialized  => "FALSE",
71
                widthad_a                               => ADDR_WIDTH,
72
                width_a                                 => DATA_WIDTH,
73
                width_byteena_a                 => 1
74
        )
75
        PORT MAP (
76
                wren_a          => wren,
77
                clock0          => clk,
78
                address_a       => addr,
79
                data_a          => data_in,
80
                q_a             => data_out
81
        );
82
 
83
END SYN;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.