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[/] [System09/] [trunk/] [rtl/] [Cyclone2/] [ram_2k.vhd] - Blame information for rev 166

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Line No. Rev Author Line
1 116 dilbert57
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ram_2k is
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    Port (
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       clk      : in  std_logic;
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       rst      : in  std_logic;
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       cs       : in  std_logic;
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       rw       : in  std_logic;
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       addr     : in  std_logic_vector (10 downto 0);
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       data_in  : in  std_logic_vector (7 downto 0);
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       data_out : out std_logic_vector (7 downto 0)
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    );
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end ram_2k;
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architecture SYN of ram_2k is
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signal we       : std_logic;
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begin
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        we <= cs and (not rw) and (not rst);
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        ram_inst : entity work.spram
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                generic map
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                (
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                        INIT_FILE => "char_rom.mif",
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                        WORD_COUNT => 2048,
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                        ADDR_WIDTH => 11
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                )
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                port map
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                (
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                        clk                     => clk,
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                        addr            => addr,
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                        wren            => we,
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                        data_in         => data_in,
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                        data_out        => data_out
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                );
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end SYN;

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