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[/] [System09/] [trunk/] [rtl/] [Cyclone2/] [spram.vhd] - Blame information for rev 176

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Line No. Rev Author Line
1 116 dilbert57
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY spram IS
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        GENERIC
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        (
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                INIT_FILE               : string        := "";
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                WORD_COUNT              : natural       := 2048;
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                ADDR_WIDTH              : natural       := 11;
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                DATA_WIDTH              : natural       := 8;
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                REG_OUT                 : string        := "UNREGISTERED"
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        );
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        PORT
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        (
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                clk                             : IN  STD_LOGIC ;
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                addr                    : IN  STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
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                wren                    : IN  STD_LOGIC ;
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                data_in                 : IN  STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
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                data_out                : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0)
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        );
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END spram;
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ARCHITECTURE SYN OF spram IS
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        COMPONENT altsyncram
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        GENERIC (
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                clock_enable_input_a    : STRING;
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                clock_enable_output_a   : STRING;
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                init_file                               : STRING;
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                intended_device_family  : STRING;
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                lpm_hint                                : STRING;
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                lpm_type                                : STRING;
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                numwords_a                              : NATURAL;
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                operation_mode                  : STRING;
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                outdata_aclr_a                  : STRING;
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                outdata_reg_a                   : STRING;
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                power_up_uninitialized  : STRING;
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                widthad_a                               : NATURAL;
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                width_a                                 : NATURAL;
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                width_byteena_a                 : NATURAL
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        );
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        PORT (
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                clock0          : IN  STD_LOGIC ;
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                wren_a          : IN  STD_LOGIC ;
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                address_a       : IN  STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
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                data_a          : IN  STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
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                q_a                     : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0)
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        );
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        END COMPONENT;
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BEGIN
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        altsyncram_component : altsyncram
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        GENERIC MAP (
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                clock_enable_input_a    => "BYPASS",
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                clock_enable_output_a   => "BYPASS",
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                init_file                               => INIT_FILE,
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                intended_device_family  => "Cyclone II",
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                lpm_hint                                => "ENABLE_RUNTIME_MOD=NO",
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                lpm_type                                => "altsyncram",
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                numwords_a                              => WORD_COUNT,
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                operation_mode                  => "SINGLE_PORT",
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                outdata_aclr_a                  => "NONE",
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                outdata_reg_a                   => REG_OUT,
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                power_up_uninitialized  => "FALSE",
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                widthad_a                               => ADDR_WIDTH,
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                width_a                                 => DATA_WIDTH,
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                width_byteena_a                 => 1
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        )
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        PORT MAP (
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                wren_a          => wren,
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                clock0          => clk,
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                address_a       => addr,
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                data_a          => data_in,
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                q_a             => data_out
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        );
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END SYN;

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