OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Cyclone2/] [sprom.vhd] - Blame information for rev 207

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 116 dilbert57
LIBRARY ieee;
2
USE ieee.std_logic_1164.all;
3
 
4
LIBRARY altera_mf;
5
USE altera_mf.all;
6
 
7
ENTITY sprom IS
8
        GENERIC
9
        (
10
                INIT_FILE               : string        := "";
11
                WORD_COUNT              : natural       := 2048;
12
                ADDR_WIDTH              : natural       := 11;
13
                DATA_WIDTH              : natural       := 8;
14
                REG_OUT                 : string        := "UNREGISTERED"
15
        );
16
        PORT
17
        (
18
                clk                             : IN  STD_LOGIC ;
19
                addr                    : IN  STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
20
                data_in                 : IN  STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
21
                data_out                : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0)
22
        );
23
END sprom;
24
 
25
ARCHITECTURE SYN OF sprom IS
26
 
27
        COMPONENT altsyncram
28
        GENERIC (
29
                clock_enable_input_a    : STRING;
30
                clock_enable_output_a   : STRING;
31
                init_file                               : STRING;
32
                intended_device_family  : STRING;
33
                lpm_hint                                : STRING;
34
                lpm_type                                : STRING;
35
                numwords_a                              : NATURAL;
36
                operation_mode                  : STRING;
37
                outdata_aclr_a                  : STRING;
38
                outdata_reg_a                   : STRING;
39
                power_up_uninitialized  : STRING;
40
                widthad_a                               : NATURAL;
41
                width_a                                 : NATURAL;
42
                width_byteena_a                 : NATURAL
43
        );
44
        PORT (
45
                clock0          : IN  STD_LOGIC ;
46
                wren_a          : IN  STD_LOGIC ;
47
                address_a       : IN  STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
48
                data_a          : IN  STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
49
                q_a                     : OUT STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0)
50
        );
51
        END COMPONENT;
52
 
53
BEGIN
54
 
55
        altsyncram_component : altsyncram
56
        GENERIC MAP (
57
                clock_enable_input_a    => "BYPASS",
58
                clock_enable_output_a   => "BYPASS",
59
                init_file                               => INIT_FILE,
60
                intended_device_family  => "Cyclone II",
61
                lpm_hint                                => "ENABLE_RUNTIME_MOD=NO",
62
                lpm_type                                => "altsyncram",
63
                numwords_a                              => WORD_COUNT,
64
                operation_mode                  => "ROM",
65
                outdata_aclr_a                  => "NONE",
66
                outdata_reg_a                   => REG_OUT,
67
                power_up_uninitialized  => "FALSE",
68
                widthad_a                               => ADDR_WIDTH,
69
                width_a                                 => DATA_WIDTH,
70
                width_byteena_a                 => 1
71
        )
72
        PORT MAP (
73
                clock0          => clk,
74
                address_a       => addr,
75
                data_a          => data_in,
76
                q_a             => data_out
77
        );
78
 
79
END SYN;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.