OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Cyclone2/] [wb_lpm_ram.vhd] - Blame information for rev 120

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 116 dilbert57
--===========================================================================--
2
--
3
--  S Y N T H E Z I A B L E    Altera LPM_RAM / WISHBONE interface
4
--
5
--  www.OpenCores.Org - August 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : wb_lpm_ram.vhd
9
--
10
-- Purpose        : Implements a WISHBONE compatble interface
11
--                  for the Altera LPM_ROM
12
--
13
-- Dependencies   : ieee.Std_Logic_1164
14
--                  ieee.std_logic_unsigned
15
--                                                                      work.lpm_components (Altera's 220PACK.vhd)
16
--
17
-- Author         : Michael L. Hasenfratz Sr.
18
--
19
--===========================================================================----
20
--
21
-- Revision History:
22
--
23
-- Date:          Revision         Author
24
--===========================================================================--
25
-- 4 Aug 2003     0.1              Michael L. Hasenfratz Sr.
26
--      Created
27
-- 5 Aug 2003     0.2              Michael L. Hasenfratz Sr.
28
--      Added Cache check
29
--
30
 
31
library ieee;
32
use ieee.std_logic_1164.all;
33
use ieee.std_logic_unsigned.all;
34
 
35
library lpm;
36
use lpm.lpm_components.all;
37
 
38
entity wb_lpm_ram is
39
        generic (
40
                LPM_WIDTH       :               positive        range 1 to 64 := 8;                             -- data bits WIDE
41
                LPM_WIDTHAD :   positive        range 1 to 32   := 8                            -- address bits;
42
        );
43
        port (
44
          DAT_I :      in  std_logic_vector(LPM_WIDTH-1 downto 0);
45
          DAT_O :      out std_logic_vector(LPM_WIDTH-1 downto 0);
46
                ADR_I :      in  std_logic_vector(LPM_WIDTHAD-1 downto 0);
47
                SEL_I :      in  std_logic_vector((LPM_WIDTH/8)-1 downto 0);
48
                WE_I :       in  std_logic;
49
                STB_I :      in  std_logic;             -- VMA (Valid Memory Access)
50
                CYC_I :      in  std_logic;             -- CYC in progress
51
                ACK_O :      out std_logic;             -- Data ready
52
                CLK_I :      in  std_logic;             -- System Clock
53
                RST_I :      in  std_logic              -- Reset
54
        );
55
end;
56
 
57
architecture bhv_wb_lpm_ram of wb_lpm_ram is
58
 
59
        signal  iwe :                           std_logic_vector(SEL_I'RANGE);  -- Internal Write Enables
60
        signal  iack :                  std_logic;              -- Internal ACK
61
        signal  sel :                           std_logic;              -- device selected
62
 
63
begin
64
 
65
---------------------------------------------------------
66
--      Instantiate the RAM interface
67
---------------------------------------------------------
68
gen : for idx in SEL_I'RANGE generate
69
ram :   LPM_RAM_DQ
70
                generic map (
71
                        LPM_WIDTH               => 8,
72
                        LPM_WIDTHAD     => LPM_WIDTHAD,
73
      USE_EAB  => "ON",
74
            LPM_OUTDATA => "UNREGISTERED"
75
                )
76
                port map (
77
                  DATA          => DAT_I((idx*8)+7 downto (idx*8)),
78
                  Q                             => DAT_O((idx*8)+7 downto (idx*8)),
79
                  WE      => iwe(idx),
80
                        ADDRESS => ADR_I,
81
                        INCLOCK => CLK_I
82
                );
83
        end generate;
84
 
85
---------------------------------------------------------
86
--      Interconnections
87
---------------------------------------------------------
88
        ACK_O   <= (iack or WE_I) and sel;
89
 
90
-- find SEL_(x)
91
selx : process(SEL_I, CYC_I, STB_I, WE_I)
92
        variable        isel :  std_logic ;
93
        begin
94
                isel    := '0';
95
                for ndx in SEL_I'RANGE loop
96
                        isel                    := isel or SEL_I(ndx);
97
                        iwe(ndx)        <= SEL_I(ndx) and WE_I;
98
                end loop;
99
                sel             <= isel and CYC_I and STB_I;
100
        end process;
101
 
102
--      ACK / HOLD
103
intc0 : process(CLK_I)
104
        begin
105
                if CLK_I'EVENT and CLK_I = '1' then
106
                        if RST_I = '1' then
107
                                iack            <= '0';
108
                        else
109
                                iack            <= sel and not(iack);
110
                        end if;
111
                end if;
112
        end process;
113
 
114
end bhv_wb_lpm_ram;
115
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.