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[/] [System09/] [trunk/] [rtl/] [Cyclone2/] [wb_lpm_rom.vhd] - Blame information for rev 145

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Line No. Rev Author Line
1 116 dilbert57
--===========================================================================--
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--
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--  S Y N T H E Z I A B L E    Altera LPM_ROM / WISHBONE interface
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--
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--  www.OpenCores.Org - August 2003
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--  This core adheres to the GNU public license  
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--
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-- File name      : wb_lpm_rom.vhd
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--
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-- Purpose        : Implements a WISHBONE compatble interface
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--                  for the Altera LPM_ROM
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--                                                                      work.lpm_components (Altera's 220PACK.vhd)
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--
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-- Author         : Michael L. Hasenfratz Sr.
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--
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--===========================================================================----
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--
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-- Revision History:
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--
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-- Date:          Revision         Author
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--===========================================================================--
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-- 1 Aug 2003       0.1              Michael L. Hasenfratz Sr.
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--      Created
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library lpm;
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use     lpm.lpm_components.all;
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entity wb_lpm_rom is
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        generic (
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                LPM_WIDTH       :               positive        range 1 to 64 := 8;                             -- data bits WIDE
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                LPM_WIDTHAD :   positive        range 1 to 32   := 8;                           -- address bits;
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                LPM_FILE :              string  := "my_rom"                                                                     -- ROM Data File
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        );
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        port (
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          DAT_O :      out std_logic_vector(LPM_WIDTH-1 downto 0);
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                ADR_I :      in  std_logic_vector(LPM_WIDTHAD-1 downto 0);
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                SEL_I :      in  std_logic_vector((LPM_WIDTH/8)-1 downto 0);
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                STB_I :      in  std_logic;             -- VMA (Valid Memory Access)
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                CYC_I :      in  std_logic;             -- CYC in progress
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                ACK_O :      out std_logic;             -- Data ready
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                CLK_I :      in  std_logic;             -- System Clock
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                RST_I :      in  std_logic              -- Reset
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        );
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end;
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architecture bhv_wb_lpm_rom of wb_lpm_rom is
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        signal  iack :                  std_logic;              -- Internal ACK
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        signal  isel :                  std_logic;              -- device selected
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begin
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---------------------------------------------------------
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--      Instantiate the ROM interface
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---------------------------------------------------------
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rom0 : LPM_ROM
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        generic map (
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                LPM_WIDTH                                                               => LPM_WIDTH,
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                LPM_WIDTHAD                                                     => LPM_WIDTHAD,
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    LPM_OUTDATA                                                 => "UNREGISTERED",
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                LPM_FILE                                                                => LPM_FILE
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        )
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        port map (
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          Q                             => DAT_O,
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                ADDRESS => ADR_I,
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                INCLOCK => CLK_I
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        );
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---------------------------------------------------------
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--      Interconnections
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---------------------------------------------------------
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        ACK_O   <= isel and iack;
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-- Selection
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romsel : process(SEL_I, CYC_I, STB_I)
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        variable        vsel :  std_logic;
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        begin
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                vsel    := '0';
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                for ndx in SEL_I'RANGE loop
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                        vsel                    := vsel or SEL_I(ndx);
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                end loop;
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                isel            <= vsel and CYC_I and STB_I;
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        end process;
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-- Read Acknowledge
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rdack : process(RST_I, CLK_I)
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        begin
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                if CLK_I'EVENT and CLK_I = '1' then
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                        if RST_I = '1' then
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                                iack            <= '0';
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                        elsif iack = '1' then
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                                iack    <= '0';
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                        else
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                                iack    <= isel;
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                        end if;
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                end if;
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        end process;
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end bhv_wb_lpm_rom;
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