OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Spartan2/] [noice09_rom2k_b4.vhd] - Blame information for rev 66

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57 
--*******************************************************
2 
--
3 
-- NOICE09 Monitor ROM for the 6809
4 
-- noice09_rom2k_b4.vhd
5 
-- John Kent
6 
-- 4th July 2006
7 
--
8 
--*******************************************************
9 
--
10 
-- Using 4 x RAMB4_S8 found in the XC2S300e
11 
-- NOICE09 assumes an ACIA at $E000
12 
-- and Monitor RAM from $F000 to $F7FF
13 
-- The monitor starts at $FC00
14 
-- The first 1K of ROM is empty and may
15 
-- be used for other purposes
16 
--
17 
-- The Noice monitor has the same entity name
18 
-- as SBUG and KBUG9S so it can be easily exchanged.
19 
--
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
library unisim;
24 
        use unisim.all;
25 
 
26 
entity mon_rom is
27 
    Port (
28 
       clk   : in  std_logic;
29 
       rst   : in  std_logic;
30 
       cs    : in  std_logic;
31 
       rw    : in  std_logic;
32 
       addr  : in  std_logic_vector (10 downto 0);
33 
       wdata : in  std_logic_vector (7 downto 0);
34 
       rdata : out std_logic_vector (7 downto 0)
35 
    );
36 
end mon_rom;
37 
 
38 
architecture rtl of mon_rom is
39 
 
40 
   signal rdata0 : std_logic_vector (7 downto 0);
41 
   signal rdata1 : std_logic_vector (7 downto 0);
42 
   signal rdata2 : std_logic_vector (7 downto 0);
43 
   signal rdata3 : std_logic_vector (7 downto 0);
44 
 
45 
   signal ena0 : std_logic;
46 
   signal ena1 : std_logic;
47 
   signal ena2 : std_logic;
48 
   signal ena3 : std_logic;
49 
 
50 
   signal we : std_logic;
51 
 
52 
   component RAMB4_S8
53 
    generic (
54 
      INIT_00, INIT_01, INIT_02, INIT_03,
55 
           INIT_04, INIT_05, INIT_06, INIT_07,
56 
           INIT_08, INIT_09, INIT_0A, INIT_0B,
57 
      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
58 
    );
59 
 
60 
    port (
61 
      clk, we, en, rst : in std_logic;
62 
      addr : in std_logic_vector(8 downto 0);
63 
      di : in std_logic_vector(7 downto 0);
64 
      do : out std_logic_vector(7 downto 0)
65 
    );
66 
  end component RAMB4_S8;
67 
 
68 
begin
69 
 
70 
  ROM0 : RAMB4_S8
71 
    generic map (
72 
    INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
73 
    INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
74 
    INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
75 
    INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
76 
    INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
77 
    INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
78 
    INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
79 
    INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
80 
    INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
81 
    INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
82 
    INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
83 
    INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
84 
    INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
85 
    INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
86 
    INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
87 
    INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
88 
    )
89 
 
90 
    port map ( clk => clk,
91 
                    en => ena0,
92 
                                   we => we,
93 
                                   rst => rst,
94 
                                   addr(8 downto 0) => addr(8 downto 0),
95 
               di(7 downto 0)   => wdata,
96 
                                   do(7 downto 0)   => rdata0(7 downto 0)
97 
        );
98 
 
99 
  ROM1 : RAMB4_S8
100 
    generic map (
101 
    INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
102 
    INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
103 
    INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
104 
    INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
105 
    INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
106 
    INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
107 
    INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
108 
    INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
109 
    INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
110 
    INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
111 
    INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
112 
    INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
113 
    INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
114 
    INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
115 
    INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
116 
    INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
117 
    )
118 
 
119 
    port map ( clk => clk,
120 
                    en => ena1,
121 
                                   we => we,
122 
                                   rst => rst,
123 
                                   addr(8 downto 0) => addr(8 downto 0),
124 
               di(7 downto 0)   => wdata,
125 
                                   do(7 downto 0)   => rdata1(7 downto 0)
126 
        );
127 
 
128 
  ROM2 : RAMB4_S8
129 
    generic map (
130 
    INIT_00 => x"ACFC8E1001E07D00E0B7118600E0B70386FA2612121F3000008E20F6CE10321A",
131 
    INIT_01 => x"2AF6B72BF6B72EF6FD0000CC22F6F723F6B710F6CCFA265A81AF1008C600F08E",
132 
    INIT_02 => x"34D1FD7E30F6B7FA862DF6B7828621F6B720F6B724F6FD26F6FD28F6FD2CF6B7",
133 
    INIT_03 => x"FCBD02349035011A903501E0B64FF227018400E0B60D271F308EFCBD00008E10",
134 
    INIT_04 => x"6D20393038363F0100000000008005394C4F3901E0B70235F627028400E0B68E",
135 
    INIT_05 => x"02352AF6B702352BF6B702352DF6B7023520F6B700302E315620726F74696E6F",
136 
    INIT_06 => x"20F6B6103524F6F725F6B7063526F6F727F6B7063528F6F729F6B706352CF6B7",
137 
    INIT_07 => x"25F781F4255FFCBD30F68E20F6CE1037FE7E2EF6F72FF6B7101F1F3002260181",
138 
    INIT_08 => x"FCBDF6265A80A7D8255FFCBD891F0C27008180A7E5228081E9255FFCBD80A7F0",
139 
    INIT_09 => x"812527FD812627FE814227FF8180E680A630F68EC526E0ABB4FEBD0234CE255F",
140 
    INIT_0a => x"FE7E018630F6B7F0861F27F7812027F8812127F9812227FA812327FB812427FC",
141 
    INIT_0b => x"31F68E1091FC8E84FE7E79FE7E4BFE7EF8FD7EE6FD7ED1FD7EA5FD7E8EFD7E92",
142 
    INIT_0c => x"5A80A7A0A6072731F6F703E6021F01E602A69CFE7EF9265AA0A780A6A0E71BC6",
143 
    INIT_0d => x"A63435F9265AA0A780A63434142703C031F6F6021F80A680E680A69CFE7EF926",
144 
    INIT_0e => x"80A7A0A680E731F68E10C620F68E1092FE7E018602200086F7265A0726A0A180",
145 
    INIT_0f => x"041F22F6F623F6B692FE7E4FF9265AA0A780A620F68E100B275D9CFE7EF9265A"
146 
    )
147 
    port map ( clk => clk,
148 
                    en => ena2,
149 
                                   we => we,
150 
                                   rst => rst,
151 
                                   addr(8 downto 0) => addr(8 downto 0),
152 
               di(7 downto 0)   => wdata,
153 
                                   do(7 downto 0)   => rdata2(7 downto 0)
154 
        );
155 
 
156 
  ROM3 : RAMB4_S8
157 
    generic map (
158 
    INIT_00 => x"063428F6F629F6B6063426F6F627F6B6063424F6F625F6B606342EF6F62FF6B6",
159 
    INIT_01 => x"1022F6F723F6B7401F3B0234508A2DF6B602342BF6B602342AF6B602342CF6B6",
160 
    INIT_02 => x"A4A6021F01E602A6043420275454C0A7008631F6CED1FD7E21F6B7008620F6CE",
161 
    INIT_03 => x"A6021F84E601A69CFE7EE02631F6F1043031F67CC0A70C260435A4E1A4E703E6",
162 
    INIT_04 => x"40B4FEBD002031F6B7018632F6B792FE7E4FA4A702A6021F84E601A692FE7EA4",
163 
    INIT_05 => x"5A80AB008602CB01E630F68EF1FC7EF8265A7CFCBD80A603CB01E630F68E84A7",
164 
    INIT_06 => x"26508502352BF6B7846E04F0BE0586846E02F0BE0686846E00F0BE078639FB26",
165 
    INIT_07 => x"6E0CF0BE0286846E08F0BE0386846E06F0BE04860234508A04342BF6F67C3409",
166 
    INIT_08 => x"0000000000000000000000000000000000000000000000000000ACFC7E018684",
167 
    INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
168 
    INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
169 
    INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
170 
    INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
171 
    INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
172 
    INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
173 
    INIT_0f => x"00FCFAFE01FFF3FED8FED1FECAFEC3FE00000000000000000000000000000000"
174 
    )
175 
    port map ( clk => clk,
176 
                    en => ena3,
177 
                                   we => we,
178 
                                   rst => rst,
179 
                                   addr(8 downto 0) => addr(8 downto 0),
180 
               di(7 downto 0)   => wdata,
181 
                                   do(7 downto 0)   => rdata3(7 downto 0)
182 
        );
183 
 
184 
my_noice09_b4 : process ( cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
185 
begin
186 
                   case addr(10 downto 9) is
187 
                        when "00" =>
188 
                           ena0  <= cs;
189 
                                ena1  <= '0';
190 
                                ena2  <= '0';
191 
                                ena3  <= '0';
192 
            rdata <= rdata0;
193 
                        when "01" =>
194 
                           ena0  <= '0';
195 
                                ena1  <= cs;
196 
                                ena2  <= '0';
197 
                                ena3  <= '0';
198 
            rdata <= rdata1;
199 
                        when "10" =>
200 
                           ena0  <= '0';
201 
                                ena1  <= '0';
202 
                                ena2  <= cs;
203 
                                ena3  <= '0';
204 
            rdata <= rdata2;
205 
                        when "11" =>
206 
                           ena0  <= '0';
207 
                                ena1  <= '0';
208 
                                ena2  <= '0';
209 
                                ena3  <= cs;
210 
            rdata <= rdata3;
211 
                        when others =>
212 
                           null;
213 
                        end case;
214 
 
215 
         we <= not rw;
216 
 
217 
end process;
218 
 
219 
end architecture rtl;
220 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.