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[/] [System09/] [trunk/] [rtl/] [Spartan2/] [ram1k_b4.vhd] - Blame information for rev 89

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Line No. Rev Author Line
1 19 dilbert57 
--
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-- Ram1k_b4.vhd
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--
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-- 1K Byte RAM made out of 2 x 512 byte Block RAMs.
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-- John Kent
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-- 3 February 2007
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library unisim;
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        use unisim.vcomponents.all;
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entity ram1k is
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    Port (
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       WB_CLK_I : in  std_logic;
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       WB_RST_I : in  std_logic;
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       WB_ADR_I : in  std_logic_vector (9 downto 0);
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       WB_DAT_O : out std_logic_vector (7 downto 0)
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       WB_DAT_I : in  std_logic_vector (7 downto 0);
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       WB_WE_I  : in  std_logic;
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       WB_STB_I : in  std_logic;
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    );
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end ram1k;
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architecture rtl of ram_2k is
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   signal rdata0   : std_logic_vector (7 downto 0);
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   signal rdata1   : std_logic_vector (7 downto 0);
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   signal ena0     : std_logic;
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   signal ena1     : std_logic;
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   component RAMB4_S8
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    generic (
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      INIT_00, INIT_01, INIT_02, INIT_03,
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      INIT_04, INIT_05, INIT_06, INIT_07,
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      INIT_08, INIT_09, INIT_0A, INIT_0B,
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      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
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    );
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    port (
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      clk, we, en, rst : in std_logic;
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      addr :  in std_logic_vector(8 downto 0);
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      di   :  in std_logic_vector(7 downto 0);
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      do   : out std_logic_vector(7 downto 0)
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    );
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  end component;
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begin
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  MY_RAM0 : RAMB4_S8
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    generic map (
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INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"    )
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    port map (
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        clk => WB_CLK_I,
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        en  => ena0,
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        we  => WB_WE_I,
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        rst => WB_RST_I,
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        addr(8 downto 0) => WB_ADR_I(8 downto 0),
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        di(7 downto 0)   => WB_DAT_I(7 downto 0),
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        do(7 downto 0)   => rdata0(7 downto 0)
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        );
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  MY_RAM1 : RAMB4_S8
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    generic map (
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INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000"    )
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    port map ( clk => clk,
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        clk => WB_CLK_I,
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        en  => ena1,
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        we  => WB_WE_I,
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        rst => WB_RST_I,
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        addr(8 downto 0) => WB_ADR_I(8 downto 0),
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        di(7 downto 0)   => WB_DAT_I(7 downto 0),
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        do(7 downto 0)   => rdata1(7 downto 0)
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        );
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my_ram_1k : process (WB_STB_I, WB_ADR_I, rdata0, rdata1 )
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begin
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        case WB_ADR_I(9) is
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        when "0" =>
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                ena0     <= WB_STB_I;
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                ena1     <= '0';
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                WB_DAT_O <= rdata0;
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        when "1" =>
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                ena0     <= '0';
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                ena1     <= WB_STB_I;
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                WB_DAT_O <= rdata1;
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        when others =>
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                null;
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        end case;
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end process;
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end;
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