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[/] [System09/] [trunk/] [rtl/] [Spartan2/] [ram2k_b4.vhd] - Blame information for rev 117

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Line No. Rev Author Line
1 99 davidgb
--===========================================================================--
2
--                                                                           --
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--       2K Byte RAM Block using 4KBit Block RAMs found in the Spartan 2     --
4
--                                                                           --
5
--===========================================================================--
6
--
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-- File name      : ram2k_b4.vhd
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--
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-- Entity name    : ram_2k
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--
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-- Purpose        : 2KB RAM block used for a character text buffer for vdu8 
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--                  using 4 x 4KBit Block RAMs
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_arith
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--                  ieee.std_logic_unsigned
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--                  unisim.vcomponents
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-- 
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-- Author         : John E. Kent      
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--                  dilbert57@opencores.org
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--
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--
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--  Copyright (C) 2004 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                             Revision History:                             --
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--===========================================================================--
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--
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-- Version Date       Author      Comments
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--
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-- 0.1     2004-02-11 John Kent   Initial Version
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-- 0.2     2010-08-27 John Kent   Added header
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--                                Changed data input & output signals
47 19 dilbert57
--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library unisim;
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        use unisim.all;
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55
entity ram_2k is
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    Port (
57 99 davidgb
       clk      : in  std_logic;
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       rst      : in  std_logic;
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       cs       : in  std_logic;
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       rw       : in  std_logic;
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       addr     : in  std_logic_vector (10 downto 0);
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       data_in  : in  std_logic_vector (7 downto 0);
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       data_out : out std_logic_vector (7 downto 0)
64 19 dilbert57
    );
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end ram_2k;
66
 
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architecture rtl of ram_2k is
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69 99 davidgb
   signal we        : std_logic;
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   signal data_out0 : std_logic_vector (7 downto 0);
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   signal data_out1 : std_logic_vector (7 downto 0);
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   signal data_out2 : std_logic_vector (7 downto 0);
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   signal data_out3 : std_logic_vector (7 downto 0);
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   signal ena0      : std_logic;
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   signal ena1      : std_logic;
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   signal ena2      : std_logic;
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   signal ena3      : std_logic;
78 19 dilbert57
 
79
   component RAMB4_S8
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    generic (
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      INIT_00, INIT_01, INIT_02, INIT_03,
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      INIT_04, INIT_05, INIT_06, INIT_07,
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      INIT_08, INIT_09, INIT_0A, INIT_0B,
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      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
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      x"0000000000000000000000000000000000000000000000000000000000000000"
86
    );
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88
    port (
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      clk, we, en, rst : in std_logic;
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      addr :  in std_logic_vector(8 downto 0);
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      di   :  in std_logic_vector(7 downto 0);
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      do   : out std_logic_vector(7 downto 0)
93
    );
94
  end component;
95
 
96
begin
97
 
98
  MY_RAM0 : RAMB4_S8
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    generic map (
100
INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
101
INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
102
INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
103
INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
104
INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
105
INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
106
INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
107
INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
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INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
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INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
110
INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
111
INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
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INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
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INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
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INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
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INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
116
    )
117
 
118
    port map ( clk => clk,
119
                    en  => ena0,
120
                                   we  => we,
121 99 davidgb
                                   rst => rst,
122 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
123 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
124
                                   do(7 downto 0)   => data_out0(7 downto 0)
125 19 dilbert57
        );
126
 
127
  MY_RAM1 : RAMB4_S8
128
    generic map (
129
 
130
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
131
INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
132
INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
133
INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
134
INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
135
INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
136
INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
137
INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
138
INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
139
INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
140
INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
141
INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
142
INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
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INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
144
INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
145
INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
146
    )
147
 
148
    port map ( clk => clk,
149
                    en  => ena1,
150
                                   we  => we,
151 99 davidgb
                                   rst => rst,
152 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
153 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
154
                                   do(7 downto 0)   => data_out1(7 downto 0)
155 19 dilbert57
        );
156
 
157
  MY_RAM2 : RAMB4_S8
158
    generic map (
159
INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
160
INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
161
INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
162
INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
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INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
164
INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
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INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
166
INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
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INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
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INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
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INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
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INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
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INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
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INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
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INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
174
INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
175
    )
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177
    port map ( clk => clk,
178
                    en  => ena2,
179
                                   we  => we,
180 99 davidgb
                                   rst => rst,
181 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
182 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
183
                                   do(7 downto 0)   => data_out2(7 downto 0)
184 19 dilbert57
        );
185
 
186
  MY_RAM3 : RAMB4_S8
187
    generic map (
188
 
189
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
190
INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
191
INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
192
INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
193
INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
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INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
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INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
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INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
197
INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
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INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
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INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
200
INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
201
INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
202
INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
203
INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
204
INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
205
    )
206
 
207
    port map ( clk => clk,
208
                    en  => ena3,
209
                                   we  => we,
210 99 davidgb
                                   rst => rst,
211 19 dilbert57
                                   addr(8 downto 0) => addr(8 downto 0),
212 99 davidgb
               di(7 downto 0)   => data_in(7 downto 0),
213
                                   do(7 downto 0)   => data_out3(7 downto 0)
214 19 dilbert57
        );
215
 
216 99 davidgb
my_ram_2k : process ( cs, rw, addr, data_out0, data_out1, data_out2, data_out3 )
217 19 dilbert57
begin
218 99 davidgb
    ena0 <= '0';
219
         ena1 <= '0';
220
    ena2 <= '0';
221
         ena3 <= '0';
222 19 dilbert57
         case addr(10 downto 9) is
223
         when "00" =>
224 99 davidgb
      ena0     <= cs;
225
                data_out <= data_out0;
226 19 dilbert57
         when "01" =>
227 99 davidgb
           ena1     <= cs;
228
                data_out <= data_out1;
229 19 dilbert57
         when "10" =>
230 99 davidgb
      ena2     <= cs;
231
                data_out <= data_out2;
232 19 dilbert57
         when "11" =>
233 99 davidgb
           ena3     <= cs;
234
                data_out <= data_out3;
235 19 dilbert57
         when others =>
236
      null;
237
         end case;
238
 
239 99 davidgb
         we <= not rw;
240 19 dilbert57
 
241
end process;
242
 
243
end;
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