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[/] [System09/] [trunk/] [rtl/] [Spartan2/] [ram2k_b4.vhd] - Blame information for rev 71

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Line No. Rev Author Line
1 19 dilbert57
--
2
-- Ram2k.vhd
3
--
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-- 2K Byte RAM made out of 4 x 512 byte Block RAMs.
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-- John Kent
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-- 11 February 2004
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library unisim;
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        use unisim.all;
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entity ram_2k is
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    Port (
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       clk   : in  std_logic;
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       rst   : in  std_logic;
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       cs    : in  std_logic;
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       rw    : in  std_logic;
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       addr  : in  std_logic_vector (10 downto 0);
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       wdata : in  std_logic_vector (7 downto 0);
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       rdata : out std_logic_vector (7 downto 0)
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    );
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end ram_2k;
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architecture rtl of ram_2k is
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   signal we       : std_logic;
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   signal reset    : std_logic;
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   signal rdata0   : std_logic_vector (7 downto 0);
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   signal rdata1   : std_logic_vector (7 downto 0);
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   signal rdata2   : std_logic_vector (7 downto 0);
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   signal rdata3   : std_logic_vector (7 downto 0);
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   signal ena0     : std_logic;
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   signal ena1     : std_logic;
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   signal ena2     : std_logic;
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   signal ena3     : std_logic;
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   component RAMB4_S8
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    generic (
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      INIT_00, INIT_01, INIT_02, INIT_03,
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      INIT_04, INIT_05, INIT_06, INIT_07,
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      INIT_08, INIT_09, INIT_0A, INIT_0B,
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      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
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      x"0000000000000000000000000000000000000000000000000000000000000000"
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    );
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    port (
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      clk, we, en, rst : in std_logic;
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      addr :  in std_logic_vector(8 downto 0);
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      di   :  in std_logic_vector(7 downto 0);
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      do   : out std_logic_vector(7 downto 0)
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    );
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  end component;
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begin
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  MY_RAM0 : RAMB4_S8
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    generic map (
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INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
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INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
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INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
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INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
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INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
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INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
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INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
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INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
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INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
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INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
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INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
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INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
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INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
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INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
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INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
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INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
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    )
78
 
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    port map ( clk => clk,
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                    en  => ena0,
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                                   we  => we,
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                                   rst => reset,
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                                   addr(8 downto 0) => addr(8 downto 0),
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               di(7 downto 0)   => wdata(7 downto 0),
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                                   do(7 downto 0)   => rdata0(7 downto 0)
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        );
87
 
88
  MY_RAM1 : RAMB4_S8
89
    generic map (
90
 
91
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
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INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
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INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
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INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
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INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
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INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
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INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
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INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
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INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
100
INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
101
INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
102
INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
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INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
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INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
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INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
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INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
107
    )
108
 
109
    port map ( clk => clk,
110
                    en  => ena1,
111
                                   we  => we,
112
                                   rst => reset,
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                                   addr(8 downto 0) => addr(8 downto 0),
114
               di(7 downto 0)   => wdata(7 downto 0),
115
                                   do(7 downto 0)   => rdata1(7 downto 0)
116
        );
117
 
118
  MY_RAM2 : RAMB4_S8
119
    generic map (
120
INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
121
INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
122
INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
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INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
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INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
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INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
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INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
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INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
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INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
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INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
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INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
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INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
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INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
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INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
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INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
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INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
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    )
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138
    port map ( clk => clk,
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                    en  => ena2,
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                                   we  => we,
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                                   rst => reset,
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                                   addr(8 downto 0) => addr(8 downto 0),
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               di(7 downto 0)   => wdata(7 downto 0),
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                                   do(7 downto 0)   => rdata2(7 downto 0)
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        );
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147
  MY_RAM3 : RAMB4_S8
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    generic map (
149
 
150
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
151
INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
152
INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
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INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
154
INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
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INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
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INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
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INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
158
INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
159
INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
160
INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
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INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
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INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
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INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
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INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
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INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
166
    )
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168
    port map ( clk => clk,
169
                    en  => ena3,
170
                                   we  => we,
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                                   rst => reset,
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                                   addr(8 downto 0) => addr(8 downto 0),
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               di(7 downto 0)   => wdata(7 downto 0),
174
                                   do(7 downto 0)   => rdata3(7 downto 0)
175
        );
176
 
177
my_ram_2k : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
178
begin
179
         case addr(10 downto 9) is
180
         when "00" =>
181
      ena0 <= cs;
182
           ena1 <= '0';
183
      ena2 <= '0';
184
           ena3 <= '0';
185
                rdata <= rdata0;
186
         when "01" =>
187
      ena0 <= '0';
188
           ena1 <= cs;
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      ena2 <= '0';
190
           ena3 <= '0';
191
                rdata <= rdata1;
192
         when "10" =>
193
      ena0 <= '0';
194
           ena1 <= '0';
195
      ena2 <= cs;
196
           ena3 <= '0';
197
                rdata <= rdata2;
198
         when "11" =>
199
      ena0 <= '0';
200
           ena1 <= '0';
201
      ena2 <= '0';
202
           ena3 <= cs;
203
                rdata <= rdata3;
204
         when others =>
205
      null;
206
         end case;
207
 
208
         we <= cs and (not rw);
209
    reset <= rst;
210
 
211
end process;
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213
end;
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