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[/] [System09/] [trunk/] [rtl/] [Spartan3/] [sys09s3e_b4.vhd] - Blame information for rev 138

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Line No. Rev Author Line
1 126 dilbert57
library IEEE;
2
   use IEEE.std_logic_1164.all;
3
   use IEEE.std_logic_arith.all;
4
library unisim;
5
   use unisim.vcomponents.all;
6
 
7
entity SYS09BUG_F000 is
8
   port(
9
      clk    : in  std_logic;
10
      rst    : in  std_logic;
11
      cs     : in  std_logic;
12
      rw     : in  std_logic;
13
      addr   : in  std_logic_vector(10 downto 0);
14
      rdata  : out std_logic_vector(7 downto 0);
15
      wdata  : in  std_logic_vector(7 downto 0)
16
   );
17
end SYS09BUG_F000;
18
 
19
architecture rtl of SYS09BUG_F000 is
20
 
21
   type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
22
   signal xdata : data_array;
23
   signal en : std_logic_vector(3 downto 0);
24
   signal we : std_logic;
25
 
26
component RAMB4_S8
27
generic (
28
   INIT_00, INIT_01, INIT_02, INIT_03,
29
   INIT_04, INIT_05, INIT_06, INIT_07,
30
   INIT_08, INIT_09, INIT_0A, INIT_0B,
31
   INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
32
    );
33
   port (
34
      clk, we, en, rst : in std_logic;
35
      addr : in std_logic_vector(8 downto 0);
36
      di   : in std_logic_vector(7 downto 0);
37
      do   : out std_logic_vector(7 downto 0)
38
      );
39
     end component RAMB4_S8;
40
 
41
   begin
42
 
43
   ROM00: RAMB4_S8
44
      generic map (
45
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
46
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
47
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
48
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
49
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
50
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
51
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
52
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
53
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
54
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
55
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
56
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
57
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
58
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
59
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
60
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
61
      )
62
      port map (
63
         clk     => clk,
64
         en      => en(0),
65
         we      => we,
66
         rst     => rst,
67
         addr    => addr(8 downto 0),
68
         di      => wdata,
69
         do      => xdata(0)
70
      );
71
 
72
   ROM01: RAMB4_S8
73
      generic map (
74
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
75
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
76
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
77
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
78
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
79
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
80
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
81
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
82
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
83
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
84
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
85
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
86
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
87
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
88
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
89
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
90
      )
91
      port map (
92
         clk     => clk,
93
         en      => en(1),
94
         we      => we,
95
         rst     => rst,
96
         addr    => addr(8 downto 0),
97
         di      => wdata,
98
         do      => xdata(1)
99
      );
100
 
101
   ROM02: RAMB4_S8
102
      generic map (
103
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
104
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
105
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
106
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
107
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
108
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
109
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
110
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
111
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
112
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
113
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
114
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
115
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
116
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
117
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
118
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
119
      )
120
      port map (
121
         clk     => clk,
122
         en      => en(2),
123
         we      => we,
124
         rst     => rst,
125
         addr    => addr(8 downto 0),
126
         di      => wdata,
127
         do      => xdata(2)
128
      );
129
 
130
   ROM03: RAMB4_S8
131
      generic map (
132
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
133
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
134
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
135
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
136
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
137
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
138
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
139
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
140
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
141
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
142
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
143
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
144
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
145
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
146
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
147
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
148
      )
149
      port map (
150
         clk     => clk,
151
         en      => en(3),
152
         we      => we,
153
         rst     => rst,
154
         addr    => addr(8 downto 0),
155
         di      => wdata,
156
         do      => xdata(3)
157
      );
158
 
159
   rom_glue: process (cs, rw, addr, xdata)
160
   begin
161
      en <= (others=>'0');
162
      case addr(10 downto 9) is
163
      when "00" =>
164
         en(0)  <= cs;
165
         rdata  <= xdata(0);
166
      when "01" =>
167
         en(1)  <= cs;
168
         rdata  <= xdata(1);
169
      when "10" =>
170
         en(2)  <= cs;
171
         rdata  <= xdata(2);
172
      when "11" =>
173
         en(3)  <= cs;
174
         rdata  <= xdata(3);
175
      when others =>
176
         null;
177
      end case;
178
      we <= not rw;
179
   end process;
180
end architecture rtl;
181
 
182
library IEEE;
183
   use IEEE.std_logic_1164.all;
184
   use IEEE.std_logic_arith.all;
185
library unisim;
186
   use unisim.vcomponents.all;
187
 
188
entity SYS09BUG_F800 is
189
   port(
190
      clk    : in  std_logic;
191
      rst    : in  std_logic;
192
      cs     : in  std_logic;
193
      rw     : in  std_logic;
194
      addr   : in  std_logic_vector(10 downto 0);
195
      rdata  : out std_logic_vector(7 downto 0);
196
      wdata  : in  std_logic_vector(7 downto 0)
197
   );
198
end SYS09BUG_F800;
199
 
200
architecture rtl of SYS09BUG_F800 is
201
 
202
   type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
203
   signal xdata : data_array;
204
   signal en : std_logic_vector(3 downto 0);
205
   signal we : std_logic;
206
 
207
component RAMB4_S8
208
generic (
209
   INIT_00, INIT_01, INIT_02, INIT_03,
210
   INIT_04, INIT_05, INIT_06, INIT_07,
211
   INIT_08, INIT_09, INIT_0A, INIT_0B,
212
   INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
213
    );
214
   port (
215
      clk, we, en, rst : in std_logic;
216
      addr : in std_logic_vector(8 downto 0);
217
      di   : in std_logic_vector(7 downto 0);
218
      do   : out std_logic_vector(7 downto 0)
219
      );
220
     end component RAMB4_S8;
221
 
222
   begin
223
 
224
   ROM00: RAMB4_S8
225
      generic map (
226
         INIT_00 => x"A780A610C6C07F8E104EFE8ECFFE0DFB11FB82FBBDFCA8FC8AFC90FC4BF814F8",
227
         INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC6450117D07FBF00E08EF9265AA0",
228
         INIT_02 => x"092C2081891FF1270D817F843C0417BC021783FE8EDE01173A03175EFE8E9204",
229
         INIT_03 => x"FE8C02300F2780E118FE8E20C0022F60C14C0417510417408B981F5804175E86",
230
         INIT_04 => x"1F6E02178BFE8E121F2D297403173B341FBC2094ADC020F9021785FE8EF5264E",
231
         INIT_05 => x"17275E81DD271881E127088111286703170C0417AE0317A4A6140417AE031721",
232
         INIT_06 => x"321FAB0217BE203F31C2202131EA03173F86ED03170827A4A1A4A7390F260D81",
233
         INIT_07 => x"F0C4201F0634F0C41000C3101F390124E1AC2034062914031705201F30C07F8E",
234
         INIT_08 => x"10C69B0317370317E4AEF701178BFE8E103439623203279F03170527E4AC011F",
235
         INIT_09 => x"03172E8602237E810425208180A610C6E1AE8B0317F5265A93031735031780A6",
236
         INIT_0a => x"273F8184A60F2710355B8DFFFF8E10341A24C07F8C1E29C00217BC20EE265A7C",
237
         INIT_0b => x"431F39FB265A1E8D08C6D37F8E104B03163F864E03173984A73F86A4AFA0A709",
238
         INIT_0c => x"A60A24C07F8C21AEB3FE16ED7FBF00008E5102170C8D4AAF04272C8D1F304AAE",
239
         INIT_0d => x"265A0427A1ACA0A608C6D37F8E1039A0A7A0A7A0A7FF8684A7A4A604263F8184",
240
         INIT_0e => x"7FBFE7F98EEB7FBFC07FBEED7FBF1429390217EE02171C295F0117393D3139F7",
241
         INIT_0f => x"27ED7FBE24273F8184A64AAEEC011770E0B671E0B73686431F392020450017C0"
242
      )
243
      port map (
244
         clk     => clk,
245
         en      => en(0),
246
         we      => we,
247
         rst     => rst,
248
         addr    => addr(8 downto 0),
249
         di      => wdata,
250
         do      => xdata(0)
251
      );
252
 
253
   ROM01: RAMB4_S8
254
      generic map (
255
         INIT_00 => x"3B71E0B73F8673E0B7368670E0B671E0B7368670E0B70D86341FED7FBF1F301F",
256
         INIT_01 => x"B7368672E0B7008670E0B7FF8673E0B73A8671E0B7328622FE16C07FBFEB7FBE",
257
         INIT_02 => x"81260217D27F7F6402171186D6FCBD8435FD265A20C604343973E0B73E8671E0",
258
         INIT_03 => x"E0EBE0E61034212991011726290234A80117F12631813D2739811F0217F92653",
259
         INIT_04 => x"FFC102355FEB2080A70527E46AE0EB02340C2904358E01170434E46AE46AE4EB",
260
         INIT_05 => x"E4AF0130492562AC4D2930344A0117E26F0E02161386D27F731602173F86BA27",
261
         INIT_06 => x"03CB2F0017CCFE8E64E720C6022320008310062762A3E4ECF501171286D6FCBD",
262
         INIT_07 => x"AF5B0117981F53F526646A65011780A684EB63EB62EB68011762AE750117981F",
263
         INIT_08 => x"00169D011690356900177DFE8E10347120028D396532B301171486C326E4AC62",
264
         INIT_09 => x"8DDC8D728D3948AF0229EB8DE78D618D394AAF0229F68DF28D910017E50016F8",
265
         INIT_0a => x"BB8D6C8D3943A70229C78DC68D498D3944AF0229D58DD18D5E8D3946AF0229E0",
266
         INIT_0b => x"1739C4A7808A0429A68DA58D5F8D3941A70229B18DB08D588D3942A70229BC8D",
267
         INIT_0c => x"8DADFE8EF42048AEEA8D9BFE8EBF0016311FF48D8FFE8E39F726048180A63B01",
268
         INIT_0d => x"204AAEC58D95FE8ED82046AECE8DA1FE8EE12044AED78DA7FE8EB4001643A6E1",
269
         INIT_0e => x"900016C4FE8EC4A6AA8DBDFE8ED02042A6B38DB8FE8ED92041A6BC8DB3FE8ECF",
270
         INIT_0f => x"098DD520CE8DC78DC08D17FF178BFE8EBF8DB88DB08DA98DA18D27FF178BFE8E"
271
      )
272
      port map (
273
         clk     => clk,
274
         en      => en(1),
275
         we      => we,
276
         rst     => rst,
277
         addr    => addr(8 downto 0),
278
         di      => wdata,
279
         do      => xdata(1)
280
      );
281
 
282
   ROM02: RAMB4_S8
283
      generic map (
284
         INIT_00 => x"4848483229118D903561A710343C29088D011F42290E8DB400172D86121F4D29",
285
         INIT_01 => x"22468112254181393080032239811D253081578D39E0AB04342829078D891F48",
286
         INIT_02 => x"4444444402340235028D0235103439021A395780032266810725618139378003",
287
         INIT_03 => x"3B8D3F8D2D860225E46880A608C602344D20078B022F3981308B0F840235048D",
288
         INIT_04 => x"84A620E08E0926018584A6D07FBE10342D207F84048D0627D27F7D8235F1265A",
289
         INIT_05 => x"34498D2086008D8235018520E0B605260185D07F9FA60234903501A6EE270185",
290
         INIT_06 => x"A7518684A70386D07FBE138D903501A70235F6260885FA27028584A6D07FBE12",
291
         INIT_07 => x"7F01E702C6F17FFD04E703E702A7EF7FFD0000CC30E08E39D27FB7FF86016D84",
292
         INIT_08 => x"84A70520098D042420810D20608D0427F27F7D30E08E16345986028D1B86F27F",
293
         INIT_09 => x"270C81890027100D81382716817C0027101A815A271B81342708819635AF0017",
294
         INIT_0a => x"EF7FB66D205A34275DEF7FFC8F0016792619C15CEF7FFC45260A810F270B8124",
295
         INIT_0b => x"816E27598114273DC1F27FF656200000CC5820212750814CEF7FB662204A2C27",
296
         INIT_0c => x"224F812080F27F7F39F17FB70426F17F7D39F27F7F39F27FB704263D81312754",
297
         INIT_0d => x"508102A74C84E720C6EF7FB6168D0000CC1B20E12218C120C0F17F7FF17FF6ED",
298
         INIT_0e => x"EA2619C15C4FF02650814CEF7FFC3903E702A7EF7FFDF07FF64F39F27F7FF726",
299
         INIT_0f => x"7FF6F42650C15C84A702E7EF7FF72086EF7FF604E75F012519C15C04E6E78D5A"
300
      )
301
      port map (
302
         clk     => clk,
303
         en      => en(2),
304
         we      => we,
305
         rst     => rst,
306
         addr    => addr(8 downto 0),
307
         di      => wdata,
308
         do      => xdata(2)
309
      );
310
 
311
   ROM03: RAMB4_S8
312
      generic map (
313
         INIT_00 => x"FB035CFB0267FB0139F27FF702E7EF7FF75FE4205F03E7F07FF7082719C15CF0",
314
         INIT_01 => x"4DAFFA5051FA4C8FF847E7F84546F9423BFB1946FB1830FB1524FB1051FB0472",
315
         INIT_02 => x"0A0DFFFFFFFF7EF991F891F891F891F87EF9C5F95472F958DBF853E0FB5292F8",
316
         INIT_03 => x"000A0D4B04202D202045335320524F4620362E31204755423930535953000000",
317
         INIT_04 => x"3D53552020043D43502020043D5053202004202D20043F54414857043E040000",
318
         INIT_05 => x"432020043D422020043D412020043D50442020043D58492020043D5949202004",
319
         INIT_06 => x"C07F9F6E38F916D27FF7535FC07FCE103904315343565A4E4948464504203A43",
320
         INIT_07 => x"FF8CCC7FBE49584F4AAF80E64AAE431FCA7F9F6EC87F9F6EC67F9F6EC47F9F6E",
321
         INIT_08 => x"000000000000C27F9F6E42EE1F37F16E44AEC4EC10340822CE7FBC8B300F27FF",
322
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
323
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
324
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
325
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
326
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
327
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
328
         INIT_0f => x"D0FEDCFEECFEE8FEE4FEE0FEF0FEDCFE00000000000000000000000000000000"
329
      )
330
      port map (
331
         clk     => clk,
332
         en      => en(3),
333
         we      => we,
334
         rst     => rst,
335
         addr    => addr(8 downto 0),
336
         di      => wdata,
337
         do      => xdata(3)
338
      );
339
 
340
   rom_glue: process (cs, rw, addr, xdata)
341
   begin
342
      en <= (others=>'0');
343
      case addr(10 downto 9) is
344
      when "00" =>
345
         en(0)  <= cs;
346
         rdata  <= xdata(0);
347
      when "01" =>
348
         en(1)  <= cs;
349
         rdata  <= xdata(1);
350
      when "10" =>
351
         en(2)  <= cs;
352
         rdata  <= xdata(2);
353
      when "11" =>
354
         en(3)  <= cs;
355
         rdata  <= xdata(3);
356
      when others =>
357
         null;
358
      end case;
359
      we <= not rw;
360
   end process;
361
end architecture rtl;
362
 

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