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[/] [System09/] [trunk/] [rtl/] [Spartan3/] [sys09s3s.vhd] - Blame information for rev 138

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Line No. Rev Author Line
1 126 dilbert57
--===========================================================================--
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--                                                                           --
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--  Synthesizable 4K Sys09_bug ROM using Xilinx RAMB16_S9 Block RAM          --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : sys09s3s_b16.vhd
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--
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--  Entity name    : mon_rom
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--
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--  Purpose        : Implements a 4KByte Sys09_bug ROM 
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--                   for the 200K gate Digilent spartan 3 starter board
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--                   using two Xilinx RAMB16_S9 Block RAM
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--
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_arith
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--                   unisim.vcomponents
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--
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--  Uses           : SYS09BUG_F000
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--                   SYS09BUG_F800
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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--  Description    : Block RAM instatiation
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--
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--  Copyright (C) 2006 - 2010 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version Date        Author     Changes
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--
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-- 1.0     2006-11-21  John Kent  Initial version
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-- 1.1     2006-12-22  John Kent  Made into 4K ROM/RAM.
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-- 1.2     2010-06-17  John Kent  Added GPL and header
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--                                Renamed data input and output signals
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-- 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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        use unisim.vcomponents.all;
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entity mon_rom is
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    Port (
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       clk      : in  std_logic;
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                 rst      : in  std_logic;
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                 cs       : in  std_logic;
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       addr     : in  std_logic_vector (11 downto 0);
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                 rw       : in  std_logic;
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       data_in  : in  std_logic_vector (7 downto 0);
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       data_out : out std_logic_vector (7 downto 0)
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    );
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end mon_rom;
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architecture rtl of mon_rom is
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  signal we        : std_logic;
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  signal cs0       : std_logic;
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  signal cs1       : std_logic;
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  signal dp0       : std_logic;
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  signal dp1       : std_logic;
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  signal data_out0 : std_logic_vector(7 downto 0);
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  signal data_out1 : std_logic_vector(7 downto 0);
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component SYS09BUG_F000
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    Port (
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       clk      : in  std_logic;
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       rst      : in  std_logic;
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       cs       : in  std_logic;
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       addr     : in  std_logic_vector (10 downto 0);
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       rw       : in  std_logic;
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       data_in  : in  std_logic_vector (7 downto 0);
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       data_out : out std_logic_vector (7 downto 0)
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    );
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end component;
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component SYS09BUG_F800
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    Port (
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       clk      : in  std_logic;
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       rst      : in  std_logic;
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       cs       : in  std_logic;
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       addr     : in  std_logic_vector (10 downto 0);
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       rw       : in  std_logic;
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       data_in  : in  std_logic_vector (7 downto 0);
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       data_out : out std_logic_vector (7 downto 0)
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    );
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end component;
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begin
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   addr_f000 : SYS09BUG_F000 port map (
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       clk      => clk,
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       rst      => rst,
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       cs       => cs0,
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       addr     => addr(10 downto 0),
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       rw       => rw,
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       data_in  => data_in,
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       data_out => data_out0
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    );
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   addr_f800 : SYS09BUG_F800 port map (
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       clk      => clk,
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       rst      => rst,
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       cs       => cs1,
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       addr     => addr(10 downto 0),
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       rw       => rw,
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       data_in  => data_in,
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       data_out => data_out1
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    );
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my_mon : process ( rw, addr, cs, data_out0, data_out1 )
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begin
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         we    <= not rw;
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    cs0   <= '0';
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    cs1   <= '0';
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         case addr(11) is
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         when '0' =>
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           cs0   <= cs;
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                data_out <= data_out0;
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    when '1' =>
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                cs1   <= cs;
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                data_out <= data_out1;
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    when others =>
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      null;
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    end case;
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end process;
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end architecture rtl;
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