URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Spartan3/] [sys09s3s_b4.vhd] - Blame information for rev 138

Go to most recent revision | Details | Compare with Previous | View Log


library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
library unisim;
   use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
   port(
      clk    : in  std_logic;
      rst    : in  std_logic;
      cs     : in  std_logic;
      rw     : in  std_logic;
      addr   : in  std_logic_vector(10 downto 0);
      rdata  : out std_logic_vector(7 downto 0);
      wdata  : in  std_logic_vector(7 downto 0)
   );
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
   type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
   signal xdata : data_array;
   signal en : std_logic_vector(3 downto 0);
   signal we : std_logic;
 
component RAMB4_S8
generic (
   INIT_00, INIT_01, INIT_02, INIT_03,
   INIT_04, INIT_05, INIT_06, INIT_07,
   INIT_08, INIT_09, INIT_0A, INIT_0B,
   INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
    );
   port (
      clk, we, en, rst : in std_logic;
      addr : in std_logic_vector(8 downto 0);
      di   : in std_logic_vector(7 downto 0);
      do   : out std_logic_vector(7 downto 0)
      );
     end component RAMB4_S8;
 
   begin
 
   ROM00: RAMB4_S8
      generic map (
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
      )
      port map (
         clk     => clk,
         en      => en(0),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(0)
      );
 
   ROM01: RAMB4_S8
      generic map (
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
      )
      port map (
         clk     => clk,
         en      => en(1),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(1)
      );
 
   ROM02: RAMB4_S8
      generic map (
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
      )
      port map (
         clk     => clk,
         en      => en(2),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(2)
      );
 
   ROM03: RAMB4_S8
      generic map (
         INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
         INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
      )
      port map (
         clk     => clk,
         en      => en(3),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(3)
      );
 
   rom_glue: process (cs, rw, addr, xdata)
   begin
      en <= (others=>'0');
      case addr(10 downto 9) is
      when "00" =>
         en(0)  <= cs;
         rdata  <= xdata(0);
      when "01" =>
         en(1)  <= cs;
         rdata  <= xdata(1);
      when "10" =>
         en(2)  <= cs;
         rdata  <= xdata(2);
      when "11" =>
         en(3)  <= cs;
         rdata  <= xdata(3);
      when others =>
         null;
      end case;
      we <= not rw;
   end process;
end architecture rtl;
 
library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
library unisim;
   use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
   port(
      clk    : in  std_logic;
      rst    : in  std_logic;
      cs     : in  std_logic;
      rw     : in  std_logic;
      addr   : in  std_logic_vector(10 downto 0);
      rdata  : out std_logic_vector(7 downto 0);
      wdata  : in  std_logic_vector(7 downto 0)
   );
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
   type data_array is array(0 to 3) of std_logic_vector(7 downto 0);
   signal xdata : data_array;
   signal en : std_logic_vector(3 downto 0);
   signal we : std_logic;
 
component RAMB4_S8
generic (
   INIT_00, INIT_01, INIT_02, INIT_03,
   INIT_04, INIT_05, INIT_06, INIT_07,
   INIT_08, INIT_09, INIT_0A, INIT_0B,
   INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
    );
   port (
      clk, we, en, rst : in std_logic;
      addr : in std_logic_vector(8 downto 0);
      di   : in std_logic_vector(7 downto 0);
      do   : out std_logic_vector(7 downto 0)
      );
     end component RAMB4_S8;
 
   begin
 
   ROM00: RAMB4_S8
      generic map (
         INIT_00 => x"A780A610C6C0DF8E1062FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",
         INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
         INIT_02 => x"031796FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031772FE8EA304",
         INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B302179DFE8E2E",
         INIT_04 => x"20F002179FFE8EF52662FE8C02300F2780E129FE8E20C0022F60C14704174C04",
         INIT_05 => x"17A4A60F0417A50317211F650217A5FE8E121F2D296B03173B341FBC2094ADC0",
         INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",
         INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",
         INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
         INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117A5FE8E103439623203",
         INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",
         INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
         INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",
         INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
         INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
         INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7"
      )
      port map (
         clk     => clk,
         en      => en(0),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(0)
      );
 
   ROM01: RAMB4_S8
      generic map (
         INIT_00 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
         INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
         INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
         INIT_03 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E7",
         INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
         INIT_05 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",
         INIT_06 => x"2320008310062762A3E4ECF901171286E7FCBDE4AF0130492562AC4D2930344A",
         INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017E6FE8E64E720C602",
         INIT_08 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",
         INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F80016A10116903569001797FE8E",
         INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
         INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
         INIT_0c => x"BF0016311FF48DA9FE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",
         INIT_0d => x"8DBBFE8EE12044AED78DC1FE8EB4001643A6E18DC7FE8EF42048AEEA8DB5FE8E",
         INIT_0e => x"D02042A6B38DD2FE8ED92041A6BC8DCDFE8ECF204AAEC58DAFFE8ED82046AECE",
         INIT_0f => x"A5FE8EBF8DB88DB08DA98DA18D27FF17A5FE8E900016DEFE8EC4A6AA8DD7FE8E"
      )
      port map (
         clk     => clk,
         en      => en(1),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(1)
      );
 
   ROM02: RAMB4_S8
      generic map (
         INIT_00 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",
         INIT_01 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
         INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
         INIT_03 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",
         INIT_04 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",
         INIT_05 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",
         INIT_06 => x"35F6260885FA27028584A6E0DFBE1234498D2086008D8235018520E0B6052601",
         INIT_07 => x"0000CC30E08E39E2DFB7FF86016D84A7518684A70386E0DFBE138D903501A702",
         INIT_08 => x"DF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702A7FBDFFD",
         INIT_09 => x"1A815A271B81342708819635AF001784A70520098D042420810D20608D0427FE",
         INIT_0a => x"19C15CFBDFFC45260A810F270B8124270C81890027100D81382716817C002710",
         INIT_0b => x"5820212750814CFBDFB662204A2C27FBDFB66D205A34275DFBDFFC8F00167926",
         INIT_0c => x"39FEDF7F39FEDFB704263D81312754816E27598114273DC1FEDFF656200000CC",
         INIT_0d => x"1B20E12218C120C0FDDF7FFDDFF6ED224F812080FEDF7F39FDDFB70426FDDF7D",
         INIT_0e => x"02A7FBDFFDFCDFF64F39FEDF7FF726508102A74C84E720C6FBDFB6168D0000CC",
         INIT_0f => x"DFF604E75F012519C15C04E6E78D5AEA2619C15C4FF02650814CFBDFFC3903E7"
      )
      port map (
         clk     => clk,
         en      => en(2),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(2)
      );
 
   ROM03: RAMB4_S8
      generic map (
         INIT_00 => x"5FE4205F03E7FCDFF7082719C15CFCDFF6F42650C15C84A702E7FBDFF72086FB",
         INIT_01 => x"FB1953FB183DFB1531FB105EFB047FFB0369FB0274FB0139FEDFF702E7FBDFF7",
         INIT_02 => x"55D5F94488F958F1F853EDFB52A8F84DBCFA505EFA4CA5F847FDF8455CF94248",
         INIT_03 => x"2047554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F992FC",
         INIT_04 => x"57043E040000000A0D4B04202D202052455452415453335320524F4620362E31",
         INIT_05 => x"3D59492020043D53552020043D43502020043D5053202004202D20043F544148",
         INIT_06 => x"464504203A43432020043D422020043D412020043D50442020043D5849202004",
         INIT_07 => x"000000000000000000000000000000000000000000000004315343565A4E4948",
         INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
         INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
         INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
         INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
         INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
         INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
         INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
         INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
      )
      port map (
         clk     => clk,
         en      => en(3),
         we      => we,
         rst     => rst,
         addr    => addr(8 downto 0),
         di      => wdata,
         do      => xdata(3)
      );
 
   rom_glue: process (cs, rw, addr, xdata)
   begin
      en <= (others=>'0');
      case addr(10 downto 9) is
      when "00" =>
         en(0)  <= cs;
         rdata  <= xdata(0);
      when "01" =>
         en(1)  <= cs;
         rdata  <= xdata(1);
      when "10" =>
         en(2)  <= cs;
         rdata  <= xdata(2);
      when "11" =>
         en(3)  <= cs;
         rdata  <= xdata(3);
      when others =>
         null;
      end case;
      we <= not rw;
   end process;
end architecture rtl;
 

Browse

Tools

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Spartan3/] [sys09s3s_b4.vhd] - Blame information for rev 138

Line No.	Rev	Author	Line
1	126	dilbert57	`library IEEE;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_arith.all;`
4			`library unisim;`
5			`use unisim.vcomponents.all;`
6
7			`entity SYS09BUG_F000 is`
8			`port(`
9			`clk : in std_logic;`
10			`rst : in std_logic;`
11			`cs : in std_logic;`
12			`rw : in std_logic;`
13			`addr : in std_logic_vector(10 downto 0);`
14			`rdata : out std_logic_vector(7 downto 0);`
15			`wdata : in std_logic_vector(7 downto 0)`
16			`);`
17			`end SYS09BUG_F000;`
18
19			`architecture rtl of SYS09BUG_F000 is`
20
21			`type data_array is array(0 to 3) of std_logic_vector(7 downto 0);`
22			`signal xdata : data_array;`
23			`signal en : std_logic_vector(3 downto 0);`
24			`signal we : std_logic;`
25
26			`component RAMB4_S8`
27			`generic (`
28			`INIT_00, INIT_01, INIT_02, INIT_03,`
29			`INIT_04, INIT_05, INIT_06, INIT_07,`
30			`INIT_08, INIT_09, INIT_0A, INIT_0B,`
31			`INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)`
32			`);`
33			`port (`
34			`clk, we, en, rst : in std_logic;`
35			`addr : in std_logic_vector(8 downto 0);`
36			`di : in std_logic_vector(7 downto 0);`
37			`do : out std_logic_vector(7 downto 0)`
38			`);`
39			`end component RAMB4_S8;`
40
41			`begin`
42
43			`ROM00: RAMB4_S8`
44			`generic map (`
45			`INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",`
46			`INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",`
47			`INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",`
48			`INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",`
49			`INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",`
50			`INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",`
51			`INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",`
52			`INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",`
53			`INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",`
54			`INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",`
55			`INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",`
56			`INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",`
57			`INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",`
58			`INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",`
59			`INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",`
60			`INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"`
61			`)`
62			`port map (`
63			`clk => clk,`
64			`en => en(0),`
65			`we => we,`
66			`rst => rst,`
67			`addr => addr(8 downto 0),`
68			`di => wdata,`
69			`do => xdata(0)`
70			`);`
71
72			`ROM01: RAMB4_S8`
73			`generic map (`
74			`INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",`
75			`INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",`
76			`INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",`
77			`INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",`
78			`INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",`
79			`INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",`
80			`INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",`
81			`INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",`
82			`INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",`
83			`INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",`
84			`INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",`
85			`INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",`
86			`INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",`
87			`INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",`
88			`INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",`
89			`INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"`
90			`)`
91			`port map (`
92			`clk => clk,`
93			`en => en(1),`
94			`we => we,`
95			`rst => rst,`
96			`addr => addr(8 downto 0),`
97			`di => wdata,`
98			`do => xdata(1)`
99			`);`
100
101			`ROM02: RAMB4_S8`
102			`generic map (`
103			`INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",`
104			`INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",`
105			`INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",`
106			`INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",`
107			`INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",`
108			`INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",`
109			`INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",`
110			`INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",`
111			`INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",`
112			`INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",`
113			`INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",`
114			`INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",`
115			`INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",`
116			`INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",`
117			`INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",`
118			`INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"`
119			`)`
120			`port map (`
121			`clk => clk,`
122			`en => en(2),`
123			`we => we,`
124			`rst => rst,`
125			`addr => addr(8 downto 0),`
126			`di => wdata,`
127			`do => xdata(2)`
128			`);`
129
130			`ROM03: RAMB4_S8`
131			`generic map (`
132			`INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",`
133			`INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",`
134			`INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",`
135			`INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",`
136			`INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",`
137			`INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",`
138			`INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",`
139			`INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",`
140			`INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",`
141			`INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",`
142			`INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",`
143			`INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",`
144			`INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",`
145			`INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",`
146			`INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",`
147			`INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"`
148			`)`
149			`port map (`
150			`clk => clk,`
151			`en => en(3),`
152			`we => we,`
153			`rst => rst,`
154			`addr => addr(8 downto 0),`
155			`di => wdata,`
156			`do => xdata(3)`
157			`);`
158
159			`rom_glue: process (cs, rw, addr, xdata)`
160			`begin`
161			`en <= (others=>'0');`
162			`case addr(10 downto 9) is`
163			`when "00" =>`
164			`en(0) <= cs;`
165			`rdata <= xdata(0);`
166			`when "01" =>`
167			`en(1) <= cs;`
168			`rdata <= xdata(1);`
169			`when "10" =>`
170			`en(2) <= cs;`
171			`rdata <= xdata(2);`
172			`when "11" =>`
173			`en(3) <= cs;`
174			`rdata <= xdata(3);`
175			`when others =>`
176			`null;`
177			`end case;`
178			`we <= not rw;`
179			`end process;`
180			`end architecture rtl;`
181
182			`library IEEE;`
183			`use IEEE.std_logic_1164.all;`
184			`use IEEE.std_logic_arith.all;`
185			`library unisim;`
186			`use unisim.vcomponents.all;`
187
188			`entity SYS09BUG_F800 is`
189			`port(`
190			`clk : in std_logic;`
191			`rst : in std_logic;`
192			`cs : in std_logic;`
193			`rw : in std_logic;`
194			`addr : in std_logic_vector(10 downto 0);`
195			`rdata : out std_logic_vector(7 downto 0);`
196			`wdata : in std_logic_vector(7 downto 0)`
197			`);`
198			`end SYS09BUG_F800;`
199
200			`architecture rtl of SYS09BUG_F800 is`
201
202			`type data_array is array(0 to 3) of std_logic_vector(7 downto 0);`
203			`signal xdata : data_array;`
204			`signal en : std_logic_vector(3 downto 0);`
205			`signal we : std_logic;`
206
207			`component RAMB4_S8`
208			`generic (`
209			`INIT_00, INIT_01, INIT_02, INIT_03,`
210			`INIT_04, INIT_05, INIT_06, INIT_07,`
211			`INIT_08, INIT_09, INIT_0A, INIT_0B,`
212			`INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)`
213			`);`
214			`port (`
215			`clk, we, en, rst : in std_logic;`
216			`addr : in std_logic_vector(8 downto 0);`
217			`di : in std_logic_vector(7 downto 0);`
218			`do : out std_logic_vector(7 downto 0)`
219			`);`
220			`end component RAMB4_S8;`
221
222			`begin`
223
224			`ROM00: RAMB4_S8`
225			`generic map (`
226			`INIT_00 => x"A780A610C6C0DF8E1062FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",`
227			`INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",`
228			`INIT_02 => x"031796FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031772FE8EA304",`
229			`INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B302179DFE8E2E",`
230			`INIT_04 => x"20F002179FFE8EF52662FE8C02300F2780E129FE8E20C0022F60C14704174C04",`
231			`INIT_05 => x"17A4A60F0417A50317211F650217A5FE8E121F2D296B03173B341FBC2094ADC0",`
232			`INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",`
233			`INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",`
234			`INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",`
235			`INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117A5FE8E103439623203",`
236			`INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",`
237			`INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",`
238			`INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",`
239			`INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",`
240			`INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",`
241			`INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7"`
242			`)`
243			`port map (`
244			`clk => clk,`
245			`en => en(0),`
246			`we => we,`
247			`rst => rst,`
248			`addr => addr(8 downto 0),`
249			`di => wdata,`
250			`do => xdata(0)`
251			`);`
252
253			`ROM01: RAMB4_S8`
254			`generic map (`
255			`INIT_00 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",`
256			`INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",`
257			`INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",`
258			`INIT_03 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E7",`
259			`INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",`
260			`INIT_05 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",`
261			`INIT_06 => x"2320008310062762A3E4ECF901171286E7FCBDE4AF0130492562AC4D2930344A",`
262			`INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017E6FE8E64E720C602",`
263			`INIT_08 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",`
264			`INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F80016A10116903569001797FE8E",`
265			`INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",`
266			`INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",`
267			`INIT_0c => x"BF0016311FF48DA9FE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",`
268			`INIT_0d => x"8DBBFE8EE12044AED78DC1FE8EB4001643A6E18DC7FE8EF42048AEEA8DB5FE8E",`
269			`INIT_0e => x"D02042A6B38DD2FE8ED92041A6BC8DCDFE8ECF204AAEC58DAFFE8ED82046AECE",`
270			`INIT_0f => x"A5FE8EBF8DB88DB08DA98DA18D27FF17A5FE8E900016DEFE8EC4A6AA8DD7FE8E"`
271			`)`
272			`port map (`
273			`clk => clk,`
274			`en => en(1),`
275			`we => we,`
276			`rst => rst,`
277			`addr => addr(8 downto 0),`
278			`di => wdata,`
279			`do => xdata(1)`
280			`);`
281
282			`ROM02: RAMB4_S8`
283			`generic map (`
284			`INIT_00 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",`
285			`INIT_01 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",`
286			`INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",`
287			`INIT_03 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",`
288			`INIT_04 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",`
289			`INIT_05 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",`
290			`INIT_06 => x"35F6260885FA27028584A6E0DFBE1234498D2086008D8235018520E0B6052601",`
291			`INIT_07 => x"0000CC30E08E39E2DFB7FF86016D84A7518684A70386E0DFBE138D903501A702",`
292			`INIT_08 => x"DF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702A7FBDFFD",`
293			`INIT_09 => x"1A815A271B81342708819635AF001784A70520098D042420810D20608D0427FE",`
294			`INIT_0a => x"19C15CFBDFFC45260A810F270B8124270C81890027100D81382716817C002710",`
295			`INIT_0b => x"5820212750814CFBDFB662204A2C27FBDFB66D205A34275DFBDFFC8F00167926",`
296			`INIT_0c => x"39FEDF7F39FEDFB704263D81312754816E27598114273DC1FEDFF656200000CC",`
297			`INIT_0d => x"1B20E12218C120C0FDDF7FFDDFF6ED224F812080FEDF7F39FDDFB70426FDDF7D",`
298			`INIT_0e => x"02A7FBDFFDFCDFF64F39FEDF7FF726508102A74C84E720C6FBDFB6168D0000CC",`
299			`INIT_0f => x"DFF604E75F012519C15C04E6E78D5AEA2619C15C4FF02650814CFBDFFC3903E7"`
300			`)`
301			`port map (`
302			`clk => clk,`
303			`en => en(2),`
304			`we => we,`
305			`rst => rst,`
306			`addr => addr(8 downto 0),`
307			`di => wdata,`
308			`do => xdata(2)`
309			`);`
310
311			`ROM03: RAMB4_S8`
312			`generic map (`
313			`INIT_00 => x"5FE4205F03E7FCDFF7082719C15CFCDFF6F42650C15C84A702E7FBDFF72086FB",`
314			`INIT_01 => x"FB1953FB183DFB1531FB105EFB047FFB0369FB0274FB0139FEDFF702E7FBDFF7",`
315			`INIT_02 => x"55D5F94488F958F1F853EDFB52A8F84DBCFA505EFA4CA5F847FDF8455CF94248",`
316			`INIT_03 => x"2047554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F992FC",`
317			`INIT_04 => x"57043E040000000A0D4B04202D202052455452415453335320524F4620362E31",`
318			`INIT_05 => x"3D59492020043D53552020043D43502020043D5053202004202D20043F544148",`
319			`INIT_06 => x"464504203A43432020043D422020043D412020043D50442020043D5849202004",`
320			`INIT_07 => x"000000000000000000000000000000000000000000000004315343565A4E4948",`
321			`INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",`
322			`INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",`
323			`INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",`
324			`INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",`
325			`INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",`
326			`INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",`
327			`INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",`
328			`INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"`
329			`)`
330			`port map (`
331			`clk => clk,`
332			`en => en(3),`
333			`we => we,`
334			`rst => rst,`
335			`addr => addr(8 downto 0),`
336			`di => wdata,`
337			`do => xdata(3)`
338			`);`
339
340			`rom_glue: process (cs, rw, addr, xdata)`
341			`begin`
342			`en <= (others=>'0');`
343			`case addr(10 downto 9) is`
344			`when "00" =>`
345			`en(0) <= cs;`
346			`rdata <= xdata(0);`
347			`when "01" =>`
348			`en(1) <= cs;`
349			`rdata <= xdata(1);`
350			`when "10" =>`
351			`en(2) <= cs;`
352			`rdata <= xdata(2);`
353			`when "11" =>`
354			`en(3) <= cs;`
355			`rdata <= xdata(3);`
356			`when others =>`
357			`null;`
358			`end case;`
359			`we <= not rw;`
360			`end process;`
361			`end architecture rtl;`
362