| 1 |
19 |
dilbert57 |
#### UCF file created by Project Navigator
|
| 2 |
|
|
#
|
| 3 |
|
|
# PIN DEFINITION FOR BURCHED SPARTAN2 B3
|
| 4 |
|
|
# XC2S200.
|
| 5 |
|
|
#
|
| 6 |
|
|
# B3 Connector J3
|
| 7 |
107 |
davidgb |
# IDE / CF Interface
|
| 8 |
|
|
# Note that this pin out is NOT consistant with the B5-IDE
|
| 9 |
19 |
dilbert57 |
#
|
| 10 |
107 |
davidgb |
#NET "ide_gclk1" LOC = "p185"; #pin 2 (Global clock input)
|
| 11 |
|
|
#NET "ide_spare1" LOC = "p181"; #pin 3
|
| 12 |
|
|
NET "ide_rst_n" LOC = "p187"; #pin 4 - ide pin 1
|
| 13 |
|
|
NET "ide_dmarq" LOC = "p188"; #pin 5 - ide pin 21
|
| 14 |
|
|
NET "pb_iowr_n" LOC = "p189"; #pin 6 - ide pin 23
|
| 15 |
|
|
NET "pb_iord_n" LOC = "p191"; #pin 7 - ide pin 25
|
| 16 |
|
|
NET "ide_iordy" LOC = "p192"; #pin 8 - ide pin 27
|
| 17 |
|
|
NET "ide_con_csel" LOC = "p193"; #pin 9 - ide pin 28
|
| 18 |
|
|
NET "ide_dmack_n" LOC = "p194"; #pin 10 - ide pin 29
|
| 19 |
|
|
NET "ide_intrq" LOC = "p195"; #pin 11 - ide pin 31
|
| 20 |
|
|
NET "ide_iocs16_n" LOC = "p199"; #pin 12 - ide pin 32
|
| 21 |
|
|
NET "pb_addr<1>" LOC = "p200"; #pin 13 - ide pin 33
|
| 22 |
|
|
NET "ide_pdiag_n" LOC = "p201"; #pin 14 - ide pin 34
|
| 23 |
|
|
NET "pb_addr<0>" LOC = "p202"; #pin 15 - ide pin 35
|
| 24 |
|
|
NET "pb_addr<2>" LOC = "p203"; #pin 16 - ide pin 36
|
| 25 |
|
|
NET "ide_cs0_n" LOC = "p204"; #pin 17 - ide pin 37
|
| 26 |
|
|
NET "ide_cs1_n" LOC = "p205"; #pin 18 - ide pin 38
|
| 27 |
|
|
NET "ide_dasp_n" LOC = "p206"; #pin 19 - ide pin 39
|
| 28 |
19 |
dilbert57 |
#
|
| 29 |
|
|
# B3 Connector J4
|
| 30 |
107 |
davidgb |
# IDE / CF Interface
|
| 31 |
|
|
# Note that this pin out is NOT consistant with the B5-IDE
|
| 32 |
|
|
# It's called the peripheral bus for consistance with the XESS board
|
| 33 |
19 |
dilbert57 |
#
|
| 34 |
107 |
davidgb |
#NET "pb_gclk2" LOC = "p182"; #pin 2 (Global clock input)
|
| 35 |
|
|
#NET "pb_spare2" LOC = "p160"; #pin 3
|
| 36 |
|
|
NET "pb_data<7>" LOC = "p161"; #pin 4 - ide pin 3
|
| 37 |
|
|
NET "pb_data<8>" LOC = "p162"; #pin 5 - ide pin 4
|
| 38 |
|
|
NET "pb_data<6>" LOC = "p163"; #pin 6 - ide pin 5
|
| 39 |
|
|
NET "pb_data<9>" LOC = "p164"; #pin 7 - ide pin 6
|
| 40 |
|
|
NET "pb_data<5>" LOC = "p165"; #pin 8 - ide pin 7
|
| 41 |
|
|
NET "pb_data<10>" LOC = "p166"; #pin 9 - ide pin 8
|
| 42 |
|
|
NET "pb_data<4>" LOC = "p167"; #pin 10 - ide pin 9
|
| 43 |
|
|
NET "pb_data<11>" LOC = "p168"; #pin 11 - ide pin 10
|
| 44 |
|
|
NET "pb_data<3>" LOC = "p172"; #pin 12 - ide pin 11
|
| 45 |
|
|
NET "pb_data<12>" LOC = "p173"; #pin 13 - ide pin 12
|
| 46 |
|
|
NET "pb_data<2>" LOC = "p174"; #pin 14 - ide pin 13
|
| 47 |
|
|
NET "pb_data<13>" LOC = "p175"; #pin 15 - ide pin 14
|
| 48 |
|
|
NET "pb_data<1>" LOC = "p176"; #pin 16 - ide pin 15
|
| 49 |
|
|
NET "pb_data<14>" LOC = "p178"; #pin 17 - ide pin 16
|
| 50 |
|
|
NET "pb_data<0>" LOC = "p179"; #pin 18 - ide pin 17
|
| 51 |
|
|
NET "pb_data<15>" LOC = "p180"; #pin 19 - ide pin 18
|
| 52 |
19 |
dilbert57 |
#
|
| 53 |
|
|
# Connector J3
|
| 54 |
|
|
# For B5-Compact-Flash:
|
| 55 |
|
|
#
|
| 56 |
|
|
#NET "GCK3" LOC = "P185"; #J2-2 (Global Clock input)
|
| 57 |
|
|
#NET "IO" LOC = "P181"; #J2-3
|
| 58 |
|
|
#NET "IO" LOC = "P187"; #J2-4
|
| 59 |
|
|
#NET "IO" LOC = "P188"; #J2-5
|
| 60 |
|
|
#NET "cf_a<2>" LOC = "P189"; #J2-6
|
| 61 |
|
|
#NET "cf_a<1>" LOC = "P191"; #J2-7
|
| 62 |
|
|
#NET "cf_a<0>" LOC = "P192"; #J2-8
|
| 63 |
|
|
#NET "cf_d<0>" LOC = "P193"; #J2-9
|
| 64 |
|
|
#NET "cf_d<1>" LOC = "P194"; #J2-10
|
| 65 |
|
|
#NET "cf_d<2>" LOC = "P195"; #J2-11
|
| 66 |
|
|
#NET "cf_cs16_n" LOC = "P199"; #J2-12
|
| 67 |
|
|
#NET "cf_d<10>" LOC = "P200"; #J2-13
|
| 68 |
|
|
#NET "cf_d<9>" LOC = "P201"; #J2-14
|
| 69 |
|
|
#NET "cf_d<8>" LOC = "P202"; #J2-15
|
| 70 |
|
|
#NET "cf_pdiag" LOC = "P203"; #J2-16
|
| 71 |
|
|
#NET "cf_dase" LOC = "P204"; #J2-17
|
| 72 |
|
|
#NET "cf_iordy" LOC = "P205"; #J2-18
|
| 73 |
|
|
#NET "cf_rst_n" LOC = "P206"; #J2-19
|
| 74 |
|
|
#
|
| 75 |
|
|
# Connector J4
|
| 76 |
|
|
# For B5-Compact-Flash:
|
| 77 |
|
|
#
|
| 78 |
|
|
#NET "GCK2" LOC = "P182"; #J1-2 (Global Clock Input)
|
| 79 |
|
|
#NET "IO" LOC = "P160"; #J1-3
|
| 80 |
|
|
#NET "cf_intrq" LOC = "P161"; #J1-4
|
| 81 |
|
|
#NET "cf_wr_n" LOC = "P162"; #J1-5
|
| 82 |
|
|
#NET "cf_rd_n" LOC = "P163"; #J1-6
|
| 83 |
|
|
#NET "cf_cs1_n" LOC = "P164"; #J1-7
|
| 84 |
|
|
#NET "cf_d<15>" LOC = "P165"; #J1-8
|
| 85 |
|
|
#NET "cf_d<14>" LOC = "P166"; #J1-9
|
| 86 |
|
|
#NET "cf_d<13>" LOC = "P167"; #J1-10
|
| 87 |
|
|
#NET "cf_d<12>" LOC = "P168"; #J1-11
|
| 88 |
|
|
#NET "cf_d<11>" LOC = "P172"; #J1-12
|
| 89 |
|
|
#NET "cf_present" LOC = "P173"; #J1-13
|
| 90 |
|
|
#NET "cf_d<3>" LOC = "P174"; #J1-14
|
| 91 |
|
|
#NET "cf_d<4>" LOC = "P175"; #J1-15
|
| 92 |
|
|
#NET "cf_d<5>" LOC = "P176"; #J1-16
|
| 93 |
|
|
#NET "cf_d<6>" LOC = "P178"; #J1-17
|
| 94 |
|
|
#NET "cf_d<7>" LOC = "P179"; #J1-18
|
| 95 |
|
|
#NET "cf_cs0_n" LOC = "P180"; #J1-19
|
| 96 |
|
|
#
|
| 97 |
|
|
# Connector J6
|
| 98 |
|
|
#
|
| 99 |
|
|
# For modified B3-SRAM
|
| 100 |
|
|
# Note: B3-SRAM must be fitted to J6/J9
|
| 101 |
|
|
#
|
| 102 |
|
|
NET "ram_data<0>" LOC = "p133"; #J2-2 (I/O - not a global clock input)
|
| 103 |
|
|
NET "ram_data<1>" LOC = "p134"; #J2-3
|
| 104 |
|
|
NET "ram_data<2>" LOC = "p135"; #J2-4
|
| 105 |
|
|
NET "ram_data<3>" LOC = "p136"; #J2-5
|
| 106 |
|
|
NET "ram_data<4>" LOC = "p138"; #J2-6
|
| 107 |
|
|
NET "ram_data<5>" LOC = "p139"; #J2-7
|
| 108 |
|
|
NET "ram_data<6>" LOC = "p140"; #J2-8
|
| 109 |
|
|
NET "ram_data<7>" LOC = "p141"; #J2-9
|
| 110 |
|
|
NET "ram_data<8>" LOC = "p142"; #J2-10
|
| 111 |
|
|
NET "ram_data<9>" LOC = "p146"; #J2-11
|
| 112 |
|
|
NET "ram_data<10>" LOC = "p147"; #J2-12
|
| 113 |
|
|
NET "ram_data<11>" LOC = "p148"; #J2-13
|
| 114 |
|
|
NET "ram_data<12>" LOC = "p149"; #J2-14
|
| 115 |
|
|
NET "ram_data<13>" LOC = "p150"; #J2-15
|
| 116 |
|
|
NET "ram_data<14>" LOC = "p151"; #J2-16
|
| 117 |
|
|
NET "ram_data<15>" LOC = "p152"; #J2-17
|
| 118 |
|
|
NET "ram_wrun" LOC = "p153"; #J2-18
|
| 119 |
|
|
NET "ram_wrln" LOC = "p154"; #J2-19
|
| 120 |
|
|
#
|
| 121 |
|
|
# Connector J9
|
| 122 |
|
|
#
|
| 123 |
|
|
# For modified B3-SRAM
|
| 124 |
|
|
# Note: B3-SRAM must be fitted to J6/J9
|
| 125 |
|
|
#
|
| 126 |
|
|
NET "ram_addr<0>" LOC = "p108"; #J1-2 (I/O - not a global clock input)
|
| 127 |
|
|
NET "ram_addr<1>" LOC = "p109"; #J1-3
|
| 128 |
|
|
NET "ram_addr<2>" LOC = "p110"; #J1-4
|
| 129 |
|
|
NET "ram_addr<3>" LOC = "p111"; #J1-5
|
| 130 |
|
|
NET "ram_addr<4>" LOC = "p112"; #J1-6
|
| 131 |
|
|
NET "ram_addr<5>" LOC = "p113"; #J1-7
|
| 132 |
|
|
NET "ram_addr<6>" LOC = "p114"; #J1-8
|
| 133 |
|
|
NET "ram_addr<7>" LOC = "p115"; #J1-9
|
| 134 |
|
|
NET "ram_csn" LOC = "p119"; #J1-10
|
| 135 |
|
|
NET "ram_addr<8>" LOC = "p120"; #J1-11
|
| 136 |
|
|
NET "ram_addr<9>" LOC = "p121"; #J1-12
|
| 137 |
|
|
NET "ram_addr<10>" LOC = "p122"; #J1-13
|
| 138 |
|
|
NET "ram_addr<11>" LOC = "p123"; #J1-14
|
| 139 |
|
|
NET "ram_addr<12>" LOC = "p125"; #J1-15
|
| 140 |
|
|
NET "ram_addr<13>" LOC = "p126"; #J1-16
|
| 141 |
|
|
NET "ram_addr<14>" LOC = "p127"; #J1-17
|
| 142 |
|
|
NET "ram_addr<15>" LOC = "p129"; #J1-18
|
| 143 |
|
|
NET "ram_addr<16>" LOC = "p132"; #J1-19
|
| 144 |
|
|
#
|
| 145 |
|
|
# Connector J10
|
| 146 |
107 |
davidgb |
# B5-X300 Interface to Dual Port RAM
|
| 147 |
19 |
dilbert57 |
#
|
| 148 |
107 |
davidgb |
NET "clk_in" LOC = "p77"; #pin 2 (GCK1 - global clock input)
|
| 149 |
|
|
NET "led" LOC = "p49"; #pin 3 (LED output)
|
| 150 |
|
|
NET "bus_cs_n" LOC = "p57"; #pin 4
|
| 151 |
|
|
NET "bus_rw" LOC = "p58"; #pin 5
|
| 152 |
|
|
NET "bus_addr<12>" LOC = "p59"; #pin 6
|
| 153 |
|
|
NET "bus_addr<11>" LOC = "p60"; #pin 7
|
| 154 |
|
|
NET "rst_n" LOC = "p61"; #pin 8 (Test Input button)
|
| 155 |
|
|
NET "bus_addr<10>" LOC = "p62"; #pin 9
|
| 156 |
|
|
NET "bus_addr<9>" LOC = "p63"; #pin 10
|
| 157 |
|
|
NET "bus_addr<8>" LOC = "p67"; #pin 11
|
| 158 |
|
|
NET "bus_addr<7>" LOC = "p68"; #pin 12
|
| 159 |
|
|
NET "bus_addr<6>" LOC = "p69"; #pin 13
|
| 160 |
|
|
NET "bus_addr<5>" LOC = "p70"; #pin 14
|
| 161 |
|
|
NET "bus_addr<4>" LOC = "p71"; #pin 15
|
| 162 |
|
|
NET "bus_addr<3>" LOC = "p73"; #pin 16
|
| 163 |
|
|
NET "bus_addr<2>" LOC = "p74"; #pin 17
|
| 164 |
|
|
NET "bus_addr<1>" LOC = "p75"; #pin 18
|
| 165 |
|
|
NET "bus_addr<0>" LOC = "p81"; #pin 19
|
| 166 |
19 |
dilbert57 |
#
|
| 167 |
107 |
davidgb |
# Connector J11
|
| 168 |
|
|
# B5-X300 Interface to Dual Port RAM
|
| 169 |
19 |
dilbert57 |
#
|
| 170 |
|
|
#NET "GCK0" LOC = "p80"; #pin 2 (Global Clock input)
|
| 171 |
107 |
davidgb |
NET "bus_data_in<7>" LOC = "p82"; #pin 3
|
| 172 |
|
|
NET "bus_data_in<6>" LOC = "p83"; #pin 4
|
| 173 |
|
|
NET "bus_data_in<5>" LOC = "p84"; #pin 5
|
| 174 |
|
|
NET "bus_data_in<4>" LOC = "p86"; #pin 6
|
| 175 |
|
|
NET "bus_data_in<3>" LOC = "p87"; #pin 7
|
| 176 |
|
|
NET "bus_data_in<2>" LOC = "p88"; #pin 8
|
| 177 |
|
|
NET "bus_data_in<1>" LOC = "p89"; #pin 9
|
| 178 |
|
|
NET "bus_data_in<0>" LOC = "p90"; #pin 10
|
| 179 |
|
|
NET "bus_data_out<7>" LOC = "p94"; #pin 11
|
| 180 |
|
|
NET "bus_data_out<6>" LOC = "p95"; #pin 12
|
| 181 |
|
|
NET "bus_data_out<5>" LOC = "p96"; #pin 13
|
| 182 |
|
|
NET "bus_data_out<4>" LOC = "p97"; #pin 14
|
| 183 |
|
|
NET "bus_data_out<3>" LOC = "p98"; #pin 15
|
| 184 |
|
|
NET "bus_data_out<2>" LOC = "p99"; #pin 16
|
| 185 |
|
|
NET "bus_data_out<1>" LOC = "p100"; #pin 17
|
| 186 |
|
|
NET "bus_data_out<0>" LOC = "p101"; #pin 18
|
| 187 |
|
|
NET "bus_clk" LOC = "p102"; #pin 19
|
| 188 |
19 |
dilbert57 |
#
|
| 189 |
|
|
# Connector J8
|
| 190 |
|
|
#
|
| 191 |
|
|
# B3-FPGA-CPU-IO Module
|
| 192 |
|
|
#
|
| 193 |
|
|
#NET "aux_clock" LOC = "p24"; #J1-2 (Note this is an I/O pad ... not a clock input)
|
| 194 |
|
|
#NET "buzzer" LOC = "p27"; #J1-3
|
| 195 |
|
|
#NET "mouse_clock" LOC = "p29"; #J1-4
|
| 196 |
|
|
#NET "mouse_data" LOC = "p30"; #J1-5
|
| 197 |
107 |
davidgb |
NET "acia_cts_n" LOC = "p31"; #J1-6
|
| 198 |
|
|
NET "acia_rts_n" LOC = "p33"; #J1-7
|
| 199 |
|
|
NET "acia_txd" LOC = "p34"; #J1-8
|
| 200 |
|
|
NET "acia_rxd" LOC = "p35"; #J1-9
|
| 201 |
19 |
dilbert57 |
NET "kb_clock" LOC = "p36"; #J1-10
|
| 202 |
|
|
NET "kb_data" LOC = "p37"; #J1-11
|
| 203 |
107 |
davidgb |
NET "vga_vsync" LOC = "p41"; #J1-12
|
| 204 |
|
|
NET "vga_hsync" LOC = "p42"; #J1-13
|
| 205 |
|
|
NET "vga_blue<0>" LOC = "p43"; #J1-14
|
| 206 |
|
|
NET "vga_blue<1>" LOC = "p44"; #J1-15
|
| 207 |
|
|
NET "vga_green<0>" LOC = "p45"; #J1-16
|
| 208 |
|
|
NET "vga_green<1>" LOC = "p46"; #J1-17
|
| 209 |
|
|
NET "vga_red<0>" LOC = "p47"; #J1-18
|
| 210 |
|
|
NET "vga_red<1>" LOC = "p48"; #J1-19
|
| 211 |
19 |
dilbert57 |
#
|
| 212 |
|
|
# Connector J5
|
| 213 |
|
|
#
|
| 214 |
|
|
# Printer port
|
| 215 |
|
|
#
|
| 216 |
107 |
davidgb |
NET "pp_ctrl<0>" LOC = "p3"; #J5-1 DB25 - 1 strobe_n
|
| 217 |
|
|
NET "pp_ctrl<1>" LOC = "p4"; #J5-2 DB25 - 14 auto Linefeed
|
| 218 |
|
|
NET "pp_data<0>" LOC = "p5"; #J5-3 DB25 - 2 data<0>
|
| 219 |
|
|
NET "pp_stat<3>" LOC = "p6"; #J5-4 DB25 - 15 error_n
|
| 220 |
|
|
NET "pp_data<1>" LOC = "p7"; #J5-5 DB25 - 3 data<1>
|
| 221 |
|
|
NET "pp_ctrl<2>" LOC = "p8"; #J5-6 DB25 - 16 initialize_n
|
| 222 |
|
|
NET "pp_data<2>" LOC = "p9"; #J5-7 DB25 - 4 data<2>
|
| 223 |
|
|
NET "pp_ctrl<3>" LOC = "p10"; #J5-8 DB25 - 17 select_printer_n
|
| 224 |
|
|
NET "pp_data<3>" LOC = "p14"; #J5-9 DB25 - 5 data<3>
|
| 225 |
|
|
# #J5-10 DB25 - 18 ground
|
| 226 |
|
|
NET "pp_data<4>" LOC = "p15"; #J5-11 DB25 - 6 data<4>
|
| 227 |
|
|
# #J5-12 DB25 - 19 ground
|
| 228 |
|
|
NET "pp_data<5>" LOC = "p16"; #J5-13 DB25 - 7 data<5>
|
| 229 |
|
|
# #J5-14 DB25 - 20 ground
|
| 230 |
|
|
NET "pp_data<6>" LOC = "p17"; #J5-15 DB25 - 8 data<6>
|
| 231 |
|
|
# #J5-16 DB25 - 21 ground
|
| 232 |
|
|
NET "pp_data<7>" LOC = "p18"; #J5-17 DB25 - 9 data<7>
|
| 233 |
|
|
# #J5-18 DB25 - 22 ground
|
| 234 |
|
|
NET "pp_stat<6>" LOC = "p20"; #J5-19 DB25 - 10 ack_n
|
| 235 |
|
|
# #J5-20 DB25 - 23 ground
|
| 236 |
|
|
NET "pp_stat<7>" LOC = "p21"; #J5-21 DB25 - 11 busy
|
| 237 |
|
|
# #J5-22 DB25 - 24 ground
|
| 238 |
|
|
NET "pp_stat<5>" LOC = "p22"; #J5-23 DB25 - 12 paper_out
|
| 239 |
|
|
# #J5-24 DB25 - 25 ground
|
| 240 |
|
|
NET "pp_stat<4>" LOC = "p23"; #J5-25 DB25 - 13 select
|
| 241 |
|
|
# #J5-26 +3.3V
|
| 242 |
|
|
# Parallel printer port pin assignment
|
| 243 |
|
|
#
|
| 244 |
|
|
# Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
|
| 245 |
|
|
# 1 nStrobe Write_n Out Control-0 Yes
|
| 246 |
|
|
# 2 Data0 Data0 In/Out Data-0 No
|
| 247 |
|
|
# 3 Data1 Data1 In/Out Data-1 No
|
| 248 |
|
|
# 4 Data2 Data2 In/Out Data-2 No
|
| 249 |
|
|
# 5 Data3 Data3 In/Out Data-3 No
|
| 250 |
|
|
# 6 Data4 Data4 In/Out Data-4 No
|
| 251 |
|
|
# 7 Data5 Data5 In/Out Data-5 No
|
| 252 |
|
|
# 8 Data6 Data6 In/Out Data-6 No
|
| 253 |
|
|
# 9 Data7 Data7 In/Out Data-7 No
|
| 254 |
|
|
# 10 nAck Interrupt In Status-6 No
|
| 255 |
|
|
# 11 Busy Wait In Status-7 Yes
|
| 256 |
|
|
# 12 Paper-Out Spare In Status-5 No
|
| 257 |
|
|
# 13 Select Spare In Status-4 No
|
| 258 |
|
|
#
|
| 259 |
|
|
# 14 Linefeed Data_Strobe_n Out Control-1 Yes
|
| 260 |
|
|
# 15 nError Spare In Status-3 No
|
| 261 |
|
|
# 16 nInitialize Reset Out Control-2 No
|
| 262 |
|
|
# 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
|
| 263 |
|
|
# 18-25 Ground Ground - - -
|
| 264 |
|
|
#
|
| 265 |
|
|
# Address MSB LSB
|
| 266 |
|
|
# Bit: 7 6 5 4 3 2 1 0
|
| 267 |
|
|
#Base (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
|
| 268 |
|
|
#Base+1 (SPP Status port) Read Pin: ~11 10 12 13 15
|
| 269 |
|
|
#Base+2 (SPP Control port) Write Pin: ~17 16 ~14 ~1
|
| 270 |
|
|
#Base+3 (EPP Address port) R/W
|
| 271 |
|
|
#Base+4 (EPP Data port) R/W
|
| 272 |
|
|
#
|
| 273 |
|
|
# ~ indicates a hardware inversion of the bit.
|
| 274 |
|
|
#
|
| 275 |
|
|
#
|
| 276 |
19 |
dilbert57 |
# Timing Groups
|
| 277 |
|
|
#
|
| 278 |
|
|
INST "ram_addr<0>" TNM = "ram_addr";
|
| 279 |
|
|
INST "ram_addr<1>" TNM = "ram_addr";
|
| 280 |
|
|
INST "ram_addr<2>" TNM = "ram_addr";
|
| 281 |
|
|
INST "ram_addr<3>" TNM = "ram_addr";
|
| 282 |
|
|
INST "ram_addr<4>" TNM = "ram_addr";
|
| 283 |
|
|
INST "ram_addr<5>" TNM = "ram_addr";
|
| 284 |
|
|
INST "ram_addr<6>" TNM = "ram_addr";
|
| 285 |
|
|
INST "ram_addr<7>" TNM = "ram_addr";
|
| 286 |
|
|
INST "ram_addr<8>" TNM = "ram_addr";
|
| 287 |
|
|
INST "ram_addr<9>" TNM = "ram_addr";
|
| 288 |
|
|
INST "ram_addr<10>" TNM = "ram_addr";
|
| 289 |
|
|
INST "ram_addr<11>" TNM = "ram_addr";
|
| 290 |
|
|
INST "ram_addr<12>" TNM = "ram_addr";
|
| 291 |
|
|
INST "ram_addr<13>" TNM = "ram_addr";
|
| 292 |
|
|
INST "ram_addr<14>" TNM = "ram_addr";
|
| 293 |
|
|
INST "ram_addr<15>" TNM = "ram_addr";
|
| 294 |
|
|
INST "ram_addr<16>" TNM = "ram_addr";
|
| 295 |
|
|
#
|
| 296 |
|
|
INST "ram_data<0>" TNM = "ram_data";
|
| 297 |
|
|
INST "ram_data<1>" TNM = "ram_data";
|
| 298 |
|
|
INST "ram_data<2>" TNM = "ram_data";
|
| 299 |
|
|
INST "ram_data<3>" TNM = "ram_data";
|
| 300 |
|
|
INST "ram_data<4>" TNM = "ram_data";
|
| 301 |
|
|
INST "ram_data<5>" TNM = "ram_data";
|
| 302 |
|
|
INST "ram_data<6>" TNM = "ram_data";
|
| 303 |
|
|
INST "ram_data<7>" TNM = "ram_data";
|
| 304 |
|
|
INST "ram_data<8>" TNM = "ram_data";
|
| 305 |
|
|
INST "ram_data<9>" TNM = "ram_data";
|
| 306 |
|
|
INST "ram_data<10>" TNM = "ram_data";
|
| 307 |
|
|
INST "ram_data<11>" TNM = "ram_data";
|
| 308 |
|
|
INST "ram_data<12>" TNM = "ram_data";
|
| 309 |
|
|
INST "ram_data<13>" TNM = "ram_data";
|
| 310 |
|
|
INST "ram_data<14>" TNM = "ram_data";
|
| 311 |
|
|
INST "ram_data<15>" TNM = "ram_data";
|
| 312 |
|
|
#
|
| 313 |
|
|
INST "ram_wrln" TNM = "ram_wr";
|
| 314 |
|
|
INST "ram_wrun" TNM = "ram_wr";
|
| 315 |
|
|
#INST "ram_csn" TNM = "ram_cs";
|
| 316 |
|
|
#
|
| 317 |
|
|
# Timing Constraints
|
| 318 |
|
|
#
|
| 319 |
107 |
davidgb |
NET "clk_in" TNM_NET = "clk_in";
|
| 320 |
|
|
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %;
|
| 321 |
|
|
#TIMEGRP "ram_cs" OFFSET = OUT 55 ns AFTER "clk_in";
|
| 322 |
|
|
#TIMEGRP "ram_wr" OFFSET = OUT 55 ns AFTER "clk_in";
|
| 323 |
|
|
#TIMEGRP "ram_addr" OFFSET = OUT 55 ns AFTER "clk_in";
|
| 324 |
|
|
#TIMEGRP "ram_data" OFFSET = OUT 55 ns AFTER "clk_in";
|
| 325 |
|
|
#TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "clk_in";
|
| 326 |
19 |
dilbert57 |
#
|
| 327 |
|
|
# Fast I/O Pins
|
| 328 |
|
|
#
|
| 329 |
|
|
NET "ram_addr<0>" FAST;
|
| 330 |
|
|
NET "ram_addr<1>" FAST;
|
| 331 |
|
|
NET "ram_addr<2>" FAST;
|
| 332 |
|
|
NET "ram_addr<3>" FAST;
|
| 333 |
|
|
NET "ram_addr<4>" FAST;
|
| 334 |
|
|
NET "ram_addr<5>" FAST;
|
| 335 |
|
|
NET "ram_addr<6>" FAST;
|
| 336 |
|
|
NET "ram_addr<7>" FAST;
|
| 337 |
|
|
NET "ram_addr<8>" FAST;
|
| 338 |
|
|
NET "ram_addr<9>" FAST;
|
| 339 |
|
|
NET "ram_addr<10>" FAST;
|
| 340 |
|
|
NET "ram_addr<11>" FAST;
|
| 341 |
|
|
NET "ram_addr<12>" FAST;
|
| 342 |
|
|
NET "ram_addr<13>" FAST;
|
| 343 |
|
|
NET "ram_addr<14>" FAST;
|
| 344 |
|
|
NET "ram_addr<15>" FAST;
|
| 345 |
|
|
NET "ram_addr<16>" FAST;
|
| 346 |
|
|
#
|
| 347 |
|
|
NET "ram_wrln" FAST;
|
| 348 |
|
|
NET "ram_wrun" FAST;
|
| 349 |
|
|
NET "ram_csn" FAST;
|
| 350 |
|
|
#
|
| 351 |
|
|
NET "ram_data<0>" FAST;
|
| 352 |
|
|
NET "ram_data<1>" FAST;
|
| 353 |
|
|
NET "ram_data<2>" FAST;
|
| 354 |
|
|
NET "ram_data<3>" FAST;
|
| 355 |
|
|
NET "ram_data<4>" FAST;
|
| 356 |
|
|
NET "ram_data<5>" FAST;
|
| 357 |
|
|
NET "ram_data<6>" FAST;
|
| 358 |
|
|
NET "ram_data<7>" FAST;
|
| 359 |
|
|
NET "ram_data<8>" FAST;
|
| 360 |
|
|
NET "ram_data<9>" FAST;
|
| 361 |
|
|
NET "ram_data<10>" FAST;
|
| 362 |
|
|
NET "ram_data<11>" FAST;
|
| 363 |
|
|
NET "ram_data<12>" FAST;
|
| 364 |
|
|
NET "ram_data<13>" FAST;
|
| 365 |
|
|
NET "ram_data<14>" FAST;
|
| 366 |
|
|
NET "ram_data<15>" FAST;
|
