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davidgb |
--=============================================================================--
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-- --
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-- System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
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-- --
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--=============================================================================--
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--
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-- File name : System09_BurchED_B3.vhd
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--
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-- Purpose : This is the top level file for a 6809 instruction compatible system on a chip
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-- It has been designed for the BurchED B3 Spartan2+ FPGA board
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-- using the Xilinx XC2S200 Spartan 2 FPGA and Xilinx ISE 7.1 software.
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-- It has been implemented with the BurchED B3 FPGA board,
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-- modified B3-SRAM module and B3-FPGA-CPU-IO module.
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-- It also supports an IDE CF card interface using a CF to IDE interface adapter.
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-- It uses a monochrome version of the VDU due to limitted Block RAM of XC2S200
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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--
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-- Uses :
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-- clk_div (..\Spartan2\clk_div.vhd) System Clock Divider
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-- cpu09 (..\VHDL\cpu09.vhd) CPU core
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-- B3_SRAM (..\VHDL\B3_SRAM.vhd) BurchED B3 SRAM module interface
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-- acia6850 (..\VHDL\acia6850.vhd) RS232 Serial Interface
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-- ACIA_Clock (..\VHDL\ACIA_Clock.vhd) ACIA Baud Rate Clock Divider
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-- keyboard (..\VHDL\keyboard.vhd) PS/2 Keyboard register interface
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-- ps2_keyboard (..\VHDL\ps2_keyboard.vhd) PS/2 Keyboard interface logic
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-- keymap_rom (..\Spartan2\keymap_rom_b4.vhd) PS/2 Keyboard key code look up table
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-- vdu8_mono (..\VHDL\vdu8_mono.vhd) 80 x 25 Monochrome Visual Display Unit.
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-- char_rom (..\Spartan2\char_rom2k_b4.vhd) Character Generator ROM
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-- ram_2k (..\Spartan2\ram2k_b4.vhd) Text buffer RAM
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-- timer (..\VHDL\timer.vhd) Timer module
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-- trap (..\VHDL\trap.vhd) Bus Trap interrupt
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-- spp (..\VHDL\spp.vhd) Simple Parallel Port
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-- peripheral_bus (..\VHDL\peripheral_bus.vhd) 16 bit IDE Peripheral Bus interface
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-- sys09bug_F800 (..\Spartan2\sys09b3s_b4.vhd) Sysbug09 Monitor ROM
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-- dat_ram (..\VHDL\datram.vhd) Dynamic Address Translation (DAT)
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--
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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-- Memory Map :
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--
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-- $0000 - $DFFF System RAM (256K Mapped via DAT)
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-- $E000 - ACIA (SWTPc)
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-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
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-- $E020 - Keyboard
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-- $E030 - VDU
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-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
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-- $E050 - Timer
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-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
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-- $E070 - Reserved for Trace Buffer
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-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
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-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
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-- $E0A0 - SPP Printer Port
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-- $E0B0 - Reserved
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-- $E0C0 - Reserved
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-- $E100 - $E13F IDE / Compact Flash Card
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-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
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-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
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-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
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-- $E200 - $EFFF Dual Port RAM interface
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-- $F000 - $F7FF Reserved SWTPc DMAF-2
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-- $F800 - $FFFF Sys09bug ROM (Read only)
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-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
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--
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--
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-- Revision History:
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--
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--===========================================================================--
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-- Version 0.1 - 20 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.4 - 29 June 2003
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--
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-- Version 0.5 - 19 July 2003
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-- prints out "Hello World"
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--
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-- Version 0.6 - 5 September 2003
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-- Runs SBUG
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--
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-- Version 1.0- 6 Sep 2003 - John Kent
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-- Inverted SysClk
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-- Initial release to Open Cores
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--
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-- Version 1.1 - 17 Jan 2004 - John Kent
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-- Updated miniUart.
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--
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-- Version 1.2 - 25 Jan 2004 - John Kent
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-- removed signals "test_alu" and "test_cc"
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-- Trap hardware re-instated.
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--
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-- Version 1.3 - 11 Feb 2004 - John Kent
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-- Designed forked off to produce System09_VDU
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-- Added VDU component
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-- VDU runs at 25MHz and divides the clock by 2 for the CPU
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-- UART Runs at 57.6 Kbps
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--
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-- Version 1.4 - 21 Nov 2004 - John Kent
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-- Changes to make compatible with Spartan3 starter kit version
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-- Designed to run with a 50MHz clock input.
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-- the VDU divides 50 MHz to generate a
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-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
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-- Changed Monitor ROM signals to make it look like
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-- a standard 2K memory block
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-- Re-assigned I/O port assignments so it is possible to run KBUG9
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--
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-- Version 1.5 - 3rd February 2007 - John Kent
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-- Changed VDU8 to use external clock divider
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-- renamed miniUART to ACIA_6850
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-- Memory decoding of ROM & IO now uses DAT
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--
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-- Version 1.6 - 7th Februaury 2007 - John Kent
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-- Made ACIA Clock generator an external component
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-- Added Generics to VDU and Keyboard
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-- Changed decoding
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--
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-- Version 1.7 - 20th May 2007 - John Kent
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-- Added 4 wait states to CF access
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-- Removed DAT memory map control of ROM & IO
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-- to allow for full use of RAM as a RAM disk.
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-- Mapped in all 16 bits of the CF data bus.
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--
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-- Version 1.8 - 1st July 2007 - John Kent
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-- Copied B5-X300 top level to B3 version.
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--
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-- Version 2.0 - 6th September 2008 - John Kent
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-- added IDE interface for a CF card.
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-- Used separate Clock DLL for generating clocks
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--
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-- Version 2.1 - 23rd Februaury 2008 - John Kent
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-- Renamed Monitor ROM
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--
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-- Version 2.2 - 28th August 2010 - John Kent
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-- Renamed ACIA_6850 to acia6850
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-- Updated CPU & VDU component signal names & generics
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-- Made peripheral bus interface a separate component
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-- Made BED_SRAM a separate component
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-- Made the LED flasher a separate component
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-- Updated Header
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--
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--===========================================================================
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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entity System09 is
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port(
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clk_in : in Std_Logic; -- System Clock input
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rst_n : in Std_logic; -- Master Reset input (active low)
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LED : out Std_logic; -- Diagnostic LED Flasher
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-- B3-SRAM Memory Interface signals
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ram_csn : out Std_Logic;
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ram_wrln : out Std_Logic;
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ram_wrun : out Std_Logic;
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ram_addr : out Std_Logic_Vector(16 downto 0);
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ram_data : inout Std_Logic_Vector(15 downto 0);
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-- End of B3-SRAM Memory Interface signals
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-- B3-FPGA-CPU-IO Module signals
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-- Asychronous Communications Interface Adapater signals (RS232 Serial Port) ($E00X)
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acia_rxd : in Std_Logic;
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acia_txd : out Std_Logic;
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acia_rts_n : out Std_Logic;
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acia_cts_n : in Std_Logic;
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-- PS/2 Keyboard Interface ($E02X)
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kb_clock : inout Std_logic;
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kb_data : inout Std_Logic;
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-- PS/2 Mouse interface
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-- mouse_clock : in Std_Logic;
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-- mouse_data : in Std_Logic;
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-- Visual Display Unit output signals ($E03X)
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vga_vsync : out Std_Logic;
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vga_hsync : out Std_Logic;
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vga_blue : out std_logic_vector(1 downto 0);
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vga_green : out std_logic_vector(1 downto 0);
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vga_red : out std_logic_vector(1 downto 0);
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-- Buzzer
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-- buzzer : out std_logic;
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-- End of B3-FPGA-CPU-IO Module signals
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-- Parallel Printer Port ($E0AX)
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pp_data : out std_logic_vector(7 downto 0);
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pp_stat : in std_logic_vector(7 downto 3);
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pp_ctrl : out std_logic_vector(3 downto 0);
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-- Peripheral Bus ($E100 - $E1FF)
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pb_iord_n : out std_logic;
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pb_iowr_n : out std_logic;
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pb_addr : out std_logic_vector(2 downto 0);
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pb_data : inout std_logic_vector(15 downto 0);
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-- IDE Compact Flash ($E100 - $E13F)
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ide_rst_n : out std_logic; -- ide pin 1
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ide_cs0_n : out std_logic; -- ide pin 37
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ide_cs1_n : out std_logic; -- ide pin 38
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ide_dmarq : in std_logic; -- ide pin 21
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ide_dmack_n : out std_logic; -- ide pin 29
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ide_iordy : in std_logic; -- ide pin 27
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ide_con_csel : out std_logic; -- ide pin 28
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ide_intrq : in std_logic; -- ide pin 31
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ide_iocs16_n : in std_logic; -- ide pin 32
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ide_pdiag_n : in std_logic; -- ide pin 34
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ide_dasp_n : out std_logic; -- ide pin 39
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-- Dual port RAM interface bus
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bus_clk : in std_logic;
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bus_cs_n : in std_logic;
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bus_rw : in std_logic;
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bus_addr : in std_logic_vector(12 downto 0);
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bus_data_in : in std_logic_vector(7 downto 0);
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bus_data_out : out std_logic_vector(7 downto 0)
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);
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end System09;
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-------------------------------------------------------------------------------
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architecture rtl of System09 is
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-----------------------------------------------------------------------------
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-- constants
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-----------------------------------------------------------------------------
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constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
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constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
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constant CPU_CLK_FREQ : integer := 12500000; -- CPU Clock
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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-- System Clock
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signal sys_clk : std_logic;
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-- CPU Interface signals
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signal cpu_rst : Std_Logic;
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signal cpu_clk : Std_Logic;
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signal cpu_rw : std_logic;
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signal cpu_vma : std_logic;
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signal cpu_halt : std_logic;
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signal cpu_hold : std_logic;
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signal cpu_firq : std_logic;
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signal cpu_irq : std_logic;
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signal cpu_nmi : std_logic;
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_data_in : std_logic_vector(7 downto 0);
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signal cpu_data_out : std_logic_vector(7 downto 0);
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-- B3 Static RAM ($0000 - $DFFF)
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signal ram_cs : std_logic; -- memory chip select
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signal ram_data_out : std_logic_vector(7 downto 0);
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-- ACIA Console serial port ($E000 - $E00F)
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signal acia_data_out : Std_Logic_Vector(7 downto 0);
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signal acia_cs : Std_Logic;
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signal acia_irq : Std_Logic;
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signal acia_clk : Std_Logic;
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-- PS/2 Keyboard interface ($E02X)
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signal kbd_data_out : std_logic_vector(7 downto 0);
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signal kbd_cs : std_logic;
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signal kbd_irq : std_logic;
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-- Visual Display Unit ($E03X)
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signal vga_clk : std_logic;
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signal vdu_cs : std_logic;
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signal vdu_data_out : std_logic_vector(7 downto 0);
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signal vga_red_o : std_logic;
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signal vga_green_o : std_logic;
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signal vga_blue_o : std_logic;
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-- Timer ($E05X)
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signal timer_data_out : std_logic_vector(7 downto 0);
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signal timer_cs : std_logic;
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signal timer_irq : std_logic;
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-- Bus trap ($E06X)
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signal trap_cs : std_logic;
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signal trap_data_out : std_logic_vector(7 downto 0);
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signal trap_irq : std_logic;
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-- Trace ($E07X)
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-- signal trace_cs : std_logic;
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-- signal trace_data_out : std_logic_vector(7 downto 0);
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-- signal trace_irq : std_logic;
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-- Simple Parallel I/O port ($E0AX)
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signal spp_data_out : std_logic_vector(7 downto 0);
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signal spp_cs : std_logic;
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-- Peripheral Bus ($E1XX)
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|
signal pb_cs : std_logic;
|
327 |
|
|
signal pb_data_out : std_logic_vector(7 downto 0);
|
328 |
|
|
signal pb_hold : std_logic;
|
329 |
|
|
|
330 |
|
|
-- Peripheral Bus Chip Selects ($E1XX)
|
331 |
|
|
signal ide_cs : std_logic; -- IDE CF interface ($E100 - $E13F)
|
332 |
|
|
signal ether_cs : std_logic; -- Ethernet interface ($E140 - $E17F)
|
333 |
|
|
signal slot1_cs : std_logic; -- Expansion slot1 ($E180 - $E1BF)
|
334 |
|
|
signal slot2_cs : std_logic; -- Expansion slot 2 ($E1C0 - $E1FF)
|
335 |
|
|
|
336 |
|
|
-- Dual Port RAM for Bus Interfacing ($E200 - $E7FF)
|
337 |
|
|
signal dpr_data_out : std_logic_vector(7 downto 0);
|
338 |
|
|
signal dpr_cs : std_logic;
|
339 |
|
|
signal dpr_wr : std_logic;
|
340 |
|
|
|
341 |
|
|
-- External Bus Interface
|
342 |
|
|
signal bus_iclk : std_logic;
|
343 |
|
|
signal bus_gclk : std_logic;
|
344 |
|
|
signal bus_cs : std_logic;
|
345 |
|
|
signal bus_wr : std_logic;
|
346 |
|
|
|
347 |
|
|
-- Monitor ROM ($F800 - $FFFF)
|
348 |
|
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
349 |
|
|
signal rom_cs : std_logic;
|
350 |
|
|
|
351 |
|
|
-- Dynamic Address Translation ($FFF0 - $FFFF)
|
352 |
|
|
signal dat_cs : std_logic;
|
353 |
|
|
signal dat_addr : std_logic_vector(7 downto 0);
|
354 |
|
|
|
355 |
|
|
-----------------------------------------------------------------
|
356 |
|
|
--
|
357 |
|
|
-- Clock generator
|
358 |
|
|
--
|
359 |
|
|
-----------------------------------------------------------------
|
360 |
|
|
|
361 |
|
|
component clock_div
|
362 |
|
|
port(
|
363 |
|
|
clk_in : in std_Logic; -- System Clock input
|
364 |
|
|
sys_clk : out std_logic; -- System Clock Out (1/1)
|
365 |
|
|
vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2)
|
366 |
|
|
cpu_clk : out std_logic -- CPU Clock Out (1/4)
|
367 |
|
|
);
|
368 |
|
|
end component;
|
369 |
|
|
|
370 |
|
|
-----------------------------------------------------------------
|
371 |
|
|
--
|
372 |
|
|
-- LED Flasher
|
373 |
|
|
--
|
374 |
|
|
-----------------------------------------------------------------
|
375 |
19 |
dilbert57 |
|
376 |
107 |
davidgb |
component flasher
|
377 |
19 |
dilbert57 |
port (
|
378 |
107 |
davidgb |
clk : in std_logic; -- Clock input
|
379 |
|
|
rst : in std_logic; -- Reset input (active high)
|
380 |
|
|
LED : out Std_Logic -- LED output
|
381 |
19 |
dilbert57 |
);
|
382 |
107 |
davidgb |
end component;
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
-----------------------------------------------------------------
|
386 |
|
|
--
|
387 |
|
|
-- 6809 Compatible CPU core
|
388 |
|
|
--
|
389 |
|
|
-----------------------------------------------------------------
|
390 |
|
|
|
391 |
|
|
component cpu09
|
392 |
|
|
port (
|
393 |
|
|
clk : in std_logic;
|
394 |
|
|
rst : in std_logic;
|
395 |
|
|
rw : out std_logic;
|
396 |
|
|
vma : out std_logic;
|
397 |
|
|
addr : out std_logic_vector(15 downto 0);
|
398 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
399 |
|
|
data_out : out std_logic_vector(7 downto 0);
|
400 |
|
|
halt : in std_logic;
|
401 |
|
|
hold : in std_logic;
|
402 |
|
|
irq : in std_logic;
|
403 |
|
|
nmi : in std_logic;
|
404 |
|
|
firq : in std_logic
|
405 |
|
|
);
|
406 |
|
|
end component;
|
407 |
19 |
dilbert57 |
|
408 |
107 |
davidgb |
-----------------------------------------------------------------
|
409 |
|
|
--
|
410 |
|
|
-- Dynamic Address Translation Registers ($FFF0 - $FFFF)
|
411 |
|
|
--
|
412 |
|
|
-----------------------------------------------------------------
|
413 |
|
|
component dat_ram
|
414 |
|
|
port (
|
415 |
|
|
clk : in std_logic;
|
416 |
|
|
rst : in std_logic;
|
417 |
|
|
cs : in std_logic;
|
418 |
|
|
rw : in std_logic;
|
419 |
|
|
addr_lo : in std_logic_vector(3 downto 0);
|
420 |
|
|
addr_hi : in std_logic_vector(3 downto 0);
|
421 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
422 |
|
|
data_out : out std_logic_vector(7 downto 0)
|
423 |
|
|
);
|
424 |
|
|
end component;
|
425 |
|
|
|
426 |
|
|
-------------------------------------------------
|
427 |
|
|
--
|
428 |
|
|
-- Sys09Bug Block RAM Monitor ROM ($F800-$FFFF)
|
429 |
|
|
--
|
430 |
|
|
-------------------------------------------------
|
431 |
|
|
component sys09bug_F800
|
432 |
|
|
port (
|
433 |
|
|
clk : in std_logic;
|
434 |
|
|
rst : in std_logic;
|
435 |
|
|
cs : in std_logic;
|
436 |
|
|
addr : in std_logic_vector (10 downto 0);
|
437 |
|
|
rw : in std_logic;
|
438 |
|
|
data_in : in std_logic_vector (7 downto 0);
|
439 |
|
|
data_out : out std_logic_vector (7 downto 0)
|
440 |
|
|
);
|
441 |
|
|
end component;
|
442 |
|
|
|
443 |
|
|
-----------------------------------------------------------------
|
444 |
|
|
--
|
445 |
|
|
-- 6850 ACIA RS232 Interface ($E000 - $E00F)
|
446 |
|
|
--
|
447 |
|
|
-----------------------------------------------------------------
|
448 |
|
|
|
449 |
|
|
component acia6850
|
450 |
|
|
port (
|
451 |
|
|
clk : in Std_Logic; -- System Clock
|
452 |
|
|
rst : in Std_Logic; -- Reset input (active high)
|
453 |
|
|
cs : in Std_Logic; -- miniUART Chip Select
|
454 |
|
|
rw : in Std_Logic; -- Read / Not Write
|
455 |
|
|
irq : out Std_Logic; -- Interrupt
|
456 |
|
|
addr : in Std_Logic; -- Register Select
|
457 |
|
|
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
458 |
|
|
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
459 |
|
|
RxC : in Std_Logic; -- Receive Baud Clock
|
460 |
|
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
461 |
|
|
RxD : in Std_Logic; -- Receive Data
|
462 |
|
|
TxD : out Std_Logic; -- Transmit Data
|
463 |
|
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
464 |
|
|
CTS_n : in Std_Logic; -- Clear To Send
|
465 |
|
|
RTS_n : out Std_Logic ); -- Request To send
|
466 |
|
|
end component;
|
467 |
|
|
|
468 |
|
|
-----------------------------------------------------------------
|
469 |
|
|
--
|
470 |
|
|
-- ACIA Clock divider
|
471 |
|
|
--
|
472 |
|
|
-----------------------------------------------------------------
|
473 |
|
|
|
474 |
|
|
component ACIA_Clock
|
475 |
|
|
generic (
|
476 |
|
|
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
|
477 |
|
|
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
|
478 |
|
|
);
|
479 |
|
|
port (
|
480 |
|
|
clk : in Std_Logic; -- System Clock Input
|
481 |
|
|
acia_clk : out Std_logic -- ACIA Clock output
|
482 |
|
|
);
|
483 |
|
|
end component;
|
484 |
|
|
|
485 |
|
|
----------------------------------------
|
486 |
|
|
--
|
487 |
|
|
-- PS/2 Keyboard ($E020 - $E02F)
|
488 |
|
|
--
|
489 |
|
|
----------------------------------------
|
490 |
|
|
|
491 |
|
|
component keyboard
|
492 |
|
|
generic(
|
493 |
|
|
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
|
494 |
|
|
);
|
495 |
|
|
port (
|
496 |
|
|
clk : in std_logic;
|
497 |
|
|
rst : in std_logic;
|
498 |
|
|
cs : in std_logic;
|
499 |
|
|
rw : in std_logic;
|
500 |
|
|
addr : in std_logic;
|
501 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
502 |
|
|
data_out : out std_logic_vector(7 downto 0);
|
503 |
|
|
irq : out std_logic;
|
504 |
|
|
kbd_clk : inout std_logic;
|
505 |
|
|
kbd_data : inout std_logic
|
506 |
|
|
);
|
507 |
|
|
end component;
|
508 |
|
|
|
509 |
|
|
----------------------------------------
|
510 |
|
|
--
|
511 |
|
|
-- Video Display Unit. ($E030 - $E03F)
|
512 |
|
|
--
|
513 |
|
|
----------------------------------------
|
514 |
|
|
component vdu8_mono
|
515 |
|
|
generic(
|
516 |
|
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
|
517 |
|
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
|
518 |
|
|
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
|
519 |
|
|
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
|
520 |
|
|
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
|
521 |
|
|
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
|
522 |
|
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
|
523 |
|
|
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
|
524 |
|
|
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
|
525 |
|
|
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
|
526 |
|
|
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
|
527 |
|
|
);
|
528 |
|
|
port(
|
529 |
|
|
-- control register interface
|
530 |
|
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
531 |
|
|
vdu_rst : in std_logic;
|
532 |
|
|
vdu_cs : in std_logic;
|
533 |
|
|
vdu_addr : in std_logic_vector(2 downto 0);
|
534 |
|
|
vdu_rw : in std_logic;
|
535 |
|
|
vdu_data_in : in std_logic_vector(7 downto 0);
|
536 |
|
|
vdu_data_out : out std_logic_vector(7 downto 0);
|
537 |
|
|
|
538 |
|
|
-- vga port connections
|
539 |
|
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
540 |
|
|
vga_red_o : out std_logic;
|
541 |
|
|
vga_green_o : out std_logic;
|
542 |
|
|
vga_blue_o : out std_logic;
|
543 |
|
|
vga_hsync_o : out std_logic;
|
544 |
|
|
vga_vsync_o : out std_logic
|
545 |
|
|
);
|
546 |
|
|
end component;
|
547 |
|
|
|
548 |
|
|
----------------------------------------
|
549 |
|
|
--
|
550 |
|
|
-- Timer module ($E050 - $E05F)
|
551 |
|
|
--
|
552 |
|
|
----------------------------------------
|
553 |
|
|
|
554 |
|
|
component timer
|
555 |
|
|
port (
|
556 |
|
|
clk : in std_logic;
|
557 |
|
|
rst : in std_logic;
|
558 |
|
|
cs : in std_logic;
|
559 |
|
|
addr : in std_logic;
|
560 |
|
|
rw : in std_logic;
|
561 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
562 |
|
|
data_out : out std_logic_vector(7 downto 0);
|
563 |
|
|
irq : out std_logic
|
564 |
|
|
);
|
565 |
|
|
end component;
|
566 |
|
|
|
567 |
|
|
------------------------------------------------------------
|
568 |
|
|
--
|
569 |
|
|
-- Bus Trap / Hardware Breakpoint ($E060 - $E06F)
|
570 |
|
|
--
|
571 |
|
|
------------------------------------------------------------
|
572 |
|
|
|
573 |
|
|
component trap
|
574 |
|
|
port (
|
575 |
|
|
clk : in std_logic;
|
576 |
|
|
rst : in std_logic;
|
577 |
|
|
cs : in std_logic;
|
578 |
|
|
rw : in std_logic;
|
579 |
|
|
vma : in std_logic;
|
580 |
|
|
addr : in std_logic_vector(15 downto 0);
|
581 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
582 |
|
|
data_out : out std_logic_vector(7 downto 0);
|
583 |
|
|
irq : out std_logic
|
584 |
|
|
);
|
585 |
|
|
end component;
|
586 |
|
|
|
587 |
|
|
------------------------------------------------------------
|
588 |
|
|
--
|
589 |
|
|
-- Bus Trace logic ($E070 - $E07F)
|
590 |
|
|
--
|
591 |
|
|
------------------------------------------------------------
|
592 |
|
|
--component trace is
|
593 |
|
|
-- port (
|
594 |
|
|
-- clk : in std_logic;
|
595 |
|
|
-- rst : in std_logic;
|
596 |
|
|
-- rs : in std_logic; -- register select
|
597 |
|
|
-- bs : in std_logic; -- bank select
|
598 |
|
|
-- rw : in std_logic;
|
599 |
|
|
-- vma : in std_logic;
|
600 |
|
|
-- addr : in std_logic_vector(15 downto 0);
|
601 |
|
|
-- data_in : in std_logic_vector(7 downto 0);
|
602 |
|
|
-- reg_data_out : out std_logic_vector(7 downto 0);
|
603 |
|
|
-- buff_data_out : out std_logic_vector(7 downto 0);
|
604 |
|
|
-- cpu_data_in : in std_logic_vector(7 downto 0);
|
605 |
|
|
-- irq : out std_logic
|
606 |
|
|
-- );
|
607 |
|
|
--end component;
|
608 |
|
|
|
609 |
|
|
----------------------------------------
|
610 |
|
|
--
|
611 |
|
|
-- Simple Parallel Port ($E0A0 - $E0AF)
|
612 |
|
|
--
|
613 |
|
|
----------------------------------------
|
614 |
|
|
component spp
|
615 |
|
|
port (
|
616 |
|
|
clk : in std_logic;
|
617 |
|
|
rst : in std_logic;
|
618 |
|
|
cs : in std_logic;
|
619 |
|
|
addr : in std_logic_vector(2 downto 0);
|
620 |
|
|
rw : in std_logic;
|
621 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
622 |
|
|
data_out : out std_logic_vector(7 downto 0);
|
623 |
|
|
irq : out std_logic;
|
624 |
|
|
hold : out std_logic;
|
625 |
|
|
spp_data : out std_logic_vector(7 downto 0);
|
626 |
|
|
spp_stat : in std_logic_vector(7 downto 3);
|
627 |
|
|
spp_ctrl : out std_logic_vector(3 downto 0)
|
628 |
|
|
);
|
629 |
|
|
end component;
|
630 |
|
|
|
631 |
|
|
------------------------------------------------------------
|
632 |
|
|
--
|
633 |
|
|
-- Peripheral Bus interface (IDE CF) ($E100 - $E1FF)
|
634 |
|
|
--
|
635 |
|
|
------------------------------------------------------------
|
636 |
19 |
dilbert57 |
|
637 |
107 |
davidgb |
component peripheral_bus is
|
638 |
19 |
dilbert57 |
port (
|
639 |
107 |
davidgb |
--
|
640 |
|
|
-- CPU Interface signals
|
641 |
|
|
--
|
642 |
|
|
clk : in std_logic; -- System Clock
|
643 |
|
|
rst : in std_logic; -- Reset input (active high)
|
644 |
|
|
cs : in std_logic; -- Peripheral Bus Chip Select
|
645 |
|
|
addr : in std_logic_vector(7 downto 0); -- Register Select
|
646 |
|
|
rw : in std_logic; -- Read / Not Write
|
647 |
|
|
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
|
648 |
|
|
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
|
649 |
|
|
hold : out std_logic; -- Hold bus cycle output
|
650 |
|
|
--
|
651 |
|
|
-- Peripheral Bus Interface Signals
|
652 |
|
|
-- IO + ($00 - $FF)
|
653 |
|
|
-- (for compatibility with XSA-3S1000 / XST 3.0)
|
654 |
|
|
--
|
655 |
|
|
pb_rd_n : out std_logic; -- ide pin 25
|
656 |
|
|
pb_wr_n : out std_logic; -- ide pin 23
|
657 |
|
|
pb_addr : out std_logic_vector( 4 downto 0);
|
658 |
|
|
pb_data : inout std_logic_vector(15 downto 0);
|
659 |
|
|
|
660 |
|
|
-- Peripheral chip selects on Peripheral Bus
|
661 |
|
|
ide_cs : out std_logic; -- IDE / CF interface ($00 - $3F)
|
662 |
|
|
eth_cs : out std_logic; -- Ethernet interface ($40 - $7F)
|
663 |
|
|
sl1_cs : out std_logic; -- Expansion slot 1 ($80 - $BF)
|
664 |
|
|
sl2_cs : out std_logic -- Expansion slot 2 ($C0 - $FF)
|
665 |
|
|
);
|
666 |
|
|
end component;
|
667 |
|
|
|
668 |
|
|
------------------------------------------------------------
|
669 |
|
|
--
|
670 |
|
|
-- External Bus interface Dual port RAM ($E200 - $EFFF)
|
671 |
|
|
--
|
672 |
|
|
------------------------------------------------------------
|
673 |
|
|
|
674 |
|
|
component RAMB4_S8_S8
|
675 |
|
|
port (
|
676 |
|
|
RSTA: IN std_logic;
|
677 |
|
|
CLKA: IN std_logic;
|
678 |
|
|
ENA: IN std_logic;
|
679 |
|
|
WEA: IN std_logic;
|
680 |
|
|
ADDRA: IN std_logic_vector(8 downto 0);
|
681 |
|
|
DIA: IN std_logic_vector(7 downto 0);
|
682 |
|
|
DOA: OUT std_logic_vector(7 downto 0);
|
683 |
|
|
RSTB: IN std_logic;
|
684 |
|
|
CLKB: IN std_logic;
|
685 |
|
|
ENB: IN std_logic;
|
686 |
|
|
WEB: IN std_logic;
|
687 |
|
|
ADDRB: IN std_logic_vector(8 downto 0);
|
688 |
|
|
DIB: IN std_logic_vector(7 downto 0);
|
689 |
|
|
DOB: OUT std_logic_vector(7 downto 0)
|
690 |
|
|
);
|
691 |
|
|
end component;
|
692 |
|
|
|
693 |
|
|
component IBUF
|
694 |
|
|
port (
|
695 |
|
|
I : IN std_logic;
|
696 |
|
|
O : OUT std_logic
|
697 |
|
|
);
|
698 |
|
|
end component;
|
699 |
|
|
|
700 |
|
|
component BUFG
|
701 |
|
|
port (
|
702 |
|
|
I : IN std_logic;
|
703 |
|
|
O : OUT std_logic
|
704 |
|
|
);
|
705 |
|
|
end component;
|
706 |
|
|
|
707 |
|
|
------------------------------------------------------------
|
708 |
|
|
--
|
709 |
|
|
-- BED SRAM interface ($0000 - $DFFF)
|
710 |
|
|
--
|
711 |
|
|
------------------------------------------------------------
|
712 |
|
|
component BED_SRAM
|
713 |
19 |
dilbert57 |
port (
|
714 |
107 |
davidgb |
--
|
715 |
|
|
-- CPU Interface signals
|
716 |
|
|
--
|
717 |
|
|
clk : in std_logic; -- System Clock (twice the CPU clock)
|
718 |
|
|
rst : in std_logic; -- Reset input (active high)
|
719 |
|
|
cs : in std_logic; -- RAM Chip Select
|
720 |
|
|
addr : in std_logic_vector(17 downto 0); -- RAM address bus
|
721 |
|
|
rw : in std_logic; -- Read / Not Write
|
722 |
|
|
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
|
723 |
|
|
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
|
724 |
|
|
--
|
725 |
|
|
-- B3_SRAM Interface Signals
|
726 |
|
|
--
|
727 |
|
|
ram_csn : out Std_Logic;
|
728 |
|
|
ram_wrln : out Std_Logic;
|
729 |
|
|
ram_wrun : out Std_Logic;
|
730 |
|
|
ram_addr : out Std_Logic_Vector(16 downto 0);
|
731 |
|
|
ram_data : inout Std_Logic_Vector(15 downto 0)
|
732 |
|
|
|
733 |
|
|
);
|
734 |
|
|
end component;
|
735 |
|
|
|
736 |
|
|
begin
|
737 |
|
|
-----------------------------------------------------------------------------
|
738 |
|
|
-- Instantiation of internal components
|
739 |
|
|
-----------------------------------------------------------------------------
|
740 |
|
|
----------------------------------------
|
741 |
|
|
--
|
742 |
|
|
-- Clock generator
|
743 |
|
|
--
|
744 |
|
|
----------------------------------------
|
745 |
|
|
my_clock_div: clock_div port map (
|
746 |
|
|
clk_in => clk_in, -- Clock input
|
747 |
|
|
sys_clk => sys_clk, -- System Clock Out (1/1)
|
748 |
|
|
vga_clk => vga_clk, -- VGA Pixel Clock Out (1/2)
|
749 |
|
|
cpu_clk => cpu_clk -- CPU Clock Out (1/4)
|
750 |
|
|
);
|
751 |
|
|
|
752 |
|
|
-----------------------------------------
|
753 |
|
|
--
|
754 |
|
|
-- LED Flasher
|
755 |
|
|
--
|
756 |
|
|
-----------------------------------------
|
757 |
19 |
dilbert57 |
|
758 |
107 |
davidgb |
my_LED_flasher : flasher port map (
|
759 |
|
|
clk => cpu_clk,
|
760 |
|
|
rst => cpu_rst,
|
761 |
|
|
LED => LED
|
762 |
19 |
dilbert57 |
);
|
763 |
107 |
davidgb |
|
764 |
|
|
----------------------------------------
|
765 |
|
|
--
|
766 |
|
|
-- CPU09 CPU Core
|
767 |
|
|
--
|
768 |
|
|
----------------------------------------
|
769 |
|
|
my_cpu : cpu09 port map (
|
770 |
|
|
clk => cpu_clk,
|
771 |
|
|
rst => cpu_rst,
|
772 |
|
|
rw => cpu_rw,
|
773 |
|
|
vma => cpu_vma,
|
774 |
|
|
addr => cpu_addr(15 downto 0),
|
775 |
|
|
data_in => cpu_data_in,
|
776 |
|
|
data_out => cpu_data_out,
|
777 |
|
|
halt => cpu_halt,
|
778 |
|
|
hold => cpu_hold,
|
779 |
|
|
irq => cpu_irq,
|
780 |
|
|
nmi => cpu_nmi,
|
781 |
|
|
firq => cpu_firq
|
782 |
|
|
);
|
783 |
|
|
|
784 |
|
|
----------------------------------------
|
785 |
|
|
--
|
786 |
|
|
-- Dynamic Address Translation ($FFF0-$FFFF)
|
787 |
|
|
--
|
788 |
|
|
----------------------------------------
|
789 |
|
|
my_dat : dat_ram port map (
|
790 |
|
|
clk => cpu_clk,
|
791 |
|
|
rst => cpu_rst,
|
792 |
|
|
cs => dat_cs,
|
793 |
|
|
rw => cpu_rw,
|
794 |
|
|
addr_hi => cpu_addr(15 downto 12),
|
795 |
|
|
addr_lo => cpu_addr(3 downto 0),
|
796 |
|
|
data_in => cpu_data_out,
|
797 |
|
|
data_out => dat_addr(7 downto 0)
|
798 |
|
|
);
|
799 |
|
|
|
800 |
|
|
----------------------------------------
|
801 |
|
|
--
|
802 |
|
|
-- SYS09BUG Monitor ROM ($F800-$FFFF)
|
803 |
|
|
--
|
804 |
|
|
----------------------------------------
|
805 |
|
|
my_rom : SYS09BUG_F800 port map (
|
806 |
|
|
clk => cpu_clk,
|
807 |
|
|
rst => cpu_rst,
|
808 |
|
|
cs => rom_cs,
|
809 |
|
|
rw => '1',
|
810 |
|
|
addr => cpu_addr(10 downto 0),
|
811 |
|
|
data_in => cpu_data_out,
|
812 |
|
|
data_out => rom_data_out
|
813 |
|
|
);
|
814 |
|
|
|
815 |
|
|
----------------------------------------
|
816 |
|
|
--
|
817 |
|
|
-- ACIA RS232 Serial interface ($E000-$E00F)
|
818 |
|
|
--
|
819 |
|
|
----------------------------------------
|
820 |
|
|
my_ACIA : acia6850 port map (
|
821 |
|
|
--
|
822 |
|
|
-- CPU Interface
|
823 |
|
|
--
|
824 |
|
|
clk => cpu_clk,
|
825 |
|
|
rst => cpu_rst,
|
826 |
|
|
cs => acia_cs,
|
827 |
|
|
rw => cpu_rw,
|
828 |
|
|
irq => acia_irq,
|
829 |
|
|
addr => cpu_addr(0),
|
830 |
|
|
data_in => cpu_data_out,
|
831 |
|
|
data_out => acia_data_out,
|
832 |
|
|
--
|
833 |
|
|
-- RS232 Interface
|
834 |
|
|
--
|
835 |
|
|
RxC => acia_clk,
|
836 |
|
|
TxC => acia_clk,
|
837 |
|
|
RxD => acia_rxd,
|
838 |
|
|
TxD => acia_txd,
|
839 |
|
|
DCD_n => '0',
|
840 |
|
|
CTS_n => acia_cts_n,
|
841 |
|
|
RTS_n => acia_rts_n
|
842 |
|
|
);
|
843 |
|
|
|
844 |
|
|
----------------------------------------
|
845 |
|
|
--
|
846 |
|
|
-- ACIA Baud Clock
|
847 |
|
|
--
|
848 |
|
|
----------------------------------------
|
849 |
|
|
my_ACIA_Clock : ACIA_Clock
|
850 |
|
|
generic map(
|
851 |
|
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
852 |
|
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
853 |
|
|
)
|
854 |
|
|
port map(
|
855 |
|
|
clk => sys_clk,
|
856 |
|
|
acia_clk => acia_clk
|
857 |
|
|
);
|
858 |
|
|
|
859 |
|
|
----------------------------------------
|
860 |
|
|
--
|
861 |
|
|
-- PS/2 Keyboard Interface ($E020-$E02F)
|
862 |
|
|
--
|
863 |
|
|
----------------------------------------
|
864 |
|
|
my_keyboard : keyboard
|
865 |
|
|
generic map (
|
866 |
|
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
867 |
|
|
)
|
868 |
|
|
port map(
|
869 |
|
|
clk => cpu_clk,
|
870 |
|
|
rst => cpu_rst,
|
871 |
|
|
cs => kbd_cs,
|
872 |
|
|
rw => cpu_rw,
|
873 |
|
|
addr => cpu_addr(0),
|
874 |
|
|
data_in => cpu_data_out(7 downto 0),
|
875 |
|
|
data_out => kbd_data_out(7 downto 0),
|
876 |
|
|
irq => kbd_irq,
|
877 |
|
|
kbd_clk => kb_clock,
|
878 |
|
|
kbd_data => kb_data
|
879 |
|
|
);
|
880 |
|
|
|
881 |
|
|
------------------------------------------------
|
882 |
|
|
--
|
883 |
|
|
-- Video Display Unit instantiation ($E030-$E03F)
|
884 |
|
|
--
|
885 |
|
|
-------------------------------------------------
|
886 |
|
|
my_vdu : vdu8_mono
|
887 |
|
|
generic map(
|
888 |
|
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- 25MHZ
|
889 |
|
|
VGA_HOR_CHARS => 80, -- CHARACTERS 25.6us
|
890 |
|
|
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS 0.32us
|
891 |
|
|
VGA_HOR_FRONT_PORCH => 16, -- PIXELS 0.64us
|
892 |
|
|
VGA_HOR_SYNC => 96, -- PIXELS 3.84us
|
893 |
|
|
VGA_HOR_BACK_PORCH => 48, -- PIXELS 1.92us
|
894 |
|
|
VGA_VER_CHARS => 25, -- CHARACTERS 12.8ms
|
895 |
|
|
VGA_VER_CHAR_LINES => 16, -- LINES 0.512ms
|
896 |
|
|
VGA_VER_FRONT_PORCH => 10, -- LINES 0.320ms
|
897 |
|
|
VGA_VER_SYNC => 2, -- LINES 0.064ms
|
898 |
|
|
VGA_VER_BACK_PORCH => 34 -- LINES 1.088ms
|
899 |
|
|
)
|
900 |
|
|
port map(
|
901 |
|
|
|
902 |
|
|
-- CPU Control Registers interface
|
903 |
|
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
904 |
|
|
vdu_rst => cpu_rst,
|
905 |
|
|
vdu_cs => vdu_cs,
|
906 |
|
|
vdu_rw => cpu_rw,
|
907 |
|
|
vdu_addr => cpu_addr(2 downto 0),
|
908 |
|
|
vdu_data_in => cpu_data_out,
|
909 |
|
|
vdu_data_out => vdu_data_out,
|
910 |
|
|
|
911 |
|
|
-- vga port connections
|
912 |
|
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
913 |
|
|
vga_red_o => vga_red_o,
|
914 |
|
|
vga_green_o => vga_green_o,
|
915 |
|
|
vga_blue_o => vga_blue_o,
|
916 |
|
|
vga_hsync_o => vga_hsync,
|
917 |
|
|
vga_vsync_o => vga_vsync
|
918 |
|
|
);
|
919 |
|
|
|
920 |
|
|
----------------------------------------
|
921 |
|
|
--
|
922 |
|
|
-- Timer Module
|
923 |
|
|
--
|
924 |
|
|
----------------------------------------
|
925 |
|
|
my_timer : timer port map (
|
926 |
|
|
clk => cpu_clk,
|
927 |
|
|
rst => cpu_rst,
|
928 |
|
|
cs => timer_cs,
|
929 |
|
|
rw => cpu_rw,
|
930 |
|
|
addr => cpu_addr(0),
|
931 |
|
|
data_in => cpu_data_out,
|
932 |
|
|
data_out => timer_data_out,
|
933 |
|
|
irq => timer_irq
|
934 |
|
|
);
|
935 |
|
|
|
936 |
|
|
----------------------------------------
|
937 |
|
|
--
|
938 |
|
|
-- Bus Trap Interrupt logic
|
939 |
|
|
--
|
940 |
|
|
----------------------------------------
|
941 |
|
|
my_trap : trap port map (
|
942 |
|
|
clk => cpu_clk,
|
943 |
|
|
rst => cpu_rst,
|
944 |
|
|
cs => trap_cs,
|
945 |
|
|
rw => cpu_rw,
|
946 |
|
|
vma => cpu_vma,
|
947 |
|
|
addr => cpu_addr,
|
948 |
|
|
data_in => cpu_data_out,
|
949 |
|
|
data_out => trap_data_out,
|
950 |
|
|
irq => trap_irq
|
951 |
|
|
);
|
952 |
|
|
|
953 |
|
|
----------------------------------------
|
954 |
|
|
--
|
955 |
|
|
-- Bus Trace logic
|
956 |
|
|
--
|
957 |
|
|
----------------------------------------
|
958 |
|
|
--my_trace : trace port map (
|
959 |
|
|
-- clk => sys_clk,
|
960 |
|
|
-- rst => cpu_rst,
|
961 |
|
|
-- rs => trace_cs,
|
962 |
|
|
-- bs => bank_cs,
|
963 |
|
|
-- rw => cpu_rw,
|
964 |
|
|
-- vma => cpu_vma,
|
965 |
|
|
-- addr => cpu_addr,
|
966 |
|
|
-- data_in => cpu_data_out,
|
967 |
|
|
-- reg_data_out => trace_data_out,
|
968 |
|
|
-- buff_data_out => bank_data_out,
|
969 |
|
|
-- cpu_data_in => cpu_data_in,
|
970 |
|
|
-- irq => trace_irq
|
971 |
|
|
-- );
|
972 |
|
|
|
973 |
|
|
----------------------------------------
|
974 |
|
|
--
|
975 |
|
|
-- Simple Parallel Port
|
976 |
|
|
--
|
977 |
|
|
----------------------------------------
|
978 |
|
|
my_spp : spp port map (
|
979 |
|
|
clk => cpu_clk,
|
980 |
|
|
rst => cpu_rst,
|
981 |
|
|
cs => spp_cs,
|
982 |
|
|
rw => cpu_rw,
|
983 |
|
|
addr => cpu_addr(2 downto 0),
|
984 |
|
|
data_in => cpu_data_out,
|
985 |
|
|
data_out => spp_data_out,
|
986 |
|
|
spp_data => pp_data,
|
987 |
|
|
spp_stat => pp_stat,
|
988 |
|
|
spp_ctrl => pp_ctrl,
|
989 |
|
|
hold => open,
|
990 |
|
|
irq => open
|
991 |
|
|
);
|
992 |
19 |
dilbert57 |
|
993 |
107 |
davidgb |
------------------------------------------------
|
994 |
|
|
--
|
995 |
|
|
-- 16 bit Peripheral Bus interface ($E100-$E1FF)
|
996 |
|
|
--
|
997 |
|
|
------------------------------------------------
|
998 |
|
|
my_pb : peripheral_bus port map (
|
999 |
|
|
--
|
1000 |
|
|
-- CPU Interface signals
|
1001 |
|
|
--
|
1002 |
19 |
dilbert57 |
clk => cpu_clk,
|
1003 |
107 |
davidgb |
rst => cpu_rst,
|
1004 |
|
|
cs => pb_cs,
|
1005 |
|
|
addr => cpu_addr(7 downto 0),
|
1006 |
|
|
rw => cpu_rw,
|
1007 |
|
|
data_in => cpu_data_out,
|
1008 |
|
|
data_out => pb_data_out,
|
1009 |
|
|
hold => pb_hold,
|
1010 |
|
|
--
|
1011 |
|
|
-- Peripheral Bus Interface Signals
|
1012 |
|
|
-- IO + ($00 - $FF)
|
1013 |
|
|
--
|
1014 |
|
|
pb_rd_n => pb_iord_n,
|
1015 |
|
|
pb_wr_n => pb_iowr_n,
|
1016 |
|
|
pb_addr(2 downto 0) => pb_addr,
|
1017 |
|
|
pb_addr(4 downto 3) => open,
|
1018 |
|
|
pb_data => pb_data,
|
1019 |
|
|
|
1020 |
|
|
-- Peripheral chip selects on Peripheral Bus
|
1021 |
|
|
ide_cs => ide_cs,
|
1022 |
|
|
eth_cs => ether_cs,
|
1023 |
|
|
sl1_cs => slot1_cs,
|
1024 |
|
|
sl2_cs => slot2_cs
|
1025 |
19 |
dilbert57 |
);
|
1026 |
107 |
davidgb |
|
1027 |
|
|
------------------------------------------------------
|
1028 |
|
|
--
|
1029 |
|
|
-- External Bus interface Dual port RAM ($E200 - $EFFF)
|
1030 |
|
|
--
|
1031 |
|
|
-------------------------------------------------------
|
1032 |
|
|
my_dpr : RAMB4_S8_S8 port map (
|
1033 |
|
|
RSTA => cpu_rst,
|
1034 |
|
|
CLKA => cpu_clk,
|
1035 |
|
|
ENA => dpr_cs,
|
1036 |
|
|
WEA => dpr_wr,
|
1037 |
|
|
ADDRA => cpu_addr(8 downto 0),
|
1038 |
|
|
DIA => cpu_data_out,
|
1039 |
|
|
DOA => dpr_data_out,
|
1040 |
|
|
RSTB => cpu_rst,
|
1041 |
|
|
CLKB => bus_gclk,
|
1042 |
|
|
ENB => bus_cs,
|
1043 |
|
|
WEB => bus_wr,
|
1044 |
|
|
ADDRB => bus_addr(8 downto 0),
|
1045 |
|
|
DIB => bus_data_in,
|
1046 |
|
|
DOB => bus_data_out
|
1047 |
|
|
);
|
1048 |
|
|
|
1049 |
|
|
my_dpr_ibuf : IBUF port map (
|
1050 |
|
|
I => bus_clk,
|
1051 |
|
|
O => bus_iclk
|
1052 |
|
|
);
|
1053 |
|
|
|
1054 |
|
|
my_dpr_bufg : BUFG port map (
|
1055 |
|
|
I => bus_iclk,
|
1056 |
|
|
O => bus_gclk
|
1057 |
|
|
);
|
1058 |
|
|
|
1059 |
|
|
-----------------------------------------------
|
1060 |
|
|
--
|
1061 |
|
|
-- BED SRAM interface (256KBytes) ($0000-$DFFF)
|
1062 |
|
|
--
|
1063 |
|
|
-----------------------------------------------
|
1064 |
|
|
my_bed_sram : BED_SRAM port map (
|
1065 |
|
|
--
|
1066 |
|
|
-- CPU Interface signals
|
1067 |
|
|
--
|
1068 |
|
|
clk => vga_clk, -- VGA Clock (twice the CPU clock)
|
1069 |
|
|
rst => cpu_rst, -- Reset input (active high)
|
1070 |
|
|
cs => ram_cs, -- RAM Chip Select
|
1071 |
|
|
addr(17 downto 12) => dat_addr( 5 downto 0), -- High RAM address goes to the DAT
|
1072 |
|
|
addr(11 downto 0) => cpu_addr(11 downto 0), -- Low RAM address goes to the CPU
|
1073 |
|
|
rw => cpu_rw, -- Read / Not Write
|
1074 |
|
|
data_in => cpu_data_out, -- Data Bus In
|
1075 |
|
|
data_out => ram_data_out, -- Data Bus Out
|
1076 |
|
|
--
|
1077 |
|
|
-- B3_SRAM Interface Signals
|
1078 |
|
|
--
|
1079 |
|
|
ram_csn => ram_csn,
|
1080 |
|
|
ram_wrln => ram_wrln,
|
1081 |
|
|
ram_wrun => ram_wrun,
|
1082 |
|
|
ram_addr => ram_addr,
|
1083 |
|
|
ram_data => ram_data
|
1084 |
19 |
dilbert57 |
);
|
1085 |
107 |
davidgb |
|
1086 |
|
|
----------------------------------------------------------------------
|
1087 |
|
|
--
|
1088 |
|
|
-- Process to decode memory map
|
1089 |
|
|
--
|
1090 |
|
|
----------------------------------------------------------------------
|
1091 |
|
|
|
1092 |
|
|
my_decoder: process( cpu_addr, cpu_rw, cpu_vma,
|
1093 |
|
|
dat_addr,
|
1094 |
|
|
rom_data_out,
|
1095 |
|
|
acia_data_out,
|
1096 |
|
|
kbd_data_out,
|
1097 |
|
|
vdu_data_out,
|
1098 |
|
|
timer_data_out,
|
1099 |
|
|
trap_data_out,
|
1100 |
|
|
spp_data_out,
|
1101 |
|
|
dpr_data_out,
|
1102 |
|
|
pb_data_out,
|
1103 |
|
|
ram_data_out )
|
1104 |
|
|
begin
|
1105 |
|
|
cpu_data_in <= (others=>'0');
|
1106 |
|
|
dat_cs <= '0';
|
1107 |
|
|
rom_cs <= '0';
|
1108 |
|
|
acia_cs <= '0';
|
1109 |
|
|
kbd_cs <= '0';
|
1110 |
|
|
vdu_cs <= '0';
|
1111 |
|
|
timer_cs <= '0';
|
1112 |
|
|
trap_cs <= '0';
|
1113 |
|
|
spp_cs <= '0';
|
1114 |
|
|
dpr_cs <= '0';
|
1115 |
|
|
pb_cs <= '0';
|
1116 |
|
|
ram_cs <= '0';
|
1117 |
|
|
|
1118 |
|
|
if cpu_addr( 15 downto 8 ) = "11111111" then
|
1119 |
|
|
--
|
1120 |
|
|
-- Dynamic Address Translation $FFF0 - $FFFF
|
1121 |
|
|
--
|
1122 |
|
|
cpu_data_in <= rom_data_out;
|
1123 |
|
|
dat_cs <= cpu_vma; -- write DAT
|
1124 |
|
|
rom_cs <= cpu_vma; -- read ROM
|
1125 |
|
|
|
1126 |
|
|
elsif (dat_addr(3 downto 0) = "1111") and (cpu_addr(11) = '1') then -- $XF800 - $XFFFF
|
1127 |
|
|
--
|
1128 |
|
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
1129 |
|
|
--
|
1130 |
|
|
cpu_data_in <= rom_data_out;
|
1131 |
|
|
rom_cs <= cpu_vma;
|
1132 |
|
|
|
1133 |
|
|
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
|
1134 |
|
|
--
|
1135 |
|
|
-- IO Devices $E000 - $E7FF
|
1136 |
|
|
--
|
1137 |
|
|
case cpu_addr(11 downto 8) is
|
1138 |
|
|
|
1139 |
|
|
--
|
1140 |
|
|
-- SWTPC peripherals from $E000 to $E0FF
|
1141 |
|
|
--
|
1142 |
|
|
when "0000" =>
|
1143 |
|
|
case cpu_addr(7 downto 4) is
|
1144 |
|
|
--
|
1145 |
|
|
-- ACIA RS232 Console Port $E000 - $E00F
|
1146 |
|
|
--
|
1147 |
|
|
when "0000" => -- $E000
|
1148 |
|
|
cpu_data_in <= acia_data_out;
|
1149 |
|
|
acia_cs <= cpu_vma;
|
1150 |
|
|
|
1151 |
|
|
--
|
1152 |
|
|
-- Reserved
|
1153 |
|
|
-- Floppy Disk Controller port $E010 - $E01F
|
1154 |
|
|
--
|
1155 |
|
|
when "0001" => -- $E010
|
1156 |
|
|
null;
|
1157 |
|
|
|
1158 |
|
|
--
|
1159 |
|
|
-- Keyboard port $E020 - $E02F
|
1160 |
|
|
--
|
1161 |
|
|
when "0010" => -- $E020
|
1162 |
|
|
cpu_data_in <= kbd_data_out;
|
1163 |
|
|
kbd_cs <= cpu_vma;
|
1164 |
|
|
|
1165 |
|
|
--
|
1166 |
|
|
-- VDU port $E030 - $E03F
|
1167 |
|
|
--
|
1168 |
|
|
when "0011" => -- $E030
|
1169 |
|
|
cpu_data_in <= vdu_data_out;
|
1170 |
|
|
vdu_cs <= cpu_vma;
|
1171 |
|
|
|
1172 |
|
|
--
|
1173 |
|
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
1174 |
|
|
--
|
1175 |
|
|
when "0100" => -- $E040
|
1176 |
|
|
cpu_data_in <= (others=> '0');
|
1177 |
|
|
|
1178 |
|
|
--
|
1179 |
|
|
-- Timer $E050 - $E05F
|
1180 |
|
|
--
|
1181 |
|
|
when "0101" => -- $E050
|
1182 |
|
|
cpu_data_in <= timer_data_out;
|
1183 |
|
|
timer_cs <= cpu_vma;
|
1184 |
|
|
|
1185 |
|
|
--
|
1186 |
|
|
-- Bus Trap Logic $E060 - $E06F
|
1187 |
|
|
--
|
1188 |
|
|
when "0110" => -- $E060
|
1189 |
|
|
cpu_data_in <= trap_data_out;
|
1190 |
|
|
trap_cs <= cpu_vma;
|
1191 |
|
|
|
1192 |
|
|
--
|
1193 |
|
|
-- Bus Trace Logic $E070 - $E07F
|
1194 |
|
|
--
|
1195 |
|
|
-- when "0111" => -- $E070
|
1196 |
|
|
-- cpu_data_in <= trace_data_out;
|
1197 |
|
|
-- trace_cs <= cpu_vma;
|
1198 |
|
|
|
1199 |
|
|
--
|
1200 |
|
|
-- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
|
1201 |
|
|
--
|
1202 |
|
|
when "1000" => -- $E080
|
1203 |
|
|
null;
|
1204 |
|
|
|
1205 |
|
|
--
|
1206 |
|
|
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
|
1207 |
|
|
--
|
1208 |
|
|
|
1209 |
|
|
--
|
1210 |
|
|
-- Simple Parallel Port $E0A0 - $E0AF
|
1211 |
|
|
--
|
1212 |
|
|
when "1010" => -- $E0A0
|
1213 |
|
|
cpu_data_in <= spp_data_out;
|
1214 |
|
|
spp_cs <= cpu_vma;
|
1215 |
|
|
|
1216 |
|
|
--
|
1217 |
|
|
-- Remaining 5 slots reserved for non SWTPc Peripherals
|
1218 |
|
|
--
|
1219 |
|
|
when others => -- $E0B0 to $E0FF
|
1220 |
|
|
cpu_data_in <= (others=> '0');
|
1221 |
|
|
|
1222 |
|
|
end case;
|
1223 |
|
|
--
|
1224 |
|
|
-- XST-3.0 Peripheral Bus goes here
|
1225 |
|
|
-- $E100 to $E1FF
|
1226 |
|
|
-- Four devices
|
1227 |
|
|
-- IDE, Ethernet, Slot1, Slot2
|
1228 |
|
|
--
|
1229 |
|
|
when "0001" =>
|
1230 |
|
|
cpu_data_in <= pb_data_out;
|
1231 |
|
|
pb_cs <= cpu_vma;
|
1232 |
|
|
|
1233 |
|
|
--
|
1234 |
|
|
-- $E200 to $EFFF reserved for future use
|
1235 |
|
|
--
|
1236 |
|
|
when others =>
|
1237 |
|
|
cpu_data_in <= dpr_data_out;
|
1238 |
|
|
dpr_cs <= cpu_vma;
|
1239 |
|
|
|
1240 |
|
|
end case;
|
1241 |
|
|
|
1242 |
|
|
--
|
1243 |
|
|
-- Flex RAM $0C000 - $0DFFF
|
1244 |
|
|
--
|
1245 |
|
|
-- elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
1246 |
|
|
-- cpu_data_in <= flex_data_out;
|
1247 |
|
|
-- flex_cs <= cpu_vma;
|
1248 |
|
|
|
1249 |
|
|
--
|
1250 |
|
|
-- Everything else is RAM
|
1251 |
|
|
--
|
1252 |
|
|
else
|
1253 |
|
|
cpu_data_in <= ram_data_out;
|
1254 |
|
|
ram_cs <= cpu_vma;
|
1255 |
|
|
end if;
|
1256 |
|
|
|
1257 |
|
|
end process;
|
1258 |
|
|
|
1259 |
|
|
--
|
1260 |
|
|
-- IDE drive / CF card signals ($E100 - $E13F)
|
1261 |
|
|
-- Located on peripheral bus
|
1262 |
|
|
--
|
1263 |
|
|
ide_bus: process( cpu_rst, cpu_addr, ide_cs )
|
1264 |
|
|
begin
|
1265 |
|
|
ide_cs0_n <= not( ide_cs ) or cpu_addr(4);
|
1266 |
|
|
ide_cs1_n <= not( ide_cs and cpu_addr(4));
|
1267 |
|
|
ide_dmack_n <= '1';
|
1268 |
|
|
ide_rst_n <= not cpu_rst;
|
1269 |
|
|
ide_con_csel <= '0';
|
1270 |
|
|
ide_dasp_n <= not ide_cs;
|
1271 |
|
|
|
1272 |
|
|
end process;
|
1273 |
|
|
|
1274 |
|
|
--
|
1275 |
|
|
-- Assign CPU interface signals
|
1276 |
|
|
--
|
1277 |
|
|
cpu_controls : process( rst_n, pb_hold,
|
1278 |
|
|
acia_irq, kbd_irq, trap_irq, timer_irq )
|
1279 |
|
|
begin
|
1280 |
|
|
cpu_rst <= not rst_n; -- CPU reset is active high
|
1281 |
|
|
cpu_irq <= acia_irq or kbd_irq;
|
1282 |
|
|
cpu_nmi <= trap_irq;
|
1283 |
|
|
cpu_firq <= timer_irq;
|
1284 |
|
|
cpu_halt <= '0';
|
1285 |
|
|
cpu_hold <= pb_hold;
|
1286 |
|
|
end process;
|
1287 |
|
|
|
1288 |
|
|
--
|
1289 |
|
|
-- Assign DPR bus interface signals
|
1290 |
|
|
--
|
1291 |
|
|
my_dpr_bus : process( bus_cs_n, bus_rw, cpu_rw )
|
1292 |
|
|
begin
|
1293 |
|
|
bus_cs <= not bus_cs_n;
|
1294 |
|
|
bus_wr <= not bus_rw;
|
1295 |
|
|
dpr_wr <= not cpu_rw;
|
1296 |
|
|
-- trace_data_out <= (others=>'0');
|
1297 |
|
|
end process;
|
1298 |
|
|
|
1299 |
|
|
--
|
1300 |
|
|
-- Assign VDU VGA output signals
|
1301 |
|
|
-- only 8 colours are handled.
|
1302 |
|
|
--
|
1303 |
|
|
my_vga_out: process( vga_red_o, vga_green_o, vga_blue_o )
|
1304 |
|
|
begin
|
1305 |
|
|
vga_red(0) <= vga_red_o;
|
1306 |
|
|
vga_red(1) <= vga_red_o;
|
1307 |
|
|
vga_green(0) <= vga_green_o;
|
1308 |
|
|
vga_green(1) <= vga_green_o;
|
1309 |
|
|
vga_blue(0) <= vga_blue_o;
|
1310 |
|
|
vga_blue(1) <= vga_blue_o;
|
1311 |
|
|
end process;
|
1312 |
|
|
|
1313 |
|
|
end rtl; --===================== End of architecture =======================--
|