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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B3/] [System09_BurchED_B3.vhd] - Blame information for rev 86

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1 19 dilbert57
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC2S200 Spartan 2+ FPGA.
12
--                  Implemented With BurchED B3 FPGA board,
13
--                  B3-SRAM module and B3-FPGA-CPU-IO module
14
--
15
-- Dependencies   : ieee.Std_Logic_1164
16
--                  ieee.std_logic_unsigned
17
--                  ieee.std_logic_arith
18
--                  ieee.numeric_std
19
--
20
-- Uses           : 
21
--                  cpu09      (cpu09.vhd)      CPU core
22
--                  mon_rom    (sys09bug_rom2k_b4.vhd) Monitor ROM
23
--                  dat_ram    (datram.vhd)     Dynamic Address Translation
24
--                  acia_6850  (ACIA_6850.vhd) ACIA / MiniUART
25
--                             (ACIA_RX.vhd)
26
--                             (ACIA_TX.vhd)
27
--                  ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
28
--                  keyboard   (keyboard.vhd)   PS/2 Keyboard Interface
29
--                  vdu8       (vdu8.vhd)       80 x 25 Video Display
30
--                  timer      (timer.vhd)      Timer module
31
--                  trap            (trap.vhd)       Bus Trap interrupt
32
--                  ioport     (ioport.vhd)     Parallel I/O port.
33
-- 
34
-- Author         : John E. Kent      
35
--                  dilbert57@opencores.org
36
-- Memory Map     :
37
--
38
-- $E000 - ACIA (SWTPc)
39
-- $E010 - Reserved for FD1771 FDC (SWTPc)
40
-- $E020 - Keyboard
41
-- $E030 - VDU
42
-- $E040 - Compact Flash
43
-- $E050 - Timer
44
-- $E060 - Bus trap
45
-- $E070 - Parallel I/O
46
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
47
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
48
-- $E0A0
49
-- $E0B0
50
-- $E0C0 - Trace logic
51
--
52
--===========================================================================----
53
--
54
-- Revision History:
55
--===========================================================================--
56
-- Version 0.1 - 20 March 2003
57
-- Version 0.2 - 30 March 2003
58
-- Version 0.3 - 29 April 2003
59
-- Version 0.4 - 29 June 2003
60
--
61
-- Version 0.5 - 19 July 2003
62
-- prints out "Hello World"
63
--
64
-- Version 0.6 - 5 September 2003
65
-- Runs SBUG
66
--
67
-- Version 1.0- 6 Sep 2003 - John Kent
68
-- Inverted SysClk
69
-- Initial release to Open Cores
70
--
71
-- Version 1.1 - 17 Jan 2004 - John Kent
72
-- Updated miniUart.
73
--
74
-- Version 1.2 - 25 Jan 2004 - John Kent
75
-- removed signals "test_alu" and "test_cc" 
76
-- Trap hardware re-instated.
77
--
78
-- Version 1.3 - 11 Feb 2004 - John Kent
79
-- Designed forked off to produce System09_VDU
80
-- Added VDU component
81
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
82
-- UART Runs at 57.6 Kbps
83
--
84
-- Version 1.4 - 21 Nov 2004 - John Kent
85
-- Changes to make compatible with Spartan3 starter kit version
86
-- Designed to run with a 50MHz clock input.
87
-- the VDU divides 50 MHz to generate a 
88
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
89
-- Changed Monitor ROM signals to make it look like
90
-- a standard 2K memory block
91
-- Re-assigned I/O port assignments so it is possible to run KBUG9
92
-- $E000 - ACIA
93
-- $E010 - Keyboard
94
-- $E020 - VDU
95
-- $E030 - Compact Flash
96
-- $E040 - Timer
97
-- $E050 - Bus trap
98
-- $E060 - Parallel I/O
99
--
100
-- Version 1.5 - 3rd February 2007 - John Kent
101
-- Changed VDU8 to use external clock divider
102
-- renamed miniUART to ACIA_6850
103
-- Memory decoding of ROM & IO now uses DAT
104
--
105
-- Version 1.6 - 7th Februaury 2007 - John Kent
106
-- Made ACIA Clock generator an external component
107
-- Added Generics to VDU and Keyboard
108
-- Changed decoding
109
--
110
-- Version 1.7 - 20th May 2007 - John Kent
111
-- Added 4 wait states to CF access
112
-- Removed DAT memory map control of ROM & IO
113
-- to allow for full use of RAM as a RAM disk.
114
-- Mapped in all 16 bits of the CF data bus.
115
--
116
-- Version 1.8 - 1st July 2007 - John Kent
117
-- Copied B5-X300 top level to B3 version.
118
-- 
119
--===========================================================================
120
--
121
library ieee;
122
   use ieee.std_logic_1164.all;
123
   use IEEE.STD_LOGIC_ARITH.ALL;
124
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
125
   use ieee.numeric_std.all;
126
library unisim;
127
        use unisim.vcomponents.all;
128
 
129
entity System09 is
130
  port(
131
    SysClk      : in  Std_Logic;  -- System Clock input
132
         Reset_n     : in  Std_logic;  -- Master Reset input (active low)
133
    LED         : out std_logic;  -- Diagnostic LED Flasher
134
 
135
    -- Memory Interface signals
136
    ram_csn     : out Std_Logic;
137
    ram_wrln    : out Std_Logic;
138
    ram_wrun    : out Std_Logic;
139
    ram_addr    : out Std_Logic_Vector(16 downto 0);
140
    ram_data    : inout Std_Logic_Vector(15 downto 0);
141
 
142
         -- Stuff on the peripheral board
143
 
144
         -- PS/2 Keyboard
145
         kb_clock    : inout Std_logic;
146
         kb_data     : inout Std_Logic;
147
 
148
         -- PS/2 Mouse interface
149
--       mouse_clock : in  Std_Logic;
150
--       mouse_data  : in  Std_Logic;
151
 
152
         -- Uart Interface
153
    rxbit       : in  Std_Logic;
154
         txbit       : out Std_Logic;
155
    rts_n       : out Std_Logic;
156
    cts_n       : in  Std_Logic;
157
 
158
         -- CRTC output signals
159
         v_drive     : out Std_Logic;
160
    h_drive     : out Std_Logic;
161
    blue_lo     : out std_logic;
162
    blue_hi     : out std_logic;
163
    green_lo    : out std_logic;
164
    green_hi    : out std_logic;
165
    red_lo      : out std_logic;
166
    red_hi      : out std_logic;
167
--         buzzer      : out std_logic;
168
 
169
-- Compact Flash
170
--    cf_rst_n     : out std_logic;
171
--    cf_cs0_n     : out std_logic;
172
--    cf_cs1_n     : out std_logic;
173
--    cf_rd_n      : out std_logic;
174
--    cf_wr_n      : out std_logic;
175
--    cf_cs16_n    : out std_logic;
176
--    cf_a         : out std_logic_vector(2 downto 0);
177
--    cf_d         : inout std_logic_vector(15 downto 0);
178
--    cf_d         : inout std_logic_vector(7 downto 0);
179
 
180
-- Parallel I/O port
181
    porta        : inout std_logic_vector(7 downto 0);
182
    portb        : inout std_logic_vector(7 downto 0);
183
 
184
-- CPU bus
185
         bus_clk      : out std_logic;
186
         bus_reset    : out std_logic;
187
         bus_rw       : out std_logic;
188
         bus_csn      : out std_logic;
189
    bus_addr     : out std_logic_vector(19 downto 0);
190
         bus_data     : inout std_logic_vector(7 downto 0);
191
 
192
-- timer
193
    timer_out    : out std_logic
194
         );
195
end System09;
196
 
197
-------------------------------------------------------------------------------
198
-- Architecture for System09
199
-------------------------------------------------------------------------------
200
architecture rtl of System09 is
201
  -----------------------------------------------------------------------------
202
  -- constants
203
  -----------------------------------------------------------------------------
204
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
205
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
206
  constant CPU_Clock_Frequency  : integer := 12500000;  -- CPU Clock
207
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
208
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
209
 
210
  type hold_state_type is ( hold_release_state, hold_request_state );
211
 
212
  -----------------------------------------------------------------------------
213
  -- Signals
214
  -----------------------------------------------------------------------------
215
  -- Monitor ROM
216
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
217
  signal rom_cs        : std_logic;
218
 
219
  -- UART Interface signals
220
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
221
  signal uart_cs       : Std_Logic;
222
  signal uart_irq      : Std_Logic;
223
  signal uart_clk       : Std_Logic;
224
  signal DCD_n         : Std_Logic;
225
 
226
  -- timer
227
  signal timer_data_out : std_logic_vector(7 downto 0);
228
  signal timer_cs    : std_logic;
229
  signal timer_irq   : std_logic;
230
 
231
  -- trap
232
  signal trap_cs         : std_logic;
233
  signal trap_data_out   : std_logic_vector(7 downto 0);
234
  signal trap_irq        : std_logic;
235
 
236
 
237
  -- trace
238
--  signal trace_cs          : std_logic;
239
--  signal trace_data_out    : std_logic_vector(7 downto 0);
240
--  signal trace_irq         : std_logic;
241
--  signal bank_cs           : std_logic;
242
--  signal bank_data_out     : std_logic_vector(7 downto 0);
243
 
244
  -- Parallel I/O port
245
  signal ioport_data_out : std_logic_vector(7 downto 0);
246
  signal ioport_cs    : std_logic;
247
 
248
  -- compact flash port
249
--  signal cf_data_out : std_logic_vector(7 downto 0);
250
--  signal cf_cs       : std_logic;
251
--  signal cf_rd       : std_logic;
252
--  signal cf_wr       : std_logic;
253
--  signal cf_hold     : std_logic;
254
--  signal cf_release  : std_logic;
255
--  signal cf_count    : std_logic_vector(3 downto 0);
256
--  signal cf_hold_state : hold_state_type;
257
 
258
  -- keyboard port
259
  signal keyboard_data_out : std_logic_vector(7 downto 0);
260
  signal keyboard_cs       : std_logic;
261
  signal keyboard_irq      : std_logic;
262
 
263
  -- RAM
264
  signal ram_cs      : std_logic; -- memory chip select
265
  signal ram_wrl     : std_logic; -- memory write lower
266
  signal ram_wru     : std_logic; -- memory write upper
267
  signal ram_data_out    : std_logic_vector(7 downto 0);
268
 
269
  -- CPU Interface signals
270
  signal cpu_reset    : Std_Logic;
271
  signal cpu_clk      : Std_Logic;
272
  signal cpu_rw       : std_logic;
273
  signal cpu_vma      : std_logic;
274
  signal cpu_halt     : std_logic;
275
  signal cpu_hold     : std_logic;
276
  signal cpu_firq     : std_logic;
277
  signal cpu_irq      : std_logic;
278
  signal cpu_nmi      : std_logic;
279
  signal cpu_addr     : std_logic_vector(15 downto 0);
280
  signal cpu_data_in  : std_logic_vector(7 downto 0);
281
  signal cpu_data_out : std_logic_vector(7 downto 0);
282
 
283
  -- Dynamic address translation
284
  signal dat_cs       : std_logic;
285
  signal dat_addr     : std_logic_vector(7 downto 0);
286
 
287
  -- Video Display Unit
288
  signal pix_clk      : std_logic;
289
  signal vdu_cs       : std_logic;
290
  signal vdu_data_out : std_logic_vector(7 downto 0);
291
  signal vga_red      : std_logic;
292
  signal vga_green    : std_logic;
293
  signal vga_blue     : std_logic;
294
 
295
  -- external bus I/O
296
  signal bus_cs       : std_logic;
297
 
298
  -- Flashing Led test signals
299
  signal countL       : std_logic_vector(23 downto 0);
300
  signal clock_div    : std_logic_vector(1 downto 0);
301
 
302
-----------------------------------------------------------------
303
--
304
-- CPU09 CPU core
305
--
306
-----------------------------------------------------------------
307
 
308
component cpu09
309
  port (
310
         clk:        in std_logic;
311
    rst:      in        std_logic;
312
    rw:      out        std_logic;              -- Asynchronous memory interface
313
    vma:             out        std_logic;
314
    address:  out       std_logic_vector(15 downto 0);
315
    data_in:  in        std_logic_vector(7 downto 0);
316
         data_out: out std_logic_vector(7 downto 0);
317
         halt:     in  std_logic;
318
         hold:     in  std_logic;
319
         irq:      in  std_logic;
320
         nmi:      in  std_logic;
321
         firq:     in  std_logic
322
  );
323
end component;
324
 
325
 
326
----------------------------------------
327
--
328
-- SBUG Block RAM Monitor ROM
329
--
330
----------------------------------------
331
component mon_rom
332
    port (
333
       clk   : in  std_logic;
334
       rst   : in  std_logic;
335
       cs    : in  std_logic;
336
       rw    : in  std_logic;
337
       addr  : in  std_logic_vector (10 downto 0);
338
       wdata : in  std_logic_vector (7 downto 0);
339
       rdata : out std_logic_vector (7 downto 0)
340
    );
341
end component;
342
 
343
 
344
----------------------------------------
345
--
346
-- Dynamic Address Translation Registers
347
--
348
----------------------------------------
349
component dat_ram
350
  port (
351
    clk:      in  std_logic;
352
         rst:      in  std_logic;
353
         cs:       in  std_logic;
354
         rw:       in  std_logic;
355
         addr_lo:  in  std_logic_vector(3 downto 0);
356
         addr_hi:  in  std_logic_vector(3 downto 0);
357
    data_in:  in  std_logic_vector(7 downto 0);
358
         data_out: out std_logic_vector(7 downto 0)
359
         );
360
end component;
361
 
362
-----------------------------------------------------------------
363
--
364
-- 6850 ACIA/UART
365
--
366
-----------------------------------------------------------------
367
 
368
component ACIA_6850
369
  port (
370
     clk      : in  Std_Logic;  -- System Clock
371
     rst      : in  Std_Logic;  -- Reset input (active high)
372
     cs       : in  Std_Logic;  -- miniUART Chip Select
373
     rw       : in  Std_Logic;  -- Read / Not Write
374
     irq      : out Std_Logic;  -- Interrupt
375
     Addr     : in  Std_Logic;  -- Register Select
376
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
377
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
378
     RxC      : in  Std_Logic;  -- Receive Baud Clock
379
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
380
     RxD      : in  Std_Logic;  -- Receive Data
381
     TxD      : out Std_Logic;  -- Transmit Data
382
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
383
     CTS_n    : in  Std_Logic;  -- Clear To Send
384
     RTS_n    : out Std_Logic );  -- Request To send
385
end component;
386
 
387
-----------------------------------------------------------------
388
--
389
-- ACIA Clock divider
390
--
391
-----------------------------------------------------------------
392
 
393
component ACIA_Clock
394
  generic (
395
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
396
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
397
  );
398
  port (
399
     clk      : in  Std_Logic;  -- System Clock Input
400
          ACIA_clk : out Std_logic   -- ACIA Clock output
401
  );
402
end component;
403
 
404
----------------------------------------
405
--
406
-- Timer module
407
--
408
----------------------------------------
409
 
410
component timer
411
  port (
412
     clk       : in std_logic;
413
     rst       : in std_logic;
414
     cs        : in std_logic;
415
     rw        : in std_logic;
416
     addr      : in std_logic;
417
     data_in   : in std_logic_vector(7 downto 0);
418
          data_out  : out std_logic_vector(7 downto 0);
419
          irq       : out std_logic;
420
     timer_in  : in std_logic;
421
          timer_out : out std_logic
422
          );
423
end component;
424
 
425
------------------------------------------------------------
426
--
427
-- Bus Trap logic
428
--
429
------------------------------------------------------------
430
 
431
component trap
432
        port (
433
         clk        : in  std_logic;
434
    rst        : in  std_logic;
435
    cs         : in  std_logic;
436
    rw         : in  std_logic;
437
    vma        : in  std_logic;
438
    addr       : in  std_logic_vector(15 downto 0);
439
    data_in    : in  std_logic_vector(7 downto 0);
440
         data_out   : out std_logic_vector(7 downto 0);
441
         irq        : out std_logic
442
  );
443
end component;
444
 
445
------------------------------------------------------------
446
--
447
-- Bus Trace logic
448
--
449
------------------------------------------------------------
450
--component trace is
451
--  port (      
452
--    clk           : in  std_logic;
453
--    rst           : in  std_logic;
454
--    rs            : in  std_logic;      -- register select
455
--    bs            : in  std_logic;      -- bank select
456
--    rw            : in  std_logic;
457
--    vma           : in  std_logic;
458
--    addr          : in  std_logic_vector(15 downto 0);
459
--    data_in       : in  std_logic_vector(7 downto 0);
460
--    reg_data_out  : out std_logic_vector(7 downto 0);
461
--    buff_data_out : out std_logic_vector(7 downto 0);
462
--    cpu_data_in   : in  std_logic_vector(7 downto 0);
463
--    irq           : out std_logic
464
--  );
465
--end component;
466
 
467
----------------------------------------
468
--
469
-- Dual 8 bit Parallel I/O module
470
--
471
----------------------------------------
472
component ioport
473
        port (
474
         clk       : in  std_logic;
475
    rst       : in  std_logic;
476
    cs        : in  std_logic;
477
    rw        : in  std_logic;
478
    addr      : in  std_logic_vector(1 downto 0);
479
    data_in   : in  std_logic_vector(7 downto 0);
480
         data_out  : out std_logic_vector(7 downto 0);
481
         porta_io  : inout std_logic_vector(7 downto 0);
482
         portb_io  : inout std_logic_vector(7 downto 0)
483
         );
484
end component;
485
 
486
----------------------------------------
487
--
488
-- PS/2 Keyboard
489
--
490
----------------------------------------
491
 
492
component keyboard
493
  generic(
494
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
495
  );
496
  port(
497
  clk             : in    std_logic;
498
  rst             : in    std_logic;
499
  cs              : in    std_logic;
500
  rw              : in    std_logic;
501
  addr            : in    std_logic;
502
  data_in         : in    std_logic_vector(7 downto 0);
503
  data_out        : out   std_logic_vector(7 downto 0);
504
  irq             : out   std_logic;
505
  kbd_clk         : inout std_logic;
506
  kbd_data        : inout std_logic
507
  );
508
end component;
509
 
510
----------------------------------------
511
--
512
-- Video Display Unit.
513
--
514
----------------------------------------
515
component vdu8_mono
516
      generic(
517
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
518
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
519
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
520
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
521
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
522
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
523
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
524
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
525
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
526
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
527
             VGA_VER_SYNC           : integer := 1;  -- LINES
528
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
529
      );
530
      port(
531
                -- control register interface
532
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
533
      vdu_rst      : in  std_logic;
534
                vdu_cs       : in  std_logic;
535
                vdu_rw       : in  std_logic;
536
                vdu_addr     : in  std_logic_vector(2 downto 0);
537
      vdu_data_in  : in  std_logic_vector(7 downto 0);
538
      vdu_data_out : out std_logic_vector(7 downto 0);
539
 
540
      -- vga port connections
541
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
542
      vga_red_o    : out std_logic;
543
      vga_green_o  : out std_logic;
544
      vga_blue_o   : out std_logic;
545
      vga_hsync_o  : out std_logic;
546
      vga_vsync_o  : out std_logic
547
   );
548
end component;
549
 
550
 
551
component BUFG
552
  port (
553
                i: in  std_logic;
554
                o: out std_logic
555
  );
556
end component;
557
 
558
begin
559
  -----------------------------------------------------------------------------
560
  -- Instantiation of internal components
561
  -----------------------------------------------------------------------------
562
 
563
----------------------------------------
564
--
565
-- CPU09 CPU Core
566
--
567
----------------------------------------
568
my_cpu : cpu09  port map (
569
         clk         => cpu_clk,
570
    rst       => cpu_reset,
571
    rw       => cpu_rw,
572
    vma       => cpu_vma,
573
    address   => cpu_addr(15 downto 0),
574
    data_in   => cpu_data_in,
575
         data_out  => cpu_data_out,
576
         halt      => cpu_halt,
577
         hold      => cpu_hold,
578
         irq       => cpu_irq,
579
         nmi       => cpu_nmi,
580
         firq      => cpu_firq
581
  );
582
 
583
----------------------------------------
584
--
585
-- SBUG / KBUG / SYS09BUG Monitor ROM
586
--
587
----------------------------------------
588
my_rom : mon_rom port map (
589
       clk   => cpu_clk,
590
                 rst   => cpu_reset,
591
                 cs    => rom_cs,
592
                 rw    => '1',
593
       addr  => cpu_addr(10 downto 0),
594
                 wdata => cpu_data_out,
595
       rdata => rom_data_out
596
    );
597
 
598
----------------------------------------
599
--
600
-- Dynamic Address Translation Registers
601
--
602
----------------------------------------
603
my_dat : dat_ram port map (
604
    clk        => cpu_clk,
605
         rst        => cpu_reset,
606
         cs         => dat_cs,
607
         rw         => cpu_rw,
608
         addr_hi    => cpu_addr(15 downto 12),
609
         addr_lo    => cpu_addr(3 downto 0),
610
    data_in    => cpu_data_out,
611
         data_out   => dat_addr(7 downto 0)
612
         );
613
 
614
----------------------------------------
615
--
616
-- ACIA/UART Serial interface
617
--
618
----------------------------------------
619
my_ACIA  : ACIA_6850 port map (
620
         clk         => cpu_clk,
621
         rst       => cpu_reset,
622
    cs        => uart_cs,
623
         rw        => cpu_rw,
624
    irq       => uart_irq,
625
    Addr      => cpu_addr(0),
626
         Datain    => cpu_data_out,
627
         DataOut   => uart_data_out,
628
         RxC       => uart_clk,
629
         TxC       => uart_clk,
630
         RxD       => rxbit,
631
         TxD       => txbit,
632
         DCD_n     => dcd_n,
633
         CTS_n     => cts_n,
634
         RTS_n     => rts_n
635
         );
636
 
637
----------------------------------------
638
--
639
-- ACIA Clock
640
--
641
----------------------------------------
642
my_ACIA_Clock : ACIA_Clock
643
  generic map(
644
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
645
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
646
  )
647
  port map(
648
    clk        => SysClk,
649
    acia_clk   => uart_clk
650
  );
651
 
652
----------------------------------------
653
--
654
-- PS/2 Keyboard Interface
655
--
656
----------------------------------------
657
my_keyboard : keyboard
658
   generic map (
659
        KBD_Clock_Frequency => CPU_Clock_frequency
660
        )
661
   port map(
662
        clk          => cpu_clk,
663
        rst          => cpu_reset,
664
        cs           => keyboard_cs,
665
        rw           => cpu_rw,
666
        addr         => cpu_addr(0),
667
        data_in      => cpu_data_out(7 downto 0),
668
        data_out     => keyboard_data_out(7 downto 0),
669
        irq          => keyboard_irq,
670
        kbd_clk      => kb_clock,
671
        kbd_data     => kb_data
672
        );
673
 
674
----------------------------------------
675
--
676
-- Video Display Unit instantiation
677
--
678
----------------------------------------
679
my_vdu : vdu8_mono
680
  generic map(
681
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
682
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
683
           VGA_HOR_CHARS          => 80, -- CHARACTERS
684
           VGA_VER_CHARS          => 25, -- CHARACTERS
685
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
686
           VGA_LINES_PER_CHAR     => 16, -- LINES
687
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
688
           VGA_HOR_SYNC           => 96, -- PIXELS
689
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
690
           VGA_VER_BACK_PORCH     => 13, -- LINES
691
           VGA_VER_SYNC           => 1,  -- LINES
692
           VGA_VER_FRONT_PORCH    => 36  -- LINES
693
  )
694
  port map(
695
 
696
                -- Control Registers
697
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
698
      vdu_rst       => cpu_reset,
699
                vdu_cs        => vdu_cs,
700
                vdu_rw        => cpu_rw,
701
                vdu_addr      => cpu_addr(2 downto 0),
702
                vdu_data_in   => cpu_data_out,
703
                vdu_data_out  => vdu_data_out,
704
 
705
      -- vga port connections
706
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
707
      vga_red_o     => vga_red,
708
      vga_green_o   => vga_green,
709
      vga_blue_o    => vga_blue,
710
      vga_hsync_o   => h_drive,
711
      vga_vsync_o   => v_drive
712
   );
713
 
714
----------------------------------------
715
--
716
-- Timer Module
717
--
718
----------------------------------------
719
my_timer  : timer port map (
720
    clk       => cpu_clk,
721
         rst       => cpu_reset,
722
    cs        => timer_cs,
723
         rw        => cpu_rw,
724
    addr      => cpu_addr(0),
725
         data_in   => cpu_data_out,
726
         data_out  => timer_data_out,
727
    irq       => timer_irq,
728
         timer_in  => CountL(5),
729
         timer_out => timer_out
730
    );
731
 
732
----------------------------------------
733
--
734
-- Bus Trap Interrupt logic
735
--
736
----------------------------------------
737
my_trap : trap port map (
738
    clk        => cpu_clk,
739
    rst        => cpu_reset,
740
    cs         => trap_cs,
741
    rw         => cpu_rw,
742
    vma        => cpu_vma,
743
    addr       => cpu_addr,
744
    data_in    => cpu_data_out,
745
    data_out   => trap_data_out,
746
    irq        => trap_irq
747
    );
748
 
749
----------------------------------------
750
--
751
-- Bus Trace logic
752
--
753
----------------------------------------
754
--my_trace : trace port map (   
755
--    clk           => SysClk,
756
--    rst           => cpu_reset,
757
--    rs            => trace_cs,
758
--    bs            => bank_cs,
759
--    rw            => cpu_rw,
760
--    vma           => cpu_vma,
761
--    addr          => cpu_addr,
762
--    data_in       => cpu_data_out,
763
--    reg_data_out  => trace_data_out,
764
--    buff_data_out => bank_data_out,
765
--    cpu_data_in   => cpu_data_in,
766
--    irq           => trace_irq
767
--    );
768
 
769
 
770
----------------------------------------
771
--
772
-- Parallel I/O Port
773
--
774
----------------------------------------
775
my_ioport  : ioport port map (
776
         clk       => cpu_clk,
777
    rst       => cpu_reset,
778
    cs        => ioport_cs,
779
    rw        => cpu_rw,
780
    addr      => cpu_addr(1 downto 0),
781
    data_in   => cpu_data_out,
782
         data_out  => ioport_data_out,
783
         porta_io  => porta,
784
         portb_io  => portb
785
         );
786
 
787
--
788
-- 12.5 MHz CPU clock
789
--
790
cpu_clk_buffer : BUFG port map(
791
    i => clock_div(1),
792
         o => cpu_clk
793
    );
794
 
795
--
796
-- 25 MHz VGA Pixel clock
797
--
798
vga_clk_buffer : BUFG port map(
799
    i => clock_div(0),
800
         o => pix_clk
801
    );
802
 
803
----------------------------------------------------------------------
804
--
805
-- Process to decode memory map
806
--
807
----------------------------------------------------------------------
808
 
809
mem_decode: process( cpu_clk, Reset_n, dat_addr,
810
                     cpu_addr, cpu_rw, cpu_vma,
811
                                              rom_data_out,
812
                                                        ram_data_out,
813
--                                            cf_data_out,
814
                                                   timer_data_out,
815
                                                        trap_data_out,
816
                                                        ioport_data_out,
817
                                                   uart_data_out,
818
                                                        keyboard_data_out,
819
                                                        vdu_data_out,
820
--                                                      trace_data_out, 
821
                                                        bus_data )
822
variable decode_addr : std_logic_vector(4 downto 0);
823
begin
824
    decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
825
--    decode_addr := cpu_addr(15 downto 11);
826
 
827
    if cpu_addr( 15 downto 8 ) = "11111111" then
828
                        cpu_data_in <= rom_data_out;
829
                        rom_cs      <= cpu_vma;              -- read ROM
830
                        dat_cs      <= cpu_vma;              -- write DAT
831
                        ram_cs      <= '0';
832
                        uart_cs     <= '0';
833
--                      cf_cs       <= '0';
834
                        timer_cs    <= '0';
835
                        trap_cs     <= '0';
836
                        ioport_cs   <= '0';
837
                        keyboard_cs <= '0';
838
                        vdu_cs      <= '0';
839
                        bus_cs      <= '0';
840
--                        trace_cs    <= '0';
841
         else
842
      case decode_addr is
843
           --
844
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
845
                --
846
                when "11111" => -- $F800 - $FFFF
847
                   cpu_data_in <= rom_data_out;
848
                        rom_cs      <= cpu_vma;              -- read ROM
849
                        dat_cs      <= '0';
850
                        ram_cs      <= '0';
851
                        uart_cs     <= '0';
852
--                      cf_cs       <= '0';
853
                        timer_cs    <= '0';
854
                        trap_cs     <= '0';
855
                        ioport_cs   <= '0';
856
                        keyboard_cs <= '0';
857
                        vdu_cs      <= '0';
858
                        bus_cs      <= '0';
859
--                        trace_cs    <= '0';
860
 
861
      --
862
                -- IO Devices $E000 - $E7FF
863
                --
864
                when "11100" => -- $E000 - $E7FF
865
                        rom_cs    <= '0';
866
                   dat_cs    <= '0';
867
                        ram_cs    <= '0';
868
                   case cpu_addr(7 downto 4) is
869
                        --
870
                        -- UART / ACIA $E000
871
                        --
872
                        when "0000" => -- $E000
873
                     cpu_data_in <= uart_data_out;
874
                          uart_cs     <= cpu_vma;
875
--                        cf_cs       <= '0';
876
                          timer_cs    <= '0';
877
                          trap_cs     <= '0';
878
                          ioport_cs   <= '0';
879
                          keyboard_cs <= '0';
880
                          vdu_cs      <= '0';
881
                          bus_cs      <= '0';
882
--                        trace_cs    <= '0';
883
 
884
                        --
885
                        -- WD1771 FDC sites at $E010-$E01F
886
                        --
887
 
888
         --
889
         -- Keyboard port $E020 - $E02F
890
                        --
891
                        when "0010" => -- $E020
892
           cpu_data_in <= keyboard_data_out;
893
                          uart_cs     <= '0';
894
--                        cf_cs       <= '0';
895
           timer_cs    <= '0';
896
                          trap_cs     <= '0';
897
                          ioport_cs   <= '0';
898
                          keyboard_cs <= cpu_vma;
899
                          vdu_cs      <= '0';
900
                          bus_cs      <= '0';
901
--                        trace_cs    <= '0';
902
 
903
         --
904
         -- VDU port $E030 - $E03F
905
                        --
906
                        when "0011" => -- $E030
907
           cpu_data_in <= vdu_data_out;
908
                          uart_cs     <= '0';
909
--                        cf_cs       <= '0';
910
           timer_cs    <= '0';
911
                          trap_cs     <= '0';
912
                          ioport_cs   <= '0';
913
                          keyboard_cs <= '0';
914
                          vdu_cs      <= cpu_vma;
915
                          bus_cs      <= '0';
916
--                        trace_cs    <= '0';
917
 
918
 
919
         --
920
                        -- Compact Flash $E040 - $E04F
921
                        --
922
--                      when "0100" => -- $E040
923
--           cpu_data_in <= cf_data_out;
924
--                        uart_cs     <= '0';
925
--           cf_cs       <= cpu_vma;
926
--                        timer_cs    <= '0';
927
--                        trap_cs     <= '0';
928
--                        ioport_cs   <= '0';
929
--                        keyboard_cs <= '0';
930
--                        vdu_cs      <= '0';
931
--                        bus_cs      <= '0';
932
--                        trace_cs    <= '0';
933
 
934
         --
935
         -- Timer $E050 - $E05F
936
                        --
937
                        when "0101" => -- $E050
938
           cpu_data_in <= timer_data_out;
939
                          uart_cs     <= '0';
940
--                        cf_cs       <= '0';
941
           timer_cs    <= cpu_vma;
942
                          trap_cs     <= '0';
943
                          ioport_cs   <= '0';
944
                          keyboard_cs <= '0';
945
                          vdu_cs      <= '0';
946
                          bus_cs      <= '0';
947
--                        trace_cs    <= '0';
948
 
949
         --
950
         -- Bus Trap Logic $E060 - $E06F
951
                        --
952
--                      when "0110" => -- $E060
953
--         cpu_data_in <= trap_data_out;
954
--                        uart_cs     <= '0';
955
--         cf_cs       <= '0';
956
--         timer_cs    <= '0';
957
--         trap_cs     <= cpu_vma;
958
--         ioport_cs   <= '0';
959
--         keyboard_cs <= '0';
960
--         vdu_cs      <= '0';
961
--         bus_cs      <= '0';
962
--                        trace_cs    <= '0';
963
 
964
         --
965
         -- I/O port $E070 - $E07F
966
                        --
967
                        when "0111" => -- $E070
968
           cpu_data_in <= ioport_data_out;
969
                          uart_cs     <= '0';
970
--                        cf_cs       <= '0';
971
           timer_cs    <= '0';
972
                          trap_cs     <= '0';
973
                          ioport_cs   <= cpu_vma;
974
                          keyboard_cs <= '0';
975
                          vdu_cs      <= '0';
976
                          bus_cs      <= '0';
977
--                        trace_cs    <= '0';
978
 
979
         --
980
         -- Bus Trace Logic $E0C00 - $E0CF
981
                        --
982
--                      when "1100" => -- $E0C0
983
--         cpu_data_in <= trace_data_out;
984
--                        uart_cs     <= '0';
985
--                        keyboard_cs <= '0';
986
--         timer_cs    <= '0';
987
--                        vdu_cs      <= '0';
988
--                        ioport_cs   <= '0';
989
--                        cf_cs       <= '0';
990
--                        trap_cs     <= '0';
991
--                        trace_cs    <= cpu_vma;
992
 
993
 
994
                        when others => -- $E080 to $E7FF
995
           cpu_data_in <= bus_data;
996
                          uart_cs     <= '0';
997
--                        cf_cs       <= '0';
998
                          timer_cs    <= '0';
999
                          trap_cs     <= '0';
1000
                          ioport_cs   <= '0';
1001
                          keyboard_cs <= '0';
1002
                          vdu_cs      <= '0';
1003
                          bus_cs      <= cpu_vma;
1004
--                        trace_cs    <= '0';
1005
                   end case;
1006
                --
1007
                -- Everything else is RAM
1008
                --
1009
                when others =>
1010
                  cpu_data_in <= ram_data_out;
1011
                  rom_cs      <= '0';
1012
                  dat_cs      <= '0';
1013
                  ram_cs      <= cpu_vma;
1014
                  uart_cs     <= '0';
1015
--                cf_cs       <= '0';
1016
                  timer_cs    <= '0';
1017
                  trap_cs     <= '0';
1018
                  ioport_cs   <= '0';
1019
                  keyboard_cs <= '0';
1020
                  vdu_cs      <= '0';
1021
                  bus_cs      <= '0';
1022
--                        trace_cs    <= '0';
1023
                end case;
1024
        end if;
1025
end process;
1026
 
1027
 
1028
--
1029
-- B5-SRAM Control
1030
-- Processes to read and write memory based on bus signals
1031
--
1032
ram_process: process( cpu_clk, Reset_n,
1033
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
1034
                                               dat_addr,
1035
                      ram_cs, ram_wrl, ram_wru, ram_data_out )
1036
begin
1037
    ram_csn <= not( ram_cs and Reset_n );
1038
         ram_wrl  <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
1039
         ram_wrln <= not (ram_wrl);
1040
    ram_wru  <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
1041
         ram_wrun <= not (ram_wru);
1042
         ram_addr(16 downto 11) <= dat_addr(5 downto 0);
1043
         ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
1044
 
1045
    if ram_wrl = '1' then
1046
                ram_data(7 downto 0) <= cpu_data_out;
1047
         else
1048
      ram_data(7 downto 0)  <= "ZZZZZZZZ";
1049
         end if;
1050
 
1051
         if ram_wru = '1' then
1052
                ram_data(15 downto 8) <= cpu_data_out;
1053
         else
1054
      ram_data(15 downto 8)  <= "ZZZZZZZZ";
1055
    end if;
1056
 
1057
         if cpu_addr(0) = '1' then
1058
      ram_data_out <= ram_data(15 downto 8);
1059
         else
1060
      ram_data_out <= ram_data(7 downto 0);
1061
    end if;
1062
end process;
1063
 
1064
--
1065
-- Compact Flash Control
1066
--
1067
--compact_flash: process( Reset_n,
1068
--                 cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
1069
--                                        cf_cs, cf_rd, cf_wr, cf_d )
1070
--begin
1071
--       cf_rst_n  <= Reset_n;
1072
--       cf_cs0_n  <= not( cf_cs ) or cpu_addr(3);
1073
--       cf_cs1_n  <= not( cf_cs and cpu_addr(3));
1074
--       cf_cs16_n <= '1';
1075
--       cf_wr     <= cf_cs and (not cpu_rw);
1076
--       cf_rd     <= cf_cs and cpu_rw;
1077
--       cf_wr_n   <= not cf_wr;
1078
--       cf_rd_n   <= not cf_rd;
1079
--       cf_a      <= cpu_addr(2 downto 0);
1080
--       if cf_wr = '1' then
1081
--         cf_d(7 downto 0) <= cpu_data_out;
1082
--       else
1083
--         cf_d(7 downto 0) <= "ZZZZZZZZ";
1084
--       end if;
1085
--       cf_data_out <= cf_d(7 downto 0);
1086
--       cf_d(15 downto 8) <= "ZZZZZZZZ";
1087
--end process;
1088
 
1089
--
1090
-- Hold CF access       for a few cycles
1091
--
1092
--cf_hold_proc: process( cpu_clk, Reset_n )
1093
--begin
1094
--    if Reset_n = '0' then
1095
--               cf_release    <= '0';
1096
--               cf_count      <= "0000";
1097
--          cf_hold_state <= hold_release_state;
1098
--       elsif cpu_clk'event and cpu_clk='0' then
1099
--          case cf_hold_state is
1100
--               when hold_release_state =>
1101
--          cf_release <= '0';
1102
--                  if cf_cs = '1' then
1103
--                          cf_count      <= "0011";
1104
--                               cf_hold_state <= hold_request_state;
1105
--                       end if;
1106
--
1107
--               when hold_request_state =>
1108
--                  cf_count <= cf_count - "0001";
1109
--                       if cf_count = "0000" then
1110
--             cf_release    <= '1';
1111
--                               cf_hold_state <= hold_release_state;
1112
--                       end if;
1113
--       when others =>
1114
--                  null;
1115
--       end case;
1116
--       end if;
1117
--end process;
1118
 
1119
--
1120
-- Interrupts and other bus control signals
1121
--
1122
interrupts : process( Reset_n,
1123
--                                                       cf_cs, cf_hold, cf_release,
1124
                      uart_irq,
1125
                                                         trap_irq,
1126
                      timer_irq, keyboard_irq
1127
                                                         )
1128
begin
1129
--    cf_hold   <= cf_cs and (not cf_release);
1130
         cpu_reset <= not Reset_n; -- CPU reset is active high
1131
    cpu_irq   <= uart_irq or keyboard_irq;
1132
         cpu_nmi   <= trap_irq;
1133
         cpu_firq  <= timer_irq;
1134
         cpu_halt  <= '0';
1135
--       cpu_hold  <= cf_hold;
1136
         cpu_hold  <= '0';
1137
end process;
1138
 
1139
--
1140
-- CPU bus signals
1141
--
1142
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out, bus_cs )
1143
begin
1144
        bus_clk   <= cpu_clk;
1145
   bus_reset <= cpu_reset;
1146
        bus_rw    <= cpu_rw;
1147
        bus_csn   <= not bus_cs;
1148
   bus_addr  <= dat_addr(7 downto 0) & cpu_addr(11 downto 0);
1149
        if( cpu_rw = '1' ) then
1150
           bus_data <= "ZZZZZZZZ";
1151
   else
1152
           bus_data <= cpu_data_out;
1153
   end if;
1154
end process;
1155
 
1156
  --
1157
  -- flash led to indicate code is working
1158
  --
1159
my_LED_Flasher: process (cpu_clk, CountL )
1160
begin
1161
    if(cpu_clk'event and cpu_clk = '0') then
1162
      countL <= countL + 1;
1163
    end if;
1164
         LED <= countL(23);
1165
         dcd_n <= '0';
1166
end process;
1167
 
1168
--
1169
-- Clock divider
1170
--
1171
my_clock_divider: process( SysClk )
1172
begin
1173
        if SysClk'event and SysClk='0' then
1174
                clock_div <= clock_div + "01";
1175
        end if;
1176
end process;
1177
--
1178
-- Assign VDU VGA colour output
1179
-- only 8 colours are handled.
1180
--
1181
my_vga_out: process( vga_red, vga_green, vga_blue )
1182
begin
1183
           red_lo   <= vga_red;
1184
      red_hi   <= vga_red;
1185
      green_lo <= vga_green;
1186
      green_hi <= vga_green;
1187
      blue_lo  <= vga_blue;
1188
      blue_hi  <= vga_blue;
1189
end process;
1190
 
1191
end rtl; --===================== End of architecture =======================--

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