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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B5-X300/] [System09_BurchED_B5-X300.vhd] - Blame information for rev 159

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Line No. Rev Author Line
1 119 dilbert57
--===========================================================================
2 19 dilbert57
--
3 119 dilbert57
--  System09 - SoC for the BurchED B5-X300 Spartan2 FPGA board.
4 19 dilbert57
--
5 119 dilbert57
--===========================================================================
6 19 dilbert57
--
7 119 dilbert57
-- File name      : System09_BurchED_B5-X300.vhd
8
--
9
-- Entity name    : my_system09
10 19 dilbert57
--
11
-- Purpose        : Top level file for 6809 compatible system on a chip
12
--                  Designed with Xilinx XC2S300e Spartan 2+ FPGA.
13
--                  Implemented With BurchED B5-X300 FPGA board,
14
--                  B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21 119 dilbert57
-- Uses           : clock_div     (../vhdl/clock_div.vhd)       System clock divider
22
--                  flasher       (../vhdl/flasher.vhd)         LED flasher
23
--                  BED_SRAM      (../vhdl/BED_SRAM.vhd)        BurchED SRAM interface
24
--                  cpu09         (../vhdl/cpu09.vhd)           CPU core
25
--                  SYS09BUG_F800 (../spartan2/sys09b5x_b4.vhd) Monitor ROM
26
--                  dat_ram       (../vhdl/datram.vhd)          Dynamic Address Translation
27
--                  acia6850      (../vhdl/acia6850.vhd)        ACIA
28
--                  ACIA_Clock    (../vhdl/ACIA_Clock.vhd)      ACIA Baud Clock Divider
29
--                  keyboard      (../vhdl/keyboard.vhd)        PS/2 Keyboard Interface
30
--                  vdu8          (../vhdl/vdu8.vhd)            80 x 25 Video Display
31
--                  timer         (../vhdl/timer.vhd)           Timer module
32
--                  trap               (../vhdl/trap.vhd)            Bus Trap interrupt
33
--                  ioport        (../vhdl/ioport.vhd)          Parallel I/O port.
34 19 dilbert57
-- 
35
-- Author         : John E. Kent      
36
--                  dilbert57@opencores.org      
37 108 davidgb
-- Memory Map     :
38
--
39
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
40
-- $E000 - ACIA (SWTPc)
41
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
42
-- $E020 - Keyboard
43
-- $E030 - VDU
44
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
45
-- $E050 - Timer
46
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
47 19 dilbert57
-- $E070 - Parallel I/O
48 108 davidgb
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
49
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
50
-- $E0A0 - Reserved SPP Printer Port
51
-- $E0B0 - Reserved
52
-- $E0C0 - Reserved
53
-- $E100 - $E13F IDE / Compact Flash Card
54
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
55
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
56
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
57
-- $E200 - $EFFF Dual Port RAM interface
58
-- $F000 - $F7FF Reserved SWTPc DMAF-2
59
-- $F800 - $FFFF Sys09bug ROM (Read only)
60
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
61 119 dilbert57
--
62
--
63
--  Copyright (C) 2003 - 2010 John Kent
64
--
65
--  This program is free software: you can redistribute it and/or modify
66
--  it under the terms of the GNU General Public License as published by
67
--  the Free Software Foundation, either version 3 of the License, or
68
--  (at your option) any later version.
69
--
70
--  This program is distributed in the hope that it will be useful,
71
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
72
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
73
--  GNU General Public License for more details.
74
--
75
--  You should have received a copy of the GNU General Public License
76
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
77 19 dilbert57
--
78 119 dilbert57
--===========================================================================
79 19 dilbert57
--
80 119 dilbert57
--                             Revision History:
81
--
82
--===========================================================================
83 19 dilbert57
-- Version 0.1 - 20 March 2003
84
-- Version 0.2 - 30 March 2003
85
-- Version 0.3 - 29 April 2003
86
-- Version 0.4 - 29 June 2003
87
--
88
-- Version 0.5 - 19 July 2003
89
-- prints out "Hello World"
90
--
91
-- Version 0.6 - 5 September 2003
92
-- Runs SBUG
93
--
94
-- Version 1.0- 6 Sep 2003 - John Kent
95
-- Inverted SysClk
96
-- Initial release to Open Cores
97
--
98
-- Version 1.1 - 17 Jan 2004 - John Kent
99
-- Updated miniUart.
100
--
101
-- Version 1.2 - 25 Jan 2004 - John Kent
102
-- removed signals "test_alu" and "test_cc" 
103
-- Trap hardware re-instated.
104
--
105
-- Version 1.3 - 11 Feb 2004 - John Kent
106
-- Designed forked off to produce System09_VDU
107
-- Added VDU component
108
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
109
-- UART Runs at 57.6 Kbps
110
--
111
-- Version 1.4 - 21 Nov 2004 - John Kent
112
-- Changes to make compatible with Spartan3 starter kit version
113
-- Designed to run with a 50MHz clock input.
114
-- the VDU divides 50 MHz to generate a 
115
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
116
-- Changed Monitor ROM signals to make it look like
117
-- a standard 2K memory block
118
-- Re-assigned I/O port assignments so it is possible to run KBUG9
119
-- $E000 - ACIA
120
-- $E010 - Keyboard
121
-- $E020 - VDU
122
-- $E030 - Compact Flash
123
-- $E040 - Timer
124
-- $E050 - Bus trap
125
-- $E060 - Parallel I/O
126
--
127
-- Version 1.5 - 3rd February 2007 - John Kent
128
-- Changed VDU8 to use external clock divider
129
-- renamed miniUART to ACIA_6850
130
-- Memory decoding of ROM & IO now uses DAT
131
--
132
-- Version 1.6 - 7th Februaury 2007 - John Kent
133
-- Made ACIA Clock generator an external component
134
-- Added Generics to VDU and Keyboard
135
-- Changed decoding
136
--
137
-- Version 1.7 - 20th May 2007 - John Kent
138
-- Added 4 wait states to CF access
139
-- Removed DAT memory map control of ROM & IO
140
-- to allow for full use of RAM as a RAM disk.
141
-- Mapped in all 16 bits of the CF data bus.
142 108 davidgb
--
143
-- Version 1.8 - 23rd February 2009 - John Kent
144
-- Renamed mon_rom to SYS09BUG_F800
145
--
146
-- Version 1.9 - 5th sepember 2010 - John Kent
147
-- Added Peripheral bus interface
148
-- Made the clock divider an external module
149
-- Rearranged VDU generic signals
150
-- Changed address decoding
151
-- Made the SRAM an external module
152 19 dilbert57
-- 
153
--===========================================================================
154
--
155
library ieee;
156
   use ieee.std_logic_1164.all;
157
   use IEEE.STD_LOGIC_ARITH.ALL;
158
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
159
   use ieee.numeric_std.all;
160
library unisim;
161
        use unisim.vcomponents.all;
162
 
163 119 dilbert57
entity my_system09 is
164 19 dilbert57
  port(
165 108 davidgb
    clk_in      : in  Std_Logic;  -- System Clock input
166
         rst_n       : in  Std_logic;  -- Master Reset input (active low)
167 19 dilbert57
    LED         : out std_logic;  -- Diagnostic LED Flasher
168
 
169
    -- Memory Interface signals
170
    ram_csn     : out Std_Logic;
171
    ram_wrln    : out Std_Logic;
172
    ram_wrun    : out Std_Logic;
173
    ram_addr    : out Std_Logic_Vector(16 downto 0);
174
    ram_data    : inout Std_Logic_Vector(15 downto 0);
175
 
176
         -- Stuff on the peripheral board
177
 
178
         -- PS/2 Keyboard
179
         kb_clock    : inout Std_logic;
180
         kb_data     : inout Std_Logic;
181
 
182
         -- PS/2 Mouse interface
183
--       mouse_clock : in  Std_Logic;
184
--       mouse_data  : in  Std_Logic;
185
 
186
         -- Uart Interface
187
    rxbit       : in  Std_Logic;
188
         txbit       : out Std_Logic;
189
    rts_n       : out Std_Logic;
190
    cts_n       : in  Std_Logic;
191
 
192
         -- CRTC output signals
193
         v_drive     : out Std_Logic;
194
    h_drive     : out Std_Logic;
195
    blue_lo     : out std_logic;
196
    blue_hi     : out std_logic;
197
    green_lo    : out std_logic;
198
    green_hi    : out std_logic;
199
    red_lo      : out std_logic;
200
    red_hi      : out std_logic;
201
--         buzzer      : out std_logic;
202
 
203
-- Compact Flash
204
    cf_rst_n     : out std_logic;
205 22 dilbert57
    cf_cs0_n     : out std_logic;
206
    cf_cs1_n     : out std_logic;
207 19 dilbert57
    cf_rd_n      : out std_logic;
208
    cf_wr_n      : out std_logic;
209
    cf_a         : out std_logic_vector(2 downto 0);
210
    cf_d         : inout std_logic_vector(15 downto 0);
211
 
212
-- Parallel I/O port
213
    porta        : inout std_logic_vector(7 downto 0);
214
    portb        : inout std_logic_vector(7 downto 0);
215
 
216
-- CPU bus
217
         bus_clk      : out std_logic;
218
         bus_reset    : out std_logic;
219
         bus_rw       : out std_logic;
220
         bus_cs       : out std_logic;
221
    bus_addr     : out std_logic_vector(15 downto 0);
222 108 davidgb
         bus_data     : inout std_logic_vector(7 downto 0)
223 19 dilbert57
         );
224 119 dilbert57
end my_system09;
225 19 dilbert57
 
226
-------------------------------------------------------------------------------
227
-- Architecture for System09
228
-------------------------------------------------------------------------------
229 119 dilbert57
architecture rtl of my_system09 is
230 19 dilbert57
  -----------------------------------------------------------------------------
231
  -- constants
232
  -----------------------------------------------------------------------------
233 108 davidgb
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
234
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
235
  constant CPU_CLK_FREQ  : integer := 12500000;  -- CPU Clock
236
  constant BAUD_RATE     : integer := 57600;      -- Baud Rate
237
  constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
238 19 dilbert57
 
239
  type hold_state_type is ( hold_release_state, hold_request_state );
240
 
241
  -----------------------------------------------------------------------------
242
  -- Signals
243
  -----------------------------------------------------------------------------
244 108 davidgb
  -- Clock signals
245
  signal sys_clk       : std_logic;
246
  signal vga_clk       : std_logic;
247
 
248
  -- CPU Interface signals
249
  signal cpu_rst       : Std_Logic;
250
  signal cpu_clk       : Std_Logic;
251
  signal cpu_vma       : std_logic;
252
  signal cpu_addr      : std_logic_vector(15 downto 0);
253
  signal cpu_rw        : std_logic;
254
  signal cpu_data_in   : std_logic_vector(7 downto 0);
255
  signal cpu_data_out  : std_logic_vector(7 downto 0);
256
  signal cpu_firq      : std_logic;
257
  signal cpu_irq       : std_logic;
258
  signal cpu_nmi       : std_logic;
259
  signal cpu_halt      : std_logic;
260
  signal cpu_hold      : std_logic;
261
 
262
  -- Dynamic address translation
263
  signal dat_cs       : std_logic;
264
  signal dat_addr     : std_logic_vector(7 downto 0);
265
 
266 19 dilbert57
  -- Monitor ROM
267
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
268
  signal rom_cs        : std_logic;
269
 
270 108 davidgb
  -- UART/ACIA Interface signals
271 19 dilbert57
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
272
  signal uart_cs       : Std_Logic;
273
  signal uart_irq      : Std_Logic;
274 108 davidgb
  signal uart_clk      : Std_Logic;
275 19 dilbert57
  signal DCD_n         : Std_Logic;
276
 
277 108 davidgb
  -- Keyboard port
278
  signal kbd_data_out  : std_logic_vector(7 downto 0);
279
  signal kbd_cs        : std_logic;
280
  signal kbd_irq       : std_logic;
281
 
282
  -- Video Display Unit
283
  signal vdu_cs        : std_logic;
284
  signal vdu_data_out  : std_logic_vector(7 downto 0);
285
  signal vga_red       : std_logic;
286
  signal vga_green     : std_logic;
287
  signal vga_blue      : std_logic;
288 19 dilbert57
 
289 108 davidgb
  -- Timer
290
  signal tmr_data_out  : std_logic_vector(7 downto 0);
291
  signal tmr_cs        : std_logic;
292
  signal tmr_irq       : std_logic;
293 19 dilbert57
 
294 108 davidgb
  -- Trap Hardware break point
295
  signal trap_cs       : std_logic;
296
  signal trap_data_out : std_logic_vector(7 downto 0);
297
  signal trap_irq      : std_logic;
298
 
299 19 dilbert57
  -- Parallel I/O port
300 108 davidgb
  signal pio_data_out  : std_logic_vector(7 downto 0);
301
  signal pio_cs        : std_logic;
302 19 dilbert57
 
303 108 davidgb
  -- Peripheral bus
304
  signal pb_data_out   : std_logic_vector(7 downto 0);
305
  signal pb_cs         : std_logic;
306
  signal pb_hold       : std_logic;
307
 
308
  -- Compact Flash on peripheral bus
309
  signal cf_cs         : std_logic;
310 19 dilbert57
 
311 108 davidgb
  -- SRAM
312
  signal ram_cs        : std_logic; -- memory chip select
313
  signal ram_data_out  : std_logic_vector(7 downto 0);
314 19 dilbert57
 
315 108 davidgb
-----------------------------------------------------------------
316
--
317
--                     Clock generator
318
--
319
-----------------------------------------------------------------
320
 
321
component clock_div
322
  port(
323
    clk_in      : in  std_Logic;  -- System Clock input
324
         sys_clk     : out std_logic;  -- System Clock Out    (1/1)
325
         vga_clk     : out std_logic;  -- VGA Pixel Clock Out (1/2)
326
    cpu_clk     : out std_logic   -- CPU Clock Out       (1/4)
327
  );
328
end component;
329
 
330
 
331
-----------------------------------------------------------------
332
--
333
--                      LED Flasher
334
--
335
-----------------------------------------------------------------
336 19 dilbert57
 
337 108 davidgb
component flasher
338
  port (
339
    clk      : in  std_logic;           -- Clock input
340
    rst      : in  std_logic;           -- Reset input (active high)
341
    LED      : out Std_Logic            -- LED output        
342
  );
343
end component;
344
 
345
------------------------------------------------------------
346
--
347
--           B5 SRAM interface ($0000 - $DFFF)
348
--
349
------------------------------------------------------------
350
component BED_SRAM
351
  port (
352
    --
353
    -- CPU Interface signals
354
    --
355
    clk       : in  std_logic;                     -- System Clock (twice the CPU clock)
356
    rst       : in  std_logic;                     -- Reset input (active high)
357
    cs        : in  std_logic;                     -- RAM Chip Select
358
    addr      : in  std_logic_vector(17 downto 0); -- RAM address bus
359
    rw        : in  std_logic;                     -- Read / Not Write
360
    data_in   : in  std_logic_vector(7 downto 0);  -- Data Bus In 
361
    data_out  : out std_logic_vector(7 downto 0);  -- Data Bus Out
362
    --
363
    -- BED_SRAM Interface Signals
364
    --
365
    ram_csn   : out   Std_Logic;
366
    ram_wrln  : out   Std_Logic;
367
    ram_wrun  : out   Std_Logic;
368
    ram_addr  : out   Std_Logic_Vector(16 downto 0);
369
    ram_data  : inout Std_Logic_Vector(15 downto 0)
370
 
371
    );
372
end component;
373
 
374 19 dilbert57
 
375
-----------------------------------------------------------------
376
--
377
-- CPU09 CPU core
378
--
379
-----------------------------------------------------------------
380
 
381
component cpu09
382
  port (
383 108 davidgb
         clk      :     in  std_logic;
384
    rst      : in  std_logic;
385
    vma      :  out std_logic;
386
    addr     : out std_logic_vector(15 downto 0);
387
    rw       :  out std_logic;          -- Asynchronous memory interface
388
    data_in  : in  std_logic_vector(7 downto 0);
389
         data_out : out std_logic_vector(7 downto 0);
390
         halt     : in  std_logic;
391
         hold     : in  std_logic;
392
         irq      : in  std_logic;
393
         nmi      : in  std_logic;
394
         firq     : in  std_logic
395 19 dilbert57
  );
396
end component;
397
 
398
----------------------------------------
399
--
400
-- Dynamic Address Translation Registers
401
--
402
----------------------------------------
403
component dat_ram
404
  port (
405
    clk:      in  std_logic;
406
         rst:      in  std_logic;
407
         cs:       in  std_logic;
408
         rw:       in  std_logic;
409
         addr_lo:  in  std_logic_vector(3 downto 0);
410
         addr_hi:  in  std_logic_vector(3 downto 0);
411
    data_in:  in  std_logic_vector(7 downto 0);
412
         data_out: out std_logic_vector(7 downto 0)
413
         );
414
end component;
415
 
416 108 davidgb
----------------------------------------
417
--
418
-- SBUG Block RAM Monitor ROM
419
--
420
----------------------------------------
421
component SYS09BUG_F800
422
    port (
423
       clk      : in  std_logic;
424
       rst      : in  std_logic;
425
       cs       : in  std_logic;
426
       addr     : in  std_logic_vector (10 downto 0);
427
       rw       : in  std_logic;
428
       data_in  : in  std_logic_vector (7 downto 0);
429
       data_out : out std_logic_vector (7 downto 0)
430
    );
431
end component;
432
 
433 19 dilbert57
-----------------------------------------------------------------
434
--
435
-- 6850 ACIA/UART
436
--
437
-----------------------------------------------------------------
438
 
439 108 davidgb
component acia6850
440 19 dilbert57
  port (
441
     clk      : in  Std_Logic;  -- System Clock
442
     rst      : in  Std_Logic;  -- Reset input (active high)
443
     cs       : in  Std_Logic;  -- miniUART Chip Select
444 108 davidgb
     addr     : in  Std_Logic;  -- Register Select
445 19 dilbert57
     rw       : in  Std_Logic;  -- Read / Not Write
446 108 davidgb
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
447
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
448 19 dilbert57
     irq      : out Std_Logic;  -- Interrupt
449
     RxC      : in  Std_Logic;  -- Receive Baud Clock
450
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
451
     RxD      : in  Std_Logic;  -- Receive Data
452
     TxD      : out Std_Logic;  -- Transmit Data
453
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
454
     CTS_n    : in  Std_Logic;  -- Clear To Send
455
     RTS_n    : out Std_Logic );  -- Request To send
456
end component;
457
 
458
-----------------------------------------------------------------
459
--
460
-- ACIA Clock divider
461
--
462
-----------------------------------------------------------------
463
 
464
component ACIA_Clock
465
  generic (
466 108 davidgb
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
467
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
468 19 dilbert57
  );
469
  port (
470
     clk      : in  Std_Logic;  -- System Clock Input
471
          ACIA_clk : out Std_logic   -- ACIA Clock output
472
  );
473
end component;
474 108 davidgb
 
475
----------------------------------------
476
--
477
-- PS/2 Keyboard
478
--
479
----------------------------------------
480 19 dilbert57
 
481 108 davidgb
component keyboard
482
  generic(
483
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
484
  );
485
  port(
486
    clk             : in    std_logic;
487
    rst             : in    std_logic;
488
    cs              : in    std_logic;
489
    rw              : in    std_logic;
490
    addr            : in    std_logic;
491
    data_in         : in    std_logic_vector(7 downto 0);
492
    data_out        : out   std_logic_vector(7 downto 0);
493
    irq             : out   std_logic;
494
    kbd_clk         : inout std_logic;
495
    kbd_data        : inout std_logic
496
  );
497
end component;
498
 
499 19 dilbert57
----------------------------------------
500
--
501 108 davidgb
-- Video Display Unit.
502
--
503
----------------------------------------
504
component vdu8
505
  generic(
506
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- 25MHz
507
         VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
508
         VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
509
         VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
510
         VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
511
         VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
512
         VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
513
         VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
514
         VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
515
         VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
516
         VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
517
  );
518
  port(
519
    -- control register interface
520
    vdu_clk      : in  std_logic;        -- CPU Clock - 12.5MHz
521
    vdu_rst      : in  std_logic;
522
    vdu_cs       : in  std_logic;
523
    vdu_rw       : in  std_logic;
524
    vdu_addr     : in  std_logic_vector(2 downto 0);
525
    vdu_data_in  : in  std_logic_vector(7 downto 0);
526
    vdu_data_out : out std_logic_vector(7 downto 0);
527
 
528
    -- vga port connections
529
    vga_clk      : in  std_logic;       -- VGA Pixel Clock - 25 MHz
530
    vga_red_o    : out std_logic;
531
    vga_green_o  : out std_logic;
532
    vga_blue_o   : out std_logic;
533
    vga_hsync_o  : out std_logic;
534
    vga_vsync_o  : out std_logic
535
  );
536
end component;
537
 
538
----------------------------------------
539
--
540 19 dilbert57
-- Timer module
541
--
542
----------------------------------------
543
 
544
component timer
545
  port (
546 108 davidgb
    clk       : in std_logic;
547
    rst       : in std_logic;
548
    cs        : in std_logic;
549
    addr      : in std_logic;
550
    rw        : in std_logic;
551
    data_in   : in std_logic_vector(7 downto 0);
552
         data_out  : out std_logic_vector(7 downto 0);
553
         irq       : out std_logic
554
  );
555 19 dilbert57
end component;
556
 
557
------------------------------------------------------------
558
--
559
-- Bus Trap logic
560
--
561
------------------------------------------------------------
562
 
563
component trap
564 108 davidgb
  port (
565
    clk        : in  std_logic;
566 19 dilbert57
    rst        : in  std_logic;
567
    cs         : in  std_logic;
568
    rw         : in  std_logic;
569
    vma        : in  std_logic;
570
    addr       : in  std_logic_vector(15 downto 0);
571
    data_in    : in  std_logic_vector(7 downto 0);
572 108 davidgb
    data_out   : out std_logic_vector(7 downto 0);
573
    irq        : out std_logic
574 19 dilbert57
  );
575
end component;
576
 
577
----------------------------------------
578
--
579
-- Dual 8 bit Parallel I/O module
580
--
581
----------------------------------------
582
component ioport
583 108 davidgb
  port (
584
    clk       : in  std_logic;
585 19 dilbert57
    rst       : in  std_logic;
586
    cs        : in  std_logic;
587
    rw        : in  std_logic;
588
    addr      : in  std_logic_vector(1 downto 0);
589
    data_in   : in  std_logic_vector(7 downto 0);
590 108 davidgb
    data_out  : out std_logic_vector(7 downto 0);
591
    porta_io  : inout std_logic_vector(7 downto 0);
592
    portb_io  : inout std_logic_vector(7 downto 0)
593 19 dilbert57
  );
594
end component;
595
 
596 108 davidgb
------------------------------------------------------------
597
--
598
-- Peripheral Bus interface (IDE CF) ($E100 - $E1FF)
599
--
600
------------------------------------------------------------
601 19 dilbert57
 
602 108 davidgb
component peripheral_bus is
603
  port (
604
    --
605
    -- CPU Interface signals
606
    --
607
    clk      : in  std_logic;                     -- System Clock
608
    rst      : in  std_logic;                     -- Reset input (active high)
609
    cs       : in  std_logic;                     -- Peripheral Bus Chip Select
610
    addr     : in  std_logic_vector(7 downto 0);  -- Register Select
611
    rw       : in  std_logic;                     -- Read / Not Write
612
    data_in  : in  std_logic_vector(7 downto 0);  -- Data Bus In 
613
    data_out : out std_logic_vector(7 downto 0);  -- Data Bus Out
614
    hold     : out std_logic;                     -- Hold bus cycle output
615
    --
616
    -- Peripheral Bus Interface Signals
617
    -- IO + ($00 - $FF) 
618
    -- (for compatibility with XSA-3S1000 / XST 3.0)
619
    --
620
    pb_rd_n  : out   std_logic; -- ide pin 25
621
    pb_wr_n  : out   std_logic; -- ide pin 23
622
    pb_addr  : out   std_logic_vector( 4 downto 0);
623
    pb_data  : inout std_logic_vector(15 downto 0);
624
 
625
    -- Peripheral chip selects on Peripheral Bus 
626
    ide_cs   : out  std_logic;  -- IDE / CF interface ($00 - $3F)
627
    eth_cs   : out  std_logic;  -- Ethernet interface ($40 - $7F)
628
    sl1_cs   : out  std_logic;  -- Expansion slot 1   ($80 - $BF)
629
    sl2_cs   : out  std_logic   -- Expansion slot 2   ($C0 - $FF)
630
    );
631
end component;
632
 
633 19 dilbert57
 
634
component BUFG
635
  port (
636
                i: in  std_logic;
637
                o: out std_logic
638
  );
639
end component;
640
 
641
begin
642 108 davidgb
-----------------------------------------------------------------------------
643
-- Instantiation of internal components
644
-----------------------------------------------------------------------------
645
----------------------------------------
646
--
647
-- Clock generator
648
--
649
----------------------------------------
650
my_clock_div: clock_div port map (
651
    clk_in   => clk_in,   -- Clock input
652
    sys_clk  => sys_clk,  -- System Clock Out    (1/1)
653
    vga_clk  => vga_clk,  -- VGA Pixel Clock Out (1/2)
654
    cpu_clk  => cpu_clk   -- CPU Clock Out       (1/4)
655
  );
656
 
657
-----------------------------------------
658
--
659
-- LED Flasher
660
--
661
-----------------------------------------
662 19 dilbert57
 
663 108 davidgb
my_LED_flasher : flasher port map (
664
    clk      => cpu_clk,
665
    rst      => cpu_rst,
666
    LED      => LED
667
  );
668
 
669
 
670 19 dilbert57
----------------------------------------
671
--
672
-- CPU09 CPU Core
673
--
674
----------------------------------------
675
my_cpu : cpu09  port map (
676
         clk         => cpu_clk,
677 108 davidgb
    rst       => cpu_rst,
678
    vma       => cpu_vma,
679
    addr      => cpu_addr(15 downto 0),
680 19 dilbert57
    rw       => cpu_rw,
681
    data_in   => cpu_data_in,
682
         data_out  => cpu_data_out,
683
         halt      => cpu_halt,
684
         hold      => cpu_hold,
685
         irq       => cpu_irq,
686
         nmi       => cpu_nmi,
687
         firq      => cpu_firq
688
  );
689
 
690
----------------------------------------
691
--
692
-- Dynamic Address Translation Registers
693
--
694
----------------------------------------
695
my_dat : dat_ram port map (
696
    clk        => cpu_clk,
697 108 davidgb
         rst        => cpu_rst,
698 19 dilbert57
         cs         => dat_cs,
699
         rw         => cpu_rw,
700
         addr_hi    => cpu_addr(15 downto 12),
701
         addr_lo    => cpu_addr(3 downto 0),
702
    data_in    => cpu_data_out,
703
         data_out   => dat_addr(7 downto 0)
704
         );
705
 
706
----------------------------------------
707
--
708 108 davidgb
-- SBUG / KBUG / SYS09BUG Monitor ROM
709
--
710
----------------------------------------
711
my_rom : SYS09BUG_F800 port map (
712
       clk      => cpu_clk,
713
                 rst      => cpu_rst,
714
                 cs       => rom_cs,
715
       addr     => cpu_addr(10 downto 0),
716
                 rw       => '1',
717
                 data_in  => cpu_data_out,
718
       data_out => rom_data_out
719
    );
720
 
721
----------------------------------------
722
--
723 19 dilbert57
-- ACIA/UART Serial interface
724
--
725
----------------------------------------
726 108 davidgb
my_acia  : acia6850 port map (
727 19 dilbert57
         clk         => cpu_clk,
728 108 davidgb
         rst       => cpu_rst,
729 19 dilbert57
    cs        => uart_cs,
730 108 davidgb
    addr      => cpu_addr(0),
731 19 dilbert57
         rw        => cpu_rw,
732 108 davidgb
         data_in   => cpu_data_out,
733
         data_out  => uart_data_out,
734 19 dilbert57
    irq       => uart_irq,
735
         RxC       => uart_clk,
736
         TxC       => uart_clk,
737
         RxD       => rxbit,
738
         TxD       => txbit,
739
         DCD_n     => dcd_n,
740
         CTS_n     => cts_n,
741
         RTS_n     => rts_n
742
         );
743
 
744
----------------------------------------
745
--
746
-- ACIA Clock
747
--
748
----------------------------------------
749
my_ACIA_Clock : ACIA_Clock
750
  generic map(
751 108 davidgb
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
752
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
753 19 dilbert57
  )
754
  port map(
755 108 davidgb
    clk        => sys_clk,
756 19 dilbert57
    acia_clk   => uart_clk
757
  );
758
 
759
----------------------------------------
760
--
761
-- PS/2 Keyboard Interface
762
--
763
----------------------------------------
764
my_keyboard : keyboard
765
   generic map (
766 108 davidgb
     KBD_CLK_FREQ => CPU_CLK_FREQ
767 19 dilbert57
        )
768
   port map(
769 108 davidgb
          clk          => cpu_clk,
770
          rst          => cpu_rst,
771
          cs           => kbd_cs,
772
          addr         => cpu_addr(0),
773
          rw           => cpu_rw,
774
          data_in      => cpu_data_out(7 downto 0),
775
          data_out     => kbd_data_out(7 downto 0),
776
          irq          => kbd_irq,
777
          kbd_clk      => kb_clock,
778
          kbd_data     => kb_data
779 19 dilbert57
        );
780 108 davidgb
 
781
 
782
------------------------------------------------
783
--
784
-- Video Display Unit instantiation ($E030-$E03F)
785
--
786
-------------------------------------------------
787
my_vdu : vdu8
788
  generic map(
789
    VGA_CLK_FREQ           => VGA_CLK_FREQ, -- 25MHZ
790
    VGA_HOR_CHARS          => 80, -- CHARACTERS 25.6us
791
    VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS 0.32us
792
    VGA_HOR_FRONT_PORCH    => 16, -- PIXELS 0.64us
793
    VGA_HOR_SYNC           => 96, -- PIXELS 3.84us
794
    VGA_HOR_BACK_PORCH     => 48, -- PIXELS 1.92us
795
    VGA_VER_CHARS          => 25, -- CHARACTERS 12.8ms
796
    VGA_VER_CHAR_LINES     => 16, -- LINES 0.512ms
797
    VGA_VER_FRONT_PORCH    => 10, -- LINES 0.320ms
798
    VGA_VER_SYNC           => 2,  -- LINES 0.064ms
799
    VGA_VER_BACK_PORCH     => 34  -- LINES 1.088ms
800
  )
801
  port map(
802
 
803
    -- CPU Control Registers interface
804
    vdu_clk       => cpu_clk,                                    -- 12.5 MHz System Clock in
805
    vdu_rst       => cpu_rst,
806
    vdu_cs        => vdu_cs,
807
    vdu_rw        => cpu_rw,
808
    vdu_addr      => cpu_addr(2 downto 0),
809
    vdu_data_in   => cpu_data_out,
810
    vdu_data_out  => vdu_data_out,
811
 
812
    -- vga port connections
813
    vga_clk       => vga_clk,                                    -- 25 MHz VDU pixel clock
814
    vga_red_o     => vga_red,
815
    vga_green_o   => vga_green,
816
    vga_blue_o    => vga_blue,
817
    vga_hsync_o   => h_drive,
818
    vga_vsync_o   => v_drive
819
  );
820 19 dilbert57
 
821
----------------------------------------
822
--
823
-- Timer Module
824
--
825
----------------------------------------
826
my_timer  : timer port map (
827
    clk       => cpu_clk,
828 108 davidgb
         rst       => cpu_rst,
829
    cs        => tmr_cs,
830 19 dilbert57
         rw        => cpu_rw,
831
    addr      => cpu_addr(0),
832
         data_in   => cpu_data_out,
833 108 davidgb
         data_out  => tmr_data_out,
834
    irq       => tmr_irq
835 19 dilbert57
    );
836
 
837
----------------------------------------
838
--
839
-- Bus Trap Interrupt logic
840
--
841
----------------------------------------
842
my_trap : trap port map (
843
         clk        => cpu_clk,
844 108 davidgb
    rst        => cpu_rst,
845 19 dilbert57
    cs         => trap_cs,
846
    rw         => cpu_rw,
847
         vma        => cpu_vma,
848
    addr       => cpu_addr,
849
    data_in    => cpu_data_out,
850
         data_out   => trap_data_out,
851
         irq        => trap_irq
852
    );
853
 
854
----------------------------------------
855
--
856
-- Parallel I/O Port
857
--
858
----------------------------------------
859
my_ioport  : ioport port map (
860
         clk       => cpu_clk,
861 108 davidgb
    rst       => cpu_rst,
862
    cs        => pio_cs,
863 19 dilbert57
    rw        => cpu_rw,
864
    addr      => cpu_addr(1 downto 0),
865
    data_in   => cpu_data_out,
866 108 davidgb
         data_out  => pio_data_out,
867 19 dilbert57
         porta_io  => porta,
868
         portb_io  => portb
869
         );
870 108 davidgb
 
871 19 dilbert57
 
872 108 davidgb
------------------------------------------------
873
--
874
-- 16 bit Peripheral Bus interface ($E100-$E1FF)
875
--
876
------------------------------------------------
877
my_pb : peripheral_bus port map (
878
    --
879
    -- CPU Interface signals
880
    --
881
    clk       => cpu_clk,
882
    rst       => cpu_rst,
883
    cs        => pb_cs,
884
    addr      => cpu_addr(7 downto 0),
885
    rw        => cpu_rw,
886
    data_in   => cpu_data_out,
887
    data_out  => pb_data_out,
888
    hold      => pb_hold,
889
    --
890
    -- Peripheral Bus Interface Signals
891
    -- IO + ($00 - $FF) 
892
    --
893
    pb_rd_n   => cf_rd_n,
894
    pb_wr_n   => cf_wr_n,
895
    pb_addr(2 downto 0) => cf_a,
896
    pb_addr(4 downto 3) => open,
897
    pb_data   => cf_d,
898
 
899
    -- Peripheral chip selects on Peripheral Bus 
900
    ide_cs    => cf_cs,
901
    eth_cs    => open,
902
    sl1_cs    => open,
903
    sl2_cs    => open
904 19 dilbert57
    );
905 108 davidgb
 
906
-----------------------------------------------
907
--
908
-- BED SRAM interface (256KBytes) ($0000-$DFFF)
909
--
910
-----------------------------------------------
911
my_bed_sram : BED_SRAM port map (
912
    --
913
    -- CPU Interface signals
914
    --
915
    clk       => vga_clk,                        -- VGA Clock (twice the CPU clock)
916
    rst       => cpu_rst,                        -- Reset input (active high)
917
    cs        => ram_cs,                         -- RAM Chip Select
918
    addr(17 downto 12) => dat_addr( 5 downto 0), -- High RAM address goes to the DAT
919
    addr(11 downto  0) => cpu_addr(11 downto 0), -- Low RAM address goes to the CPU
920
    rw        => cpu_rw,                         -- Read / Not Write
921
    data_in   => cpu_data_out,                   -- Data Bus In 
922
    data_out  => ram_data_out,                   -- Data Bus Out
923
    --
924
    -- BED_SRAM Interface Signals
925
    --
926
    ram_csn   => ram_csn,
927
    ram_wrln  => ram_wrln,
928
    ram_wrun  => ram_wrun,
929
    ram_addr  => ram_addr,
930
    ram_data  => ram_data
931
    );
932 19 dilbert57
 
933
----------------------------------------------------------------------
934
--
935
-- Process to decode memory map
936
--
937
----------------------------------------------------------------------
938
 
939 108 davidgb
mem_decode: process( dat_addr,
940 19 dilbert57
                     cpu_addr, cpu_rw, cpu_vma,
941
                                              rom_data_out,
942
                                                   uart_data_out,
943 108 davidgb
                                                        kbd_data_out,
944 19 dilbert57
                                                        vdu_data_out,
945 108 davidgb
                                                   tmr_data_out,
946
                                                        trap_data_out,
947
                                                        pio_data_out,
948
                                                        bus_data,
949
                     pb_data_out,
950
                                                        ram_data_out )
951 19 dilbert57
begin
952 108 davidgb
  rom_cs   <= '0';              -- read ROM
953
  dat_cs   <= '0';              -- write DAT
954
  ram_cs   <= '0';
955
  uart_cs  <= '0';
956
  kbd_cs   <= '0';
957
  vdu_cs   <= '0';
958
  tmr_cs   <= '0';
959
  trap_cs  <= '0';
960
  pio_cs   <= '0';
961
  bus_cs   <= '0';
962
  pb_cs    <= '0';
963
 
964
  --
965
  -- ROM / DAT $FF00 - $FFFF
966
  -- 
967
  if cpu_addr( 15 downto 8 ) = "11111111" then
968
    cpu_data_in <= rom_data_out;
969
    rom_cs      <= cpu_vma;              -- read ROM
970
    dat_cs      <= cpu_vma;              -- write DAT
971
  else
972
    --
973
    -- Decode on 4K Byte boundaries
974
    --
975
    case dat_addr(3 downto 0) is
976
    when "1111" => -- $F000 - $FFFF
977
      if cpu_addr(11) = '1' then
978
        --
979
        -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
980
        --
981
        cpu_data_in <= rom_data_out;
982
        rom_cs      <= cpu_vma;
983
      else
984
        --
985
        -- SRAM $F000 - $F7FF
986
        -- Future use DMAF-2 Floppy Disk controller
987
        -- 
988
        cpu_data_in <= ram_data_out;
989
        ram_cs      <= cpu_vma;
990
      end if;
991
    --
992
    -- IO Devices $EXXX - $EXXX
993
    --
994
    when "1110" =>
995
      --
996
      -- Decode on 256 Byte boundaries
997
      -- IO device $E0XX - $E7XX
998
      --
999
      case cpu_addr(10 downto 8) is
1000
      when "000" =>
1001
         --
1002
         -- Decode I/O Devices on 16 byte boundaries
1003
         -- IO device $E00X - $E0FX
1004
         --
1005 19 dilbert57
                   case cpu_addr(7 downto 4) is
1006
                        --
1007
                        -- UART / ACIA $E000
1008
                        --
1009
                        when "0000" => -- $E000
1010
                     cpu_data_in <= uart_data_out;
1011
                          uart_cs     <= cpu_vma;
1012
 
1013
                        --
1014
                        -- WD1771 FDC sites at $E010-$E01F
1015
                        --
1016
 
1017
         --
1018
         -- Keyboard port $E020 - $E02F
1019
                        --
1020
                        when "0010" => -- $E020
1021 108 davidgb
           cpu_data_in <= kbd_data_out;
1022
                          kbd_cs      <= cpu_vma;
1023 19 dilbert57
 
1024
         --
1025
         -- VDU port $E030 - $E03F
1026
                        --
1027
                        when "0011" => -- $E030
1028
           cpu_data_in <= vdu_data_out;
1029
                          vdu_cs      <= cpu_vma;
1030
 
1031
         --
1032 108 davidgb
                        -- Reserved $E040 - $E04F
1033
         --
1034 19 dilbert57
 
1035
         --
1036
         -- Timer $E050 - $E05F
1037
                        --
1038
                        when "0101" => -- $E050
1039 108 davidgb
           cpu_data_in <= tmr_data_out;
1040
           tmr_cs    <= cpu_vma;
1041 19 dilbert57
 
1042
         --
1043
         -- Bus Trap Logic $E060 - $E06F
1044
                        --
1045
                        when "0110" => -- $E060
1046
           cpu_data_in <= trap_data_out;
1047
                          trap_cs     <= cpu_vma;
1048
 
1049
         --
1050 108 davidgb
         -- Parallel I/O port $E070 - $E07F
1051 19 dilbert57
                        --
1052
                        when "0111" => -- $E070
1053 108 davidgb
           cpu_data_in <= pio_data_out;
1054
                          pio_cs       <= cpu_vma;
1055
 
1056
         --
1057
         -- Undefined / Extension Bus $E080 - $E0FF
1058
         --
1059
                        when others => -- $E080 to $E0FF
1060 19 dilbert57
           cpu_data_in <= bus_data;
1061 108 davidgb
           bus_cs      <= cpu_vma;
1062
                   end case;
1063
 
1064
      --
1065
      -- Peripheral Bus $E100 - $E1FF
1066
      --
1067
      when "001" =>
1068
        cpu_data_in <= pb_data_out;
1069
        pb_cs       <= cpu_vma;
1070
 
1071
      --
1072
      -- Map RAM at $E200 - $EFFF Just in case we need driver space.
1073
      --
1074
      when others =>
1075
         cpu_data_in <= ram_data_out;
1076
         ram_cs      <= cpu_vma;
1077
      end case;
1078
    --
1079
    -- Everything else is RAM $0000 - $DFFF
1080
    --
1081
    when others =>
1082
      cpu_data_in <= ram_data_out;
1083
      ram_cs      <= cpu_vma;
1084
    end case;
1085
  end if;
1086 19 dilbert57
end process;
1087
 
1088
--
1089
-- Interrupts and other bus control signals
1090
--
1091 108 davidgb
interrupts : process( rst_n, pb_hold,
1092
                      uart_irq, trap_irq, tmr_irq, kbd_irq )
1093 19 dilbert57
begin
1094 108 davidgb
         cpu_rst   <= not rst_n; -- CPU reset is active high
1095
    cpu_irq   <= uart_irq or kbd_irq;
1096 19 dilbert57
         cpu_nmi   <= trap_irq;
1097 108 davidgb
         cpu_firq  <= tmr_irq;
1098 19 dilbert57
         cpu_halt  <= '0';
1099 108 davidgb
         cpu_hold  <= pb_hold;
1100 19 dilbert57
end process;
1101
 
1102
--
1103
-- CPU bus signals
1104
--
1105 108 davidgb
my_bus : process( cpu_clk, cpu_rst, cpu_rw, cpu_addr, cpu_data_out )
1106 19 dilbert57
begin
1107
        bus_clk   <= cpu_clk;
1108 108 davidgb
   bus_reset <= cpu_rst;
1109 19 dilbert57
        bus_rw    <= cpu_rw;
1110
   bus_addr  <= cpu_addr;
1111
        if( cpu_rw = '1' ) then
1112 108 davidgb
           bus_data <= (others => 'Z');
1113 19 dilbert57
   else
1114
           bus_data <= cpu_data_out;
1115
   end if;
1116
end process;
1117
 
1118
--
1119
-- Assign VDU VGA colour output
1120
-- only 8 colours are handled.
1121
--
1122
my_vga_out: process( vga_red, vga_green, vga_blue )
1123
begin
1124
           red_lo   <= vga_red;
1125
      red_hi   <= vga_red;
1126
      green_lo <= vga_green;
1127
      green_hi <= vga_green;
1128
      blue_lo  <= vga_blue;
1129
      blue_hi  <= vga_blue;
1130
end process;
1131 108 davidgb
 
1132
--
1133
-- CF card chip selects ($E100 - $E13F)
1134
-- Located on peripheral bus
1135
--
1136
my_cf_decode: process( cpu_rst, cpu_addr, cf_cs )
1137
begin
1138
 
1139
  cf_cs0_n  <= not( cf_cs and not cpu_addr(4));
1140
  cf_cs1_n  <= not( cf_cs and     cpu_addr(4));
1141
  cf_rst_n  <= not cpu_rst;
1142
 
1143
end process;
1144 19 dilbert57
 
1145
end rtl; --===================== End of architecture =======================--
1146
 

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