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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S1000/] [System09_Digilent_3S1000.vhd] - Blame information for rev 117

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1 105 davidgb
--===========================================================================--
2
--                                                                           --
3
-- Synthesizable 6809 SoC Top Level File For Digilent XC3S1000 Starter Board --
4
--                                                                           --
5
--===========================================================================--
6
--
7
--  File name      : System09_Digilent_3S1000.vhd
8
--
9
--  Purpose        : Implements the top level of a Quad core 6809 instruction 
10
--                   System on a Chip (SoC) for the Digilent Spartan 3 Starter board 
11
--                   fitted with the XC3S1000 FPGA.
12
--                   Memory mapping of peripherals and memory are similar to the 
13
--                   SWTPc 6809 MP-09. 
14
--
15
--  Status:        : *** Currently under development ***
16
--                   The version for the Digilenet Spartan 3 Starter board using the
17
--                   XC3S200 FPGA should also work on the XC3S1000 if the FPGA type
18
--                   is changed in the Xilinx ISE project file.
19
--                  
20
--  Dependencies   : ieee.Std_Logic_1164
21
--                   ieee.std_logic_unsigned
22
--                   ieee.std_logic_arith
23
--                   ieee.numeric_std
24
--
25
--  Uses           : mon_rom   (sys09bug_rom4k_b16.vhd) Monitor ROM
26
--                   quadcpu09 (quadcpu09.vhd)          Quad CPU core
27
--                   dat_ram   (datram.vhd)             Dynamic Address Translation
28
--                   acia6850  (acia6850.vhd)           ACIA (UART)
29
--                   keyboard  (keyboard.vhd)           PS/2 Keyboard
30
--                             (ps2_keyboard.vhd)
31
--                             (keymap_rom)
32
--                   vdu8      (vdu8.vhd)                         Video Display Unit
33
--                             (char_rom2K_b16.vhd)
34
--                             (ram2k_b16.vhd)
35
--                   seven_segment (SevenSegment.vhd)   Seven Segment Display
36
--
37
--  Author         : John E. Kent
38
--
39
--  Email          : dilbert57@opencores.org      
40
--
41
--  Web            : http://opencores.org/project,system09
42
--
43
--  Copyright (C) 2003 - 2010 John Kent
44
--
45
--  This program is free software: you can redistribute it and/or modify
46
--  it under the terms of the GNU General Public License as published by
47
--  the Free Software Foundation, either version 3 of the License, or
48
--  (at your option) any later version.
49
--
50
--  This program is distributed in the hope that it will be useful,
51
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
52
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
53
--  GNU General Public License for more details.
54
--
55
--  You should have received a copy of the GNU General Public License
56
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
57
--
58
--===========================================================================--
59
--                                                                           --
60
--                              Revision  History                            --
61
--                                                                           --
62
--===========================================================================--
63
--
64
-- Version       Date          Author     Changes
65
-- 
66
-- Version 0.1 - 20 March 2003 - John Kent
67
-- Version 0.2 - 30 March 2003 - John Kent
68
-- Version 0.3 - 29 April 2003 - John Kent
69
-- Version 0.4 - 29 June 2003  - John Kent
70
--
71
-- Version 0.5 - 19 July 2003 - John Kent
72
-- prints out "Hello World"
73
--
74
-- Version 0.6 - 5 September 2003 - John Kent
75
-- Runs SBUG
76
--
77
-- Version 1.0- 6 Sep 2003 - John Kent
78
-- Inverted sys_clk
79
-- Initial release to Open Cores
80
--
81
-- Version 1.1 - 17 Jan 2004 - John Kent
82
-- Updated miniUart.
83
--
84
-- Version 1.2 - 25 Jan 2004 - John Kent
85
-- removed signals "test_alu" and "test_cc" 
86
-- Trap hardware re-instated.
87
--
88
-- Version 1.3 - 11 Feb 2004 - John Kent
89
-- Designed forked off to produce System09_VDU
90
-- Added VDU component
91
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
92
-- UART Runs at 57.6 Kbps
93
--
94
-- Version 2.0 - 2 September 2004 - John Kent
95
-- ported to Digilent Xilinx Spartan3 starter board
96
--      removed Compaact Flash and Trap Logic.
97
-- Replaced SBUG with KBug9s
98
--
99
-- Version 2.1 - 21 November 2006 - John Kent
100
-- Replaced KBug9s with Sys09bug 1.0
101
-- Inverted bottom nybble of DAT register outputs
102
-- Changed ROM & I/O decoding to be compatible with SWTPc
103
-- Upped the serial baud rate to 115.2 KBd
104
-- added multiple global clock buffers
105
-- (Uart would not operate correctly)
106
--
107
-- Version 2.2 - 22 December 2006 - John Kent
108
-- Increased CPU clock from 12.5MHz to 25 MHz.
109
-- Removed some of the global clock buffers
110
-- Added LED output register
111
-- Changed address decoding to 4K Blocks
112
--
113
-- Version 2.3 - 1 June 2007 - John Kent
114
-- Updated VDU & ACIA
115
-- Changed decoding for Sys09Bug
116
--
117
-- Version 2.4 - 31 January 2008 - John Kent
118
--      ACIA does not appear to work.
119
-- Made RAM OE and WE strobes synchonous to sys_clk
120
--
121
-- Version 3.0 - 16 June 2010 - John Kent
122
-- *** Under development ***
123
-- Updated GPL notice.  
124
-- Work under way to implementing a quad core version.
125
--
126
--===========================================================================--
127
library ieee;
128
   use ieee.std_logic_1164.all;
129
   use ieee.std_logic_arith.all;
130
   use ieee.std_logic_unsigned.all;
131
   use ieee.numeric_std.all;
132
 
133
entity my_system09 is
134
  port(
135
    sys_clk     : in  Std_Logic;  -- System Clock input
136
         rst_sw      : in  Std_logic;  -- Master Reset input (active high)
137
         nmi_sw      : in  Std_logic;
138
 
139
    -- Memory Interface signals
140
    ram_addr    : out Std_Logic_Vector(17 downto 0);
141
    ram_wen     : out Std_Logic;
142
    ram_oen     : out Std_Logic;
143
 
144
    ram1_cen    : out Std_Logic;
145
         ram1_ubn    : out Std_Logic;
146
         ram1_lbn    : out Std_Logic;
147
    ram1_data   : inout Std_Logic_Vector(15 downto 0);
148
 
149
    ram2_cen    : out Std_Logic;
150
         ram2_ubn    : out Std_Logic;
151
         ram2_lbn    : out Std_Logic;
152
    ram2_data   : inout Std_Logic_Vector(15 downto 0);
153
 
154
         -- PS/2 Keyboard
155
         ps2c        : inout Std_logic;
156
         ps2d        : inout Std_Logic;
157
 
158
         -- ACIA Interface
159
    rxd         : in  Std_Logic;
160
         txd         : out Std_Logic;
161
 
162
         -- CRTC output signals
163
         vs          : out Std_Logic;
164
    hs          : out Std_Logic;
165
    blue        : out std_logic;
166
    green       : out std_logic;
167
    red         : out std_logic;
168
 
169
         -- LEDS & Switches
170
         switches    : in  std_logic_vector(7 downto 0);
171
         leds        : out std_logic_vector(7 downto 0);
172
 
173
         -- seven segment display
174
         segments    : out std_logic_vector(7 downto 0);
175
         digits      : out std_logic_vector(3 downto 0)
176
         );
177
end my_system09;
178
 
179
-------------------------------------------------------------------------------
180
-- Architecture for System09
181
-------------------------------------------------------------------------------
182
architecture my_computer of my_system09 is
183
  -----------------------------------------------------------------------------
184
  -- constants
185
  -----------------------------------------------------------------------------
186
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
187
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
188
  constant CPU_CLK_FREQ  : integer := 25000000;  -- CPU Clock
189
  constant BAUD_RATE     : integer := 57600;        -- Baud Rate
190
  constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
191
 
192
  type hold_state_type is ( hold_release_state, hold_request_state );
193
 
194
  -----------------------------------------------------------------------------
195
  -- Signals
196
  -----------------------------------------------------------------------------
197
 
198
  -- ACIA Interface signals
199
  signal acia_clk      : std_logic;
200
  signal acia_cs       : Std_Logic;
201
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
202
  signal acia_irq      : Std_Logic;
203
  signal acia_rxd      : Std_Logic;
204
  signal acia_txd      : Std_Logic;
205
  signal acia_dcd_n    : Std_Logic;
206
--  signal acia_rts_n    : Std_Logic;
207
  signal acia_cts_n    : Std_Logic;
208
 
209
  -- keyboard port
210
  signal kbd_cs       : std_logic;
211
  signal kbd_data_out : std_logic_vector(7 downto 0);
212
  signal kbd_irq      : std_logic;
213
 
214
  -- LEDs
215
  signal led_cs       : std_logic;
216
  signal led_data_out : std_logic_vector(7 downto 0);
217
 
218
  -- RAM
219
  signal ram_cs       : std_logic; -- memory chip select
220
  signal ram_data_out : std_logic_vector(7 downto 0);
221
  signal ram1_ce      : std_logic;
222
  signal ram1_ub      : std_logic;
223
  signal ram1_lb      : std_logic;
224
  signal ram2_ce      : std_logic;
225
  signal ram2_ub      : std_logic;
226
  signal ram2_lb      : std_logic;
227
  signal ram_we       : std_logic;
228
  signal ram_oe       : std_logic;
229
 
230
  -- CPU Interface signals
231
  signal cpu_rst      : Std_Logic;
232
  signal cpu_clk      : Std_Logic;
233
  signal cpu_vma      : std_logic;
234
  signal cpu_addr     : std_logic_vector(19 downto 0);
235
  signal cpu_rw       : std_logic;
236
  signal cpu_data_in  : std_logic_vector(7 downto 0);
237
  signal cpu_data_out : std_logic_vector(7 downto 0);
238
  signal cpu_firq     : std_logic;
239
  signal cpu_irq      : std_logic;
240
  signal cpu_nmi      : std_logic;
241
  signal cpu_halt     : std_logic;
242
  signal cpu_hold     : std_logic;
243
 
244
  -- Video Display Unit
245
  signal vdu_cs       : std_logic;
246
  signal vdu_data_out : std_logic_vector(7 downto 0);
247
  signal vga_clk      : std_logic;
248
 
249
  -- 7 Segment Display
250
  signal seg_cs       : std_logic;
251
  signal seg_data_out : std_logic_vector(7 downto 0);
252
 
253
  -- System Clock Prescaler
254
  signal clk_count    : std_logic;
255
 
256
-----------------------------------------------------------------
257
--
258
-- Quad CPU09 CPU core
259
--
260
-----------------------------------------------------------------
261
 
262
component quadcpu09
263
  port (
264
         clk      :     in  std_logic;
265
    rst      : in  std_logic;
266
    vma      :  out std_logic;
267
    addr     : out std_logic_vector(19 downto 0);
268
    rw       :  out std_logic;
269
         data_out : out std_logic_vector(7 downto 0);
270
    data_in  : in        std_logic_vector(7 downto 0);
271
         irq      : in  std_logic;
272
         nmi      : in  std_logic;
273
         firq     : in  std_logic;
274
         halt     : in  std_logic;
275
         hold     : in  std_logic
276
  );
277
end component;
278
 
279
 
280
-----------------------------------------------------------------
281
--
282
-- 6850 ACIA
283
--
284
-----------------------------------------------------------------
285
 
286
component acia6850
287
  port (
288
    clk      : in  Std_Logic;  -- System Clock
289
    rst      : in  Std_Logic;  -- Reset input (active high)
290
    cs       : in  Std_Logic;  -- ACIA Chip Select
291
    addr     : in  Std_Logic;  -- Register Select
292
    rw       : in  Std_Logic;  -- Read / Not Write
293
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
294
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
295
    irq      : out Std_Logic;  -- Interrupt
296
    RxC      : in  Std_Logic;  -- Receive Baud Clock
297
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
298
    RxD      : in  Std_Logic;  -- Receive Data
299
    TxD      : out Std_Logic;  -- Transmit Data
300
         DCD_n    : in  Std_Logic;  -- Data Carrier Detect
301
    CTS_n    : in  Std_Logic;  -- Clear To Send
302
    RTS_n    : out Std_Logic   -- Request To send
303
  );
304
end component;
305
 
306
-----------------------------------------------------------------
307
--
308
-- ACIA Clock divider
309
--
310
-----------------------------------------------------------------
311
 
312
component ACIA_Clock
313
  generic (
314
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
315
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
316
  );
317
  port (
318
     CLK      : in  std_logic;  -- System Clock Input
319
          ACIA_CLK : out std_logic   -- ACIA Clock output
320
  );
321
end component;
322
 
323
 
324
----------------------------------------
325
--
326
-- PS/2 Keyboard
327
--
328
----------------------------------------
329
 
330
component keyboard
331
  generic(
332
  KBD_CLK_FREQ : integer := CPU_CLK_FREQ
333
  );
334
  port(
335
  clk             : in    std_logic;
336
  rst             : in    std_logic;
337
  cs              : in    std_logic;
338
  addr            : in    std_logic;
339
  rw              : in    std_logic;
340
  data_in         : in    std_logic_vector(7 downto 0);
341
  data_out        : out   std_logic_vector(7 downto 0);
342
  irq             : out   std_logic;
343
  kbd_clk         : inout std_logic;
344
  kbd_data        : inout std_logic
345
  );
346
end component;
347
 
348
----------------------------------------
349
--
350
-- Video Display Unit.
351
--
352
----------------------------------------
353
component vdu8
354
      generic(
355
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
356
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
357
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
358
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
359
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
360
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
361
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
362
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
363
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
364
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
365
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
366
      );
367
      port(
368
                -- control register interface
369
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
370
      vdu_rst      : in  std_logic;
371
                vdu_cs       : in  std_logic;
372
                vdu_addr     : in  std_logic_vector(2 downto 0);
373
                vdu_rw       : in  std_logic;
374
      vdu_data_in  : in  std_logic_vector(7 downto 0);
375
      vdu_data_out : out std_logic_vector(7 downto 0);
376
 
377
      -- vga port connections
378
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
379
      vga_red_o    : out std_logic;
380
      vga_green_o  : out std_logic;
381
      vga_blue_o   : out std_logic;
382
      vga_hsync_o  : out std_logic;
383
      vga_vsync_o  : out std_logic
384
   );
385
end component;
386
 
387
----------------------------------------
388
--
389
-- Seven Segment Display driver
390
--
391
----------------------------------------
392
 
393
component seven_segment is
394
        port (
395
          clk         : in  std_logic;
396
     rst         : in  std_logic;
397
     cs          : in  std_logic;
398
     addr        : in  std_logic_vector(1 downto 0);
399
     rw          : in  std_logic;
400
     data_in     : in  std_logic_vector(7 downto 0);
401
          data_out    : out std_logic_vector(7 downto 0);
402
          segments    : out std_logic_vector(7 downto 0);
403
          digits             : out std_logic_vector(3 downto 0)
404
        );
405
end component;
406
 
407
component BUFG
408
  port (
409
    i            : in  std_logic;
410
    o            : out std_logic
411
  );
412
end component;
413
 
414
begin
415
  -----------------------------------------------------------------------------
416
  -- Instantiation of internal components
417
  -----------------------------------------------------------------------------
418
 
419
my_quadcpu : quadcpu09  port map (
420
         clk         => cpu_clk,
421
    rst       => cpu_rst,
422
    vma       => cpu_vma,
423
    addr      => cpu_addr(19 downto 0),
424
    rw       => cpu_rw,
425
         data_out  => cpu_data_out,
426
    data_in   => cpu_data_in,
427
         irq       => cpu_irq,
428
         nmi       => cpu_nmi,
429
         firq      => cpu_firq,
430
         halt      => cpu_halt,
431
         hold      => cpu_hold
432
    );
433
 
434
my_acia  : acia6850 port map (
435
         clk         => cpu_clk,
436
         rst       => cpu_rst,
437
    cs        => acia_cs,
438
    addr      => cpu_addr(0),
439
         rw        => cpu_rw,
440
         data_in   => cpu_data_out,
441
         data_out  => acia_data_out,
442
    irq       => acia_irq,
443
         RxC       => acia_clk,
444
         TxC       => acia_clk,
445
         RxD       => acia_rxd,
446
         TxD       => acia_txd,
447
         DCD_n     => acia_dcd_n,
448
         CTS_n     => acia_cts_n,
449
         RTS_n     => open
450
         );
451
 
452
 
453
----------------------------------------
454
--
455
-- ACIA Clock
456
--
457
----------------------------------------
458
my_ACIA_Clock : ACIA_Clock
459
  generic map(
460
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
461
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
462
  )
463
  port map(
464
    clk        => sys_clk,
465
    acia_clk   => acia_clk
466
  );
467
 
468
 
469
----------------------------------------
470
--
471
-- PS/2 Keyboard Interface
472
--
473
----------------------------------------
474
my_keyboard : keyboard
475
   generic map (
476
        KBD_CLK_FREQ => CPU_CLK_FREQ
477
        )
478
   port map(
479
        clk          => cpu_clk,
480
        rst          => cpu_rst,
481
        cs           => kbd_cs,
482
        addr         => cpu_addr(0),
483
        rw           => cpu_rw,
484
        data_in      => cpu_data_out(7 downto 0),
485
        data_out     => kbd_data_out(7 downto 0),
486
        irq          => kbd_irq,
487
        kbd_clk      => ps2c,
488
        kbd_data     => ps2d
489
        );
490
 
491
----------------------------------------
492
--
493
-- Video Display Unit instantiation
494
--
495
----------------------------------------
496
my_vdu : vdu8
497
  generic map(
498
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
499
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
500
           VGA_HOR_CHARS          => 80, -- CHARACTERS
501
           VGA_VER_CHARS          => 25, -- CHARACTERS
502
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
503
           VGA_LINES_PER_CHAR     => 16, -- LINES
504
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
505
           VGA_HOR_SYNC           => 96, -- PIXELS
506
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
507
           VGA_VER_BACK_PORCH     => 13, -- LINES
508
           VGA_VER_SYNC           => 1,  -- LINES
509
           VGA_VER_FRONT_PORCH    => 36  -- LINES
510
  )
511
  port map(
512
 
513
                -- Control Registers
514
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
515
      vdu_rst       => cpu_rst,
516
                vdu_cs        => vdu_cs,
517
                vdu_addr      => cpu_addr(2 downto 0),
518
                vdu_rw        => cpu_rw,
519
                vdu_data_in   => cpu_data_out,
520
                vdu_data_out  => vdu_data_out,
521
 
522
      -- vga port connections
523
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
524
      vga_red_o     => red,
525
      vga_green_o   => green,
526
      vga_blue_o    => blue,
527
      vga_hsync_o   => hs,
528
      vga_vsync_o   => vs
529
   );
530
 
531
 
532
----------------------------------------
533
--
534
-- Seven Segment Display instantiation
535
--
536
----------------------------------------
537
 
538
my_seg : seven_segment port map (
539
    clk        => cpu_clk,
540
         rst        => cpu_rst,
541
         cs         => seg_cs,
542
         addr       => cpu_addr(1 downto 0),
543
         rw         => cpu_rw,
544
    data_in    => cpu_data_out,
545
         data_out   => seg_data_out,
546
         segments   => segments,
547
         digits     => digits
548
         );
549
 
550
 
551
vga_clk_buffer : BUFG port map(
552
    i => clk_count,
553
         o => vga_clk
554
    );
555
 
556
cpu_clk_buffer : BUFG port map(
557
    i => clk_count,
558
         o => cpu_clk
559
    );
560
 
561
--
562
-- Clock divider
563
-- Assumes 50 MHz system clock
564
-- 25MHz pixel clock
565
-- 25MHz CPU clock
566
--
567
sys09_clock : process( sys_clk, clk_count )
568
begin
569
        if sys_clk'event and sys_clk='1' then
570
           clk_count <= not clk_count;
571
   end if;
572
end process;
573
 
574
----------------------------------------------------------------------
575
--
576
-- Process to decode memory map
577
--
578
----------------------------------------------------------------------
579
 
580
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
581
                                                   acia_data_out,
582
                                                        kbd_data_out,
583
                                                        vdu_data_out,
584
                                                        seg_data_out,
585
                                                        led_data_out,
586
                                                        ram_data_out
587
                                                        )
588
begin
589
      cpu_data_in <= (others=>'0');
590
      dat_cs      <= '0';
591
      acia_cs     <= '0';
592
      kbd_cs      <= '0';
593
      vdu_cs      <= '0';
594
      seg_cs      <= '0';
595
      led_cs     <= '0';
596
      ram_cs      <= '0';
597
--           timer_cs    <= '0';
598
--      trap_cs     <= '0';
599
--           pb_cs       <= '0';
600
--      ide_cs      <= '0';
601
--      ether_cs    <= '0';
602
--           slot1_cs    <= '0';
603
--      slot2_cs    <= '0';
604
 
605
      --
606
                -- IO Devices $E000 - $EFFF
607
                --
608
                if cpu_addr(15 downto 12) = "1110" then -- $XE000 - $XEFFF
609
                        case cpu_addr(11 downto 8) is
610
                        --
611
                        -- SWTPC peripherals from $E000 to $E0FF
612
                        --
613
                        when "0000" =>
614
                     case cpu_addr(7 downto 4) is
615
                          --
616
                          -- ACIA ($E000 - $E00F)
617
                          --
618
                          when "0000" =>
619
                            acia_cs     <= cpu_vma;
620
                       cpu_data_in <= acia_data_out;
621
 
622
                --
623
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
624
           --
625
 
626
                          --
627
           -- Keyboard port ($E020 - $E02F)
628
                          --
629
                          when "0010" =>
630
                            kbd_cs      <= cpu_vma;
631
             cpu_data_in <= kbd_data_out;
632
 
633
           --
634
           -- VDU port ($E030 - $E03F)
635
                          --
636
                          when "0011" =>
637
                            vdu_cs      <= cpu_vma;
638
             cpu_data_in <= vdu_data_out;
639
 
640
           --
641
                          -- Reserved - SWTPc MP-T ($E040 - $E04F)
642
                          --
643
 
644
           --
645
           -- Reserved - Timer ($E050 - $E05F) (B5-X300)
646
                          --
647
 
648
           --
649
           -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300)
650
                          --
651
 
652
           --
653
           -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
654
                          --
655
 
656
                          --
657
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
658
                          --
659
 
660
                          --
661
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
662
                          --
663
 
664
           --
665
                          -- Read Switched port ($E0A0 - $E0AF)
666
                          -- Write LEDS
667
                          --
668
                          when "1010" =>
669
                            led_cs      <= cpu_vma;
670
             cpu_data_in <= led_data_out;
671
 
672
           --
673
           -- 7 segment display port ($E0B0 - $E0BF)
674
                          --
675
                          when "1011" =>
676
                            seg_cs      <= cpu_vma;
677
             cpu_data_in <= seg_data_out;
678
 
679
 
680
                          when others => -- $EXC0 to $EXFF
681
                            null;
682
                     end case;
683
                        --
684
                        -- XST-3.0 Peripheral Bus goes here
685
                        --      $E100 to $E1FF
686
                        --      Four devices
687
                        -- IDE, Ethernet, Slot1, Slot2
688
                        --
689
--                      when "0001" =>
690
--                        cpu_data_in <= pb_data_out;
691
--                        pb_cs       <= cpu_vma;
692
--                   case cpu_addr(7 downto 6) is
693
                          --
694
                          -- IDE Interface $E100 to $E13F
695
                          --
696
--                        when "00" =>
697
--                          ide_cs   <= cpu_vma;
698
                          --
699
                          -- Ethernet Interface $E140 to $E17F
700
                          --
701
--                        when "01" =>
702
--                          ether_cs <= cpu_vma;
703
                          --
704
                          -- Slot 1 Interface $E180 to $E1BF
705
                          --
706
--                        when "10" =>
707
--                          slot1_cs <= cpu_vma;
708
                          --
709
                          -- Slot 2 Interface $E1C0 to $E1FF
710
                          --
711
--                        when "11" =>
712
--                          slot2_cs <= cpu_vma;
713
           --
714
                          -- Nothing else
715
                          --
716
--         when others =>
717
--           null;
718
--         end case;
719
         --
720
                        --      $E200 to $EFFF reserved for future use
721
                        --
722
                when others =>
723
                          null;
724
         end case;
725
                --
726
                -- Everything else is RAM
727
                --
728
                else
729
                  ram_cs      <= cpu_vma;
730
                  cpu_data_in <= ram_data_out;
731
      end if;
732
end process;
733
 
734
 
735
--
736
-- 1M byte SRAM Control
737
-- Processes to read and write memory based on bus signals
738
--
739
ram_process: process( cpu_rst, sys_clk,
740
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
741
                                               ram_cs,
742
                      ram1_ce, ram1_ub, ram1_lb, ram1_data,
743
                      ram2_ce, ram2_ub, ram2_lb, ram2_data,
744
                                                         ram_we, ram_oe )
745
begin
746
    --
747
    -- ram_hold signal helps 
748
    --
749
    if( cpu_rst = '1' ) then
750
           ram_we   <= '0';
751
           ram_oe   <= '0';
752
    --
753
         -- Clock Hold on rising edge
754
         --
755
    elsif( sys_clk'event and sys_clk='1' ) then
756
           if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then
757
             ram_we   <= not cpu_rw;
758
             ram_oe   <=     cpu_rw;
759
      else
760
             ram_we   <= '0';
761
             ram_oe   <= '0';
762
      end if;
763
    end if;
764
 
765
         ram_wen  <= not ram_we;
766
         ram_oen  <= not ram_oe;
767
 
768
    ram1_ce   <= ram_cs and (not cpu_addr(1));
769
    ram1_ub   <= not cpu_addr(0);
770
    ram1_lb   <= cpu_addr(0);
771
    ram1_cen  <= not ram1_ce;
772
    ram1_ubn  <= not ram1_ub;
773
    ram1_lbn  <= not ram1_lb;
774
 
775
    ram2_ce   <= ram_cs and cpu_addr(1);
776
    ram2_ub   <= not cpu_addr(0);
777
    ram2_lb   <= cpu_addr(0);
778
    ram2_cen  <= not ram2_ce;
779
    ram2_ubn  <= not ram2_ub;
780
    ram2_lbn  <= not ram2_lb;
781
 
782
         ram_addr(17 downto 0) <= cpu_addr(19 downto 2);
783
 
784
    if ram_we = '1' and ram1_ce = '1' and ram1_lb = '1' then
785
                ram1_data(7 downto 0) <= cpu_data_out;
786
         else
787
      ram1_data(7 downto 0)  <= "ZZZZZZZZ";
788
         end if;
789
 
790
    if ram_we = '1' and ram1_ce = '1' and ram1_ub = '1' then
791
                ram1_data(15 downto 8) <= cpu_data_out;
792
         else
793
      ram1_data(15 downto 8)  <= "ZZZZZZZZ";
794
         end if;
795
 
796
    if ram_we = '1' and ram2_ce = '1' and ram2_lb = '1' then
797
                ram2_data(7 downto 0) <= cpu_data_out;
798
         else
799
      ram2_data(7 downto 0)  <= "ZZZZZZZZ";
800
         end if;
801
 
802
    if ram_we = '1' and ram2_ce = '1' and ram2_ub = '1' then
803
                ram2_data(15 downto 8) <= cpu_data_out;
804
         else
805
      ram2_data(15 downto 8)  <= "ZZZZZZZZ";
806
         end if;
807
 
808
         case cpu_addr(1 downto 0) is
809
         when "00" =>
810
      ram_data_out <= ram1_data(15 downto 8);
811
         when "01" =>
812
      ram_data_out <= ram1_data(7 downto 0);
813
         when "10" =>
814
      ram_data_out <= ram2_data(15 downto 8);
815
    when others =>
816
      ram_data_out <= ram2_data(7 downto 0);
817
    end case;
818
end process;
819
 
820
--
821
-- LEDS output register
822
--
823
led_output : process( cpu_clk, cpu_rst, switches )
824
begin
825
        if cpu_rst = '1' then
826
                leds <= (others=>'0');
827
        elsif cpu_clk'event and cpu_clk='0' then
828
                if      led_cs = '1' and cpu_rw = '0' then
829
                        leds <= cpu_data_out;
830
                end if;
831
        end if;
832
        led_data_out <= switches;
833
end process;
834
 
835
--
836
-- Interrupts and other bus control signals
837
--
838
interrupts : process(   rst_sw,
839
                                                                acia_irq,
840
                                                                kbd_irq,
841
                                                                nmi_sw
842
                                                         )
843
begin
844
   if sys_clk'event and sys_clk = '1' then
845
          cpu_rst  <= rst_sw; -- CPU reset is active high
846
   end if;
847
        cpu_firq   <= kbd_irq;
848
        cpu_nmi    <= nmi_sw;
849
        cpu_irq    <= acia_irq;
850
        cpu_halt   <= '0';
851
        cpu_hold   <= '0';
852
end process;
853
 
854
--
855
-- ACIA pin assignments
856
--
857
acia_assignments : process( rxd, acia_txd )
858
begin
859
        acia_dcd_n <= '0';
860
        acia_cts_n <= '0';
861
        acia_rxd   <= rxd;
862
        txd        <= acia_txd;
863
end process;
864
 
865
 
866
end my_computer; --===================== End of architecture =======================--
867
 

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