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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S1000/] [__projnav.log] - Blame information for rev 135

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1 105 davidgb 
Project Navigator Auto-Make Log File
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
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Entity  compiled.
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Entity  (Architecture ) compiled.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
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Entity  compiled.
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Entity  (Architecture ) compiled.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" Line 16. Undefined symbol 'clk_b'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" Line 16. clk_b: Undefined symbol (last report in this block)
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ERROR:HDLParsers:507 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" Line 15. ) is not a correct resolution function name
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ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" Line 16. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR
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-->
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Total memory usage is 81604 kilobytes
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Number of errors   :    4 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
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Architecture rtl of Entity cpu09 is up to date.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
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Architecture rtl of Entity dat_ram is up to date.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
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Entity  compiled.
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ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" Line 114. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR
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-->
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Total memory usage is 81604 kilobytes
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Number of errors   :    1 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
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Architecture rtl of Entity cpu09 is up to date.
99 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
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Architecture rtl of Entity dat_ram is up to date.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
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Entity  compiled.
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ERROR:HDLParsers:3452 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" Line 36. An index or element of the formal port DOPA of RAMB16_S18_S18 is missing in instantiation.
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-->
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Total memory usage is 81604 kilobytes
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Number of errors   :    1 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
135 
Architecture rtl of Entity cpu09 is up to date.
136 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
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Architecture rtl of Entity dat_ram is up to date.
138 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
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Entity  compiled.
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Entity  (Architecture ) compiled.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
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Entity  compiled.
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 94. Undefined symbol 'addr_lo'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 94. addr_lo: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 176. Undefined symbol 'my_mul32'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 176. my_mul32: Undefined symbol (last report in this block)
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ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 176. parse error, unexpected PROCESS, expecting OPENPAR or TICK or LSQBRACK
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 191. Undefined symbol 'mul_left_lo'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 191. mul_left_lo: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 192. Undefined symbol 'mul_right_hi'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 192. mul_right_hi: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 193. Undefined symbol 'mul_right_lo'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 193. mul_right_lo: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 194. Undefined symbol 'mul_out_0'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 194. mul_out_0: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 195. Undefined symbol 'mul_out_1'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 195. mul_out_1: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 196. Undefined symbol 'mul_out_2'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 196. mul_out_2: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 197. Undefined symbol 'mul_out_3'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 197. mul_out_3: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 198. Undefined symbol 'mul_out'.
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 198. mul_out: Undefined symbol (last report in this block)
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ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 210. parse error, unexpected PROCESS, expecting SEMICOLON
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-->
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Total memory usage is 82628 kilobytes
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Number of errors   :   22 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
196 
Architecture rtl of Entity cpu09 is up to date.
197 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
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Architecture rtl of Entity dat_ram is up to date.
199 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
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Architecture rtl of Entity dpr_2k is up to date.
201 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
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Entity  compiled.
203 
ERROR:HDLParsers:3313 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 194. Undefined symbol 'mult_right_hi'.  Should it be: mul_right_hi?
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 194. mult_right_hi: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3313 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 195. Undefined symbol 'mult_right_lo'.  Should it be: mul_right_lo?
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ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" Line 195. mult_right_lo: Undefined symbol (last report in this block)
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-->
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Total memory usage is 82628 kilobytes
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Number of errors   :    4 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
213 
Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
237 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
238 
Architecture rtl of Entity cpu09 is up to date.
239 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
240 
Architecture rtl of Entity dat_ram is up to date.
241 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
242 
Architecture rtl of Entity dpr_2k is up to date.
243 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
244 
Entity  compiled.
245 
Entity  (Architecture ) compiled.
246 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
247 
ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 43. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
248 
-->
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Total memory usage is 82628 kilobytes
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Number of errors   :    1 (   0 filtered)
253 
Number of warnings :    0 (   0 filtered)
254 
Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
277 
=========================================================================
278 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
279 
Architecture rtl of Entity cpu09 is up to date.
280 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
281 
Architecture rtl of Entity dat_ram is up to date.
282 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
283 
Architecture rtl of Entity dpr_2k is up to date.
284 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
285 
Architecture rtl of Entity mul32 is up to date.
286 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
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ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 43. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
288 
-->
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Total memory usage is 82628 kilobytes
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Number of errors   :    1 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
294 
Number of infos    :    0 (   0 filtered)
295 
 
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
301 
-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
317 
=========================================================================
318 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
319 
Architecture rtl of Entity cpu09 is up to date.
320 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
321 
Architecture rtl of Entity dat_ram is up to date.
322 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
323 
Architecture rtl of Entity dpr_2k is up to date.
324 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
325 
Architecture rtl of Entity mul32 is up to date.
326 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
327 
Entity  compiled.
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 159. Undefined symbol 'clk_b'.
329 
ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 159. clk_b: Undefined symbol (last report in this block)
330 
ERROR:HDLParsers:507 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 158. ) is not a correct resolution function name
331 
ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 159. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR
332 
-->
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Total memory usage is 82628 kilobytes
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Number of errors   :    4 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
361 
=========================================================================
362 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
363 
Architecture rtl of Entity cpu09 is up to date.
364 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
365 
Architecture rtl of Entity dat_ram is up to date.
366 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
367 
Architecture rtl of Entity dpr_2k is up to date.
368 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
369 
Architecture rtl of Entity mul32 is up to date.
370 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
371 
Entity  compiled.
372 
ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 253. parse error, unexpected CLOSEPAR
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ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 294. Undefined symbol 'data_in'.
374 
ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 294. data_in: Undefined symbol (last report in this block)
375 
ERROR:HDLParsers:3312 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 295. Undefined symbol 'cid_dato'.
376 
ERROR:HDLParsers:1209 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 295. cid_dato: Undefined symbol (last report in this block)
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ERROR:HDLParsers:800 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 333. Type of cpu_dati is incompatible with type of cpu_id.
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ERROR:HDLParsers:804 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 362. Size of concat operation is different than size of the target.
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ERROR:HDLParsers:1401 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 380. Object mem_dato of mode OUT can not be read.
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ERROR:HDLParsers:1402 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 392. Object mem_dati of mode IN can not be updated.
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ERROR:HDLParsers:1401 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 393. Object mem_dato of mode OUT can not be read.
382 
-->
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Total memory usage is 82628 kilobytes
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Number of errors   :   10 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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ERROR: XST failed
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Process "Synthesize" did not complete.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Synthesize".
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
412 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
413 
Architecture rtl of Entity cpu09 is up to date.
414 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
415 
Architecture rtl of Entity dat_ram is up to date.
416 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
417 
Architecture rtl of Entity dpr_2k is up to date.
418 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
419 
Architecture rtl of Entity mul32 is up to date.
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Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
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Entity  compiled.
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ERROR:HDLParsers:800 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 332. Type of cpu_dati is incompatible with type of cpu_id.
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ERROR:HDLParsers:804 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 361. Size of concat operation is different than size of the target.
424 
ERROR:HDLParsers:1401 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 379. Object mem_dato of mode OUT can not be read.
425 
ERROR:HDLParsers:1402 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 391. Object mem_dati of mode IN can not be updated.
426 
ERROR:HDLParsers:1401 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 392. Object mem_dato of mode OUT can not be read.
427 
-->
428 
 
429 
Total memory usage is 82628 kilobytes
430 
 
431 
Number of errors   :    5 (   0 filtered)
432 
Number of warnings :    0 (   0 filtered)
433 
Number of infos    :    0 (   0 filtered)
434 
 
435 
ERROR: XST failed
436 
Process "Synthesize" did not complete.
437 
 
438 
 
439 
Project Navigator Auto-Make Log File
440 
-------------------------------------
441 
 
442 
 
443 
 
444 
 
445 
 
446 
 
447 
 
448 
 
449 
 
450 
 
451 
Started process "Synthesize".
452 
 
453 
 
454 
=========================================================================
455 
*                          HDL Compilation                              *
456 
=========================================================================
457 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
458 
Architecture rtl of Entity cpu09 is up to date.
459 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
460 
Architecture rtl of Entity dat_ram is up to date.
461 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
462 
Architecture rtl of Entity dpr_2k is up to date.
463 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
464 
Architecture rtl of Entity mul32 is up to date.
465 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
466 
Entity  compiled.
467 
ERROR:HDLParsers:800 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 332. Type of cpu_dati is incompatible with type of cpu_id.
468 
ERROR:HDLParsers:1401 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 379. Object mem_dato of mode OUT can not be read.
469 
-->
470 
 
471 
Total memory usage is 82628 kilobytes
472 
 
473 
Number of errors   :    2 (   0 filtered)
474 
Number of warnings :    0 (   0 filtered)
475 
Number of infos    :    0 (   0 filtered)
476 
 
477 
ERROR: XST failed
478 
Process "Synthesize" did not complete.
479 
 
480 
 
481 
Project Navigator Auto-Make Log File
482 
-------------------------------------
483 
 
484 
 
485 
 
486 
 
487 
 
488 
 
489 
 
490 
 
491 
 
492 
 
493 
Started process "Synthesize".
494 
 
495 
 
496 
=========================================================================
497 
*                          HDL Compilation                              *
498 
=========================================================================
499 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
500 
Architecture rtl of Entity cpu09 is up to date.
501 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
502 
Architecture rtl of Entity dat_ram is up to date.
503 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
504 
Architecture rtl of Entity dpr_2k is up to date.
505 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
506 
Architecture rtl of Entity mul32 is up to date.
507 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
508 
Entity  compiled.
509 
ERROR:HDLParsers:800 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 333. Type of cpu_dati is incompatible with type of cpu_id.
510 
-->
511 
 
512 
Total memory usage is 82628 kilobytes
513 
 
514 
Number of errors   :    1 (   0 filtered)
515 
Number of warnings :    0 (   0 filtered)
516 
Number of infos    :    0 (   0 filtered)
517 
 
518 
ERROR: XST failed
519 
Process "Synthesize" did not complete.
520 
 
521 
 
522 
Project Navigator Auto-Make Log File
523 
-------------------------------------
524 
 
525 
 
526 
 
527 
 
528 
 
529 
 
530 
 
531 
 
532 
 
533 
 
534 
Started process "Synthesize".
535 
 
536 
 
537 
=========================================================================
538 
*                          HDL Compilation                              *
539 
=========================================================================
540 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
541 
Architecture rtl of Entity cpu09 is up to date.
542 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
543 
Architecture rtl of Entity dat_ram is up to date.
544 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
545 
Architecture rtl of Entity dpr_2k is up to date.
546 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
547 
Architecture rtl of Entity mul32 is up to date.
548 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
549 
ERROR:HDLParsers:3384 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 44. String literal "0000000" is not of size 8.
550 
ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 45. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
551 
-->
552 
 
553 
Total memory usage is 82628 kilobytes
554 
 
555 
Number of errors   :    2 (   0 filtered)
556 
Number of warnings :    0 (   0 filtered)
557 
Number of infos    :    0 (   0 filtered)
558 
 
559 
ERROR: XST failed
560 
Process "Synthesize" did not complete.
561 
 
562 
 
563 
Project Navigator Auto-Make Log File
564 
-------------------------------------
565 
 
566 
 
567 
 
568 
 
569 
 
570 
 
571 
 
572 
 
573 
 
574 
 
575 
Started process "Synthesize".
576 
 
577 
 
578 
=========================================================================
579 
*                          HDL Compilation                              *
580 
=========================================================================
581 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
582 
Architecture rtl of Entity cpu09 is up to date.
583 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
584 
Architecture rtl of Entity dat_ram is up to date.
585 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
586 
Architecture rtl of Entity dpr_2k is up to date.
587 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
588 
Architecture rtl of Entity mul32 is up to date.
589 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
590 
ERROR:HDLParsers:164 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" Line 45. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
591 
-->
592 
 
593 
Total memory usage is 82628 kilobytes
594 
 
595 
Number of errors   :    1 (   0 filtered)
596 
Number of warnings :    0 (   0 filtered)
597 
Number of infos    :    0 (   0 filtered)
598 
 
599 
ERROR: XST failed
600 
Process "Synthesize" did not complete.
601 
 
602 
 
603 
Project Navigator Auto-Make Log File
604 
-------------------------------------
605 
 
606 
 
607 
 
608 
 
609 
 
610 
 
611 
 
612 
 
613 
 
614 
 
615 
Started process "Synthesize".
616 
 
617 
 
618 
=========================================================================
619 
*                          HDL Compilation                              *
620 
=========================================================================
621 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
622 
Architecture rtl of Entity cpu09 is up to date.
623 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
624 
Architecture rtl of Entity dat_ram is up to date.
625 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
626 
Architecture rtl of Entity dpr_2k is up to date.
627 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
628 
Architecture rtl of Entity mul32 is up to date.
629 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
630 
Entity  compiled.
631 
Entity  (Architecture ) compiled.
632 
 
633 
=========================================================================
634 
*                            HDL Analysis                               *
635 
=========================================================================
636 
Analyzing Entity  (Architecture ).
637 
Entity  analyzed. Unit  generated.
638 
 
639 
Analyzing Entity  (Architecture ).
640 
Entity  analyzed. Unit  generated.
641 
 
642 
Analyzing Entity  (Architecture ).
643 
Entity  analyzed. Unit  generated.
644 
 
645 
Analyzing Entity  (Architecture ).
646 
Entity  analyzed. Unit  generated.
647 
 
648 
Analyzing Entity  (Architecture ).
649 
WARNING:Xst:1610 - "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" line 198: Width mismatch.  has a width of 64 bits but assigned expression is 208-bit wide.
650 
Entity  analyzed. Unit  generated.
651 
 
652 
 
653 
=========================================================================
654 
*                           HDL Synthesis                               *
655 
=========================================================================
656 
 
657 
Synthesizing Unit .
658 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd".
659 
    Found 8-bit 16-to-1 multiplexer for signal .
660 
    Found 18x18-bit multiplier for signal <$n0000> created at line 194.
661 
    Found 8-bit register for signal .
662 
    Found 8-bit register for signal .
663 
    Found 8-bit register for signal .
664 
    Found 8-bit register for signal .
665 
    Found 8-bit register for signal .
666 
    Found 8-bit register for signal .
667 
    Found 8-bit register for signal .
668 
    Found 8-bit register for signal .
669 
    Summary:
670 
        inferred  64 D-type flip-flop(s).
671 
        inferred   1 Multiplier(s).
672 
        inferred   8 Multiplexer(s).
673 
Unit  synthesized.
674 
 
675 
 
676 
Synthesizing Unit .
677 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd".
678 
Unit  synthesized.
679 
 
680 
 
681 
Synthesizing Unit .
682 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd".
683 
    Found 8-bit 16-to-1 multiplexer for signal <$n0000> created at line 176.
684 
    Found 8-bit 16-to-1 multiplexer for signal <$n0002>.
685 
    Found 8-bit 16-to-1 multiplexer for signal <$n0003>.
686 
    Found 8-bit 16-to-1 multiplexer for signal <$n0004>.
687 
    Found 8-bit 16-to-1 multiplexer for signal <$n0005>.
688 
    Found 8-bit 16-to-1 multiplexer for signal <$n0006>.
689 
    Found 8-bit 16-to-1 multiplexer for signal <$n0007>.
690 
    Found 8-bit 16-to-1 multiplexer for signal <$n0008>.
691 
    Found 8-bit 16-to-1 multiplexer for signal <$n0009>.
692 
    Found 8-bit 16-to-1 multiplexer for signal <$n0010>.
693 
    Found 8-bit 16-to-1 multiplexer for signal <$n0011>.
694 
    Found 8-bit 16-to-1 multiplexer for signal <$n0012>.
695 
    Found 8-bit 16-to-1 multiplexer for signal <$n0013>.
696 
    Found 8-bit 16-to-1 multiplexer for signal <$n0014>.
697 
    Found 8-bit 16-to-1 multiplexer for signal <$n0015>.
698 
    Found 8-bit 16-to-1 multiplexer for signal <$n0016>.
699 
    Found 8-bit 16-to-1 multiplexer for signal <$n0017>.
700 
    Found 8-bit register for signal .
701 
    Found 8-bit register for signal .
702 
    Found 8-bit register for signal .
703 
    Found 8-bit register for signal .
704 
    Found 8-bit register for signal .
705 
    Found 8-bit register for signal .
706 
    Found 8-bit register for signal .
707 
    Found 8-bit register for signal .
708 
    Found 8-bit register for signal .
709 
    Found 8-bit register for signal .
710 
    Found 8-bit register for signal .
711 
    Found 8-bit register for signal .
712 
    Found 8-bit register for signal .
713 
    Found 8-bit register for signal .
714 
    Found 8-bit register for signal .
715 
    Found 8-bit register for signal .
716 
    Summary:
717 
        inferred 136 Multiplexer(s).
718 
Unit  synthesized.
719 
 
720 
 
721 
Synthesizing Unit .
722 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd".
723 
    Using one-hot encoding for signal .
724 
    Using one-hot encoding for signal .
725 
    Using one-hot encoding for signal .
726 
    Using one-hot encoding for signal .
727 
    Using one-hot encoding for signal .
728 
    Using one-hot encoding for signal .
729 
    Using one-hot encoding for signal .
730 
    Using one-hot encoding for signal .
731 
    Using one-hot encoding for signal .
732 
    Using one-hot encoding for signal .
733 
    Using one-hot encoding for signal .
734 
    Using one-hot encoding for signal .
735 
    Using one-hot encoding for signal .
736 
    Using one-hot encoding for signal .
737 
    Using one-hot encoding for signal .
738 
    Using one-hot encoding for signal .
739 
    Using one-hot encoding for signal .
740 
    Using one-hot encoding for signal .
741 
    Using one-hot encoding for signal .
742 
    Using one-hot encoding for signal .
743 
    Using one-hot encoding for signal .
744 
    Found 16x8-bit ROM for signal <$n0058> created at line 1153.
745 
    Found 16x211-bit ROM for signal <$n0405>.
746 
    Found 16x66-bit ROM for signal <$n0406>.
747 
    Found 16x12-bit ROM for signal <$n0340> created at line 3917.
748 
    Found 16x6-bit ROM for signal <$n0346> created at line 2637.
749 
    Found 16-bit adder for signal <$n0003> created at line 457.
750 
    Found 12-bit shifter logical left for signal <$n0091> created at line 3199.
751 
    Found 16-bit addsub for signal <$n0278>.
752 
    Found 16-bit addsub for signal <$n0279>.
753 
    Found 5-bit 4-to-1 multiplexer for signal <$n0280> created at line 2833.
754 
    Found 5-bit 4-to-1 multiplexer for signal <$n0281> created at line 3501.
755 
    Found 5-bit 4-to-1 multiplexer for signal <$n0283> created at line 2029.
756 
    Found 5-bit 16-to-1 multiplexer for signal <$n0284> created at line 1843.
757 
    Found 16-bit 4-to-1 multiplexer for signal <$n0287> created at line 3137.
758 
    Found 38-bit 4-to-1 multiplexer for signal <$n0297> created at line 2833.
759 
    Found 38-bit 16-to-1 multiplexer for signal <$n0302> created at line 1843.
760 
    Found 4-bit 16-to-1 multiplexer for signal <$n0309> created at line 1843.
761 
    Found 4-bit 4-to-1 multiplexer for signal <$n0310>.
762 
    Found 10-bit 4-to-1 multiplexer for signal <$n0318> created at line 2833.
763 
    Found 10-bit 16-to-1 multiplexer for signal <$n0321> created at line 1843.
764 
    Found 10-bit 4-to-1 multiplexer for signal <$n0324> created at line 2931.
765 
    Found 12-bit 4-to-1 multiplexer for signal <$n0325> created at line 2833.
766 
    Found 12-bit shifter logical left for signal <$n0326> created at line 3559.
767 
    Found 12-bit shifter logical left for signal <$n0329> created at line 3404.
768 
    Found 12-bit 16-to-1 multiplexer for signal <$n0330> created at line 1548.
769 
    Found 12-bit 16-to-1 multiplexer for signal <$n0333> created at line 1684.
770 
    Found 12-bit 16-to-1 multiplexer for signal <$n0334> created at line 1843.
771 
    Found 6-bit 16-to-1 multiplexer for signal <$n0344> created at line 1843.
772 
    Found 6-bit 4-to-1 multiplexer for signal <$n0347> created at line 2833.
773 
    Found 5-bit 16-to-1 multiplexer for signal <$n0351> created at line 1548.
774 
    Found 5-bit 4-to-1 multiplexer for signal <$n0352>.
775 
    Found 5-bit 16-to-1 multiplexer for signal <$n0354> created at line 1843.
776 
    Found 4-bit 4-to-1 multiplexer for signal <$n0363> created at line 3944.
777 
    Found 4-bit 4-to-1 multiplexer for signal <$n0364> created at line 4013.
778 
    Found 8-bit 16-to-1 multiplexer for signal <$n0373> created at line 1843.
779 
    Found 8-bit 16-to-1 multiplexer for signal <$n0379> created at line 3197.
780 
    Found 5-bit comparator lessequal for signal <$n0513> created at line 1151.
781 
    Found 5-bit comparator lessequal for signal <$n0514> created at line 1150.
782 
    Found 5-bit comparator lessequal for signal <$n0515> created at line 1168.
783 
    Found 1-bit xor2 for signal <$n0980> created at line 3822.
784 
    Found 1-bit xor2 for signal <$n1240> created at line 1398.
785 
    Found 1-bit xor2 for signal <$n1241> created at line 1400.
786 
    Found 1-bit xor3 for signal <$n1242> created at line 1407.
787 
    Found 16-bit xor2 for signal <$n1482> created at line 1201.
788 
    Found 8-bit register for signal .
789 
    Found 8-bit register for signal .
790 
    Found 8-bit register for signal .
791 
    Found 8-bit register for signal .
792 
    Found 16-bit register for signal .
793 
    Found 3-bit register for signal .
794 
    Found 16-bit register for signal .
795 
    Found 1-bit register for signal .
796 
    Found 1-bit register for signal .
797 
    Found 1-bit register for signal .
798 
    Found 8-bit register for signal .
799 
    Found 16-bit register for signal .
800 
    Found 8-bit register for signal .
801 
    Found 16-bit register for signal .
802 
    Found 8-bit register for signal .
803 
    Found 24-bit register for signal .
804 
    Found 16-bit register for signal .
805 
    Found 16-bit register for signal .
806 
    Found 16-bit register for signal .
807 
    Summary:
808 
        inferred   5 ROM(s).
809 
        inferred 198 D-type flip-flop(s).
810 
        inferred   3 Adder/Subtractor(s).
811 
        inferred   3 Comparator(s).
812 
        inferred 249 Multiplexer(s).
813 
        inferred   3 Combinational logic shifter(s).
814 
        inferred   1 Xor(s).
815 
Unit  synthesized.
816 
 
817 
 
818 
Synthesizing Unit .
819 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd".
820 
WARNING:Xst:653 - Signal  is used but never assigned. Tied to value 0.
821 
WARNING:Xst:646 - Signal > is assigned but never used.
822 
WARNING:Xst:646 - Signal > is assigned but never used.
823 
WARNING:Xst:646 - Signal > is assigned but never used.
824 
WARNING:Xst:646 - Signal > is assigned but never used.
825 
WARNING:Xst:646 - Signal > is assigned but never used.
826 
WARNING:Xst:646 - Signal > is assigned but never used.
827 
WARNING:Xst:1780 - Signal  is never used or assigned.
828 
    Found 8-bit comparator equal for signal <$n0015> created at line 389.
829 
    Found 12-bit comparator equal for signal <$n0016> created at line 389.
830 
    Found 8-bit comparator not equal for signal <$n0017> created at line 369.
831 
    Found 12-bit comparator not equal for signal <$n0018> created at line 369.
832 
    Found 1-bit 4-to-1 multiplexer for signal .
833 
    Summary:
834 
        inferred   4 Comparator(s).
835 
        inferred   1 Multiplexer(s).
836 
Unit  synthesized.
837 
 
838 
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
839 
 
840 
=========================================================================
841 
*                       Advanced HDL Synthesis                          *
842 
=========================================================================
843 
 
844 
Advanced RAM inference ...
845 
Advanced multiplier inference ...
846 
Advanced Registered AddSub inference ...
847 
Dynamic shift register inference ...
848 
 
849 
=========================================================================
850 
HDL Synthesis Report
851 
 
852 
Macro Statistics
853 
# ROMs                             : 5
854 
 16x12-bit ROM                     : 1
855 
 16x211-bit ROM                    : 1
856 
 16x6-bit ROM                      : 1
857 
 16x66-bit ROM                     : 1
858 
 16x8-bit ROM                      : 1
859 
# Multipliers                      : 1
860 
 18x18-bit multiplier              : 1
861 
# Adders/Subtractors               : 3
862 
 16-bit adder                      : 1
863 
 16-bit addsub                     : 2
864 
# Registers                        : 150
865 
 1-bit register                    : 115
866 
 3-bit register                    : 1
867 
 8-bit register                    : 34
868 
# Comparators                      : 7
869 
 12-bit comparator equal           : 1
870 
 12-bit comparator not equal       : 1
871 
 5-bit comparator lessequal        : 3
872 
 8-bit comparator equal            : 1
873 
 8-bit comparator not equal        : 1
874 
# Multiplexers                     : 44
875 
 1-bit 4-to-1 multiplexer          : 1
876 
 10-bit 16-to-1 multiplexer        : 1
877 
 10-bit 4-to-1 multiplexer         : 2
878 
 12-bit 16-to-1 multiplexer        : 3
879 
 12-bit 4-to-1 multiplexer         : 1
880 
 16-bit 4-to-1 multiplexer         : 1
881 
 38-bit 16-to-1 multiplexer        : 1
882 
 38-bit 4-to-1 multiplexer         : 1
883 
 4-bit 16-to-1 multiplexer         : 1
884 
 4-bit 4-to-1 multiplexer          : 3
885 
 5-bit 16-to-1 multiplexer         : 3
886 
 5-bit 4-to-1 multiplexer          : 4
887 
 6-bit 16-to-1 multiplexer         : 1
888 
 6-bit 4-to-1 multiplexer          : 1
889 
 8-bit 16-to-1 multiplexer         : 20
890 
# Logic shifters                   : 3
891 
 12-bit shifter logical left       : 3
892 
# Xors                             : 5
893 
 1-bit xor2                        : 3
894 
 1-bit xor3                        : 1
895 
 16-bit xor2                       : 1
896 
 
897 
=========================================================================
898 
 
899 
=========================================================================
900 
*                         Low Level Synthesis                           *
901 
=========================================================================
902 
WARNING:Xst:1989 - Unit : instances ,  of unit  are equivalent, second instance is removed
903 
 
904 
Optimizing unit  ...
905 
 
906 
Optimizing unit  ...
907 
 
908 
Optimizing unit  ...
909 
 
910 
Optimizing unit  ...
911 
Loading device for application Rf_Device from file '3s1000.nph' in environment C:/Xilinx_ISE_7.1.
912 
 
913 
Mapping all equations...
914 
Building and optimizing final netlist ...
915 
Found area constraint ratio of 100 (+ 5) on block my_unicpu09, actual ratio is 21.
916 
FlipFlop my_cpu/ea_5 has been replicated 1 time(s)
917 
FlipFlop my_cpu/ea_6 has been replicated 1 time(s)
918 
FlipFlop my_cpu/md_0 has been replicated 3 time(s)
919 
FlipFlop my_cpu/md_1 has been replicated 2 time(s)
920 
FlipFlop my_cpu/md_2 has been replicated 3 time(s)
921 
FlipFlop my_cpu/md_3 has been replicated 3 time(s)
922 
FlipFlop my_cpu/md_4 has been replicated 2 time(s)
923 
FlipFlop my_cpu/md_5 has been replicated 2 time(s)
924 
FlipFlop my_cpu/md_6 has been replicated 2 time(s)
925 
FlipFlop my_cpu/md_7 has been replicated 3 time(s)
926 
FlipFlop my_cpu/op_code_0 has been replicated 2 time(s)
927 
FlipFlop my_cpu/op_code_1 has been replicated 2 time(s)
928 
FlipFlop my_cpu/op_code_2 has been replicated 3 time(s)
929 
FlipFlop my_cpu/op_code_3 has been replicated 2 time(s)
930 
FlipFlop my_cpu/op_code_4 has been replicated 2 time(s)
931 
FlipFlop my_cpu/op_code_5 has been replicated 2 time(s)
932 
FlipFlop my_cpu/op_code_6 has been replicated 2 time(s)
933 
FlipFlop my_cpu/op_code_7 has been replicated 2 time(s)
934 
FlipFlop my_cpu/state_0 has been replicated 10 time(s)
935 
FlipFlop my_cpu/state_1 has been replicated 10 time(s)
936 
FlipFlop my_cpu/state_2 has been replicated 9 time(s)
937 
FlipFlop my_cpu/state_3 has been replicated 9 time(s)
938 
FlipFlop my_cpu/state_4 has been replicated 11 time(s)
939 
FlipFlop my_cpu/state_5 has been replicated 9 time(s)
940 
FlipFlop my_cpu/state_6 has been replicated 12 time(s)
941 
FlipFlop my_cpu/state_7 has been replicated 6 time(s)
942 
PACKER Warning: Lut my_cpu/cpu09__n0279<1>lut driving carry my_cpu/cpu09__n0279<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
943 
PACKER Warning: Lut my_cpu/cpu09__n0279<5>lut driving carry my_cpu/cpu09__n0279<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
944 
PACKER Warning: Lut my_cpu/cpu09__n0279<6>lut driving carry my_cpu/cpu09__n0279<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
945 
PACKER Warning: Lut my_cpu/cpu09__n0279<7>lut driving carry my_cpu/cpu09__n0279<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
946 
PACKER Warning: Lut my_cpu/cpu09__n0279<13>lut driving carry my_cpu/cpu09__n0279<13>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
947 
PACKER Warning: Lut my_cpu/cpu09__n0278<3>lut driving carry my_cpu/cpu09__n0278<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
948 
PACKER Warning: Lut my_cpu/cpu09__n0278<4>lut driving carry my_cpu/cpu09__n0278<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
949 
PACKER Warning: Lut my_cpu/cpu09__n0278<5>lut driving carry my_cpu/cpu09__n0278<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
950 
PACKER Warning: Lut my_cpu/cpu09__n0278<6>lut driving carry my_cpu/cpu09__n0278<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
951 
PACKER Warning: Lut my_cpu/cpu09__n0278<7>lut driving carry my_cpu/cpu09__n0278<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
952 
PACKER Warning: Lut my_cpu/cpu09__n0278<8>lut driving carry my_cpu/cpu09__n0278<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
953 
PACKER Warning: Lut my_cpu/cpu09__n0278<9>lut driving carry my_cpu/cpu09__n0278<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
954 
PACKER Warning: Lut my_cpu/cpu09__n0278<10>lut driving carry my_cpu/cpu09__n0278<10>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
955 
PACKER Warning: Lut my_cpu/cpu09__n0278<11>lut driving carry my_cpu/cpu09__n0278<11>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
956 
PACKER Warning: Lut my_cpu/cpu09__n0278<12>lut driving carry my_cpu/cpu09__n0278<12>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
957 
PACKER Warning: Lut my_cpu/cpu09__n0278<13>lut driving carry my_cpu/cpu09__n0278<13>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
958 
PACKER Warning: Lut my_cpu/cpu09__n0278<14>lut driving carry my_cpu/cpu09__n0278<14>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
959 
 
960 
=========================================================================
961 
*                            Final Report                               *
962 
=========================================================================
963 
 
964 
Device utilization summary:
965 
---------------------------
966 
 
967 
Selected Device : 3s1000ft256-5
968 
 
969 
 Number of Slices:                    1665  out of   7680    21%
970 
 Number of Slice Flip Flops:           505  out of  15360     3%
971 
 Number of 4 input LUTs:              3084  out of  15360    20%
972 
 Number of bonded IOBs:                 67  out of    173    38%
973 
 Number of BRAMs:                        3  out of     24    12%
974 
 Number of MULT18X18s:                   1  out of     24     4%
975 
 Number of GCLKs:                        1  out of      8    12%
976 
 
977 
 
978 
=========================================================================
979 
TIMING REPORT
980 
 
981 
 
982 
Clock Information:
983 
------------------
984 
-----------------------------------+------------------------+-------+
985 
Clock Signal                       | Clock buffer(FF name)  | Load  |
986 
-----------------------------------+------------------------+-------+
987 
clk                                | BUFGP                  | 508   |
988 
-----------------------------------+------------------------+-------+
989 
 
990 
Timing Summary:
991 
---------------
992 
Speed Grade: -5
993 
 
994 
   Minimum period: 28.328ns (Maximum Frequency: 35.301MHz)
995 
   Minimum input arrival time before clock: 11.983ns
996 
   Maximum output required time after clock: 25.036ns
997 
   Maximum combinational path delay: No path found
998 
 
999 
=========================================================================
1000 
 
1001 
 
1002 
 
1003 
 
1004 
Started process "Translate".
1005 
 
1006 
PMSPEC -- Overriding Xilinx file
1007 
with local file
1008 
 
1009 
Command Line: ngdbuild -intstyle ise -dd
1010 
c:\vhdl\system09\rtl\system09_digilent_3s1000/_ngo -nt timestamp -i -p
1011 
xc3s1000-ft256-5 my_unicpu09.ngc my_unicpu09.ngd
1012 
 
1013 
Reading NGO file 'C:/Vhdl/System09/rtl/System09_Digilent_3S1000/my_unicpu09.ngc'
1014 
...
1015 
 
1016 
Checking timing specifications ...
1017 
Checking expanded design ...
1018 
 
1019 
NGDBUILD Design Results Summary:
1020 
  Number of errors:     0
1021 
  Number of warnings:   0
1022 
 
1023 
Writing NGD file "my_unicpu09.ngd" ...
1024 
 
1025 
Writing NGDBUILD log file "my_unicpu09.bld"...
1026 
 
1027 
NGDBUILD done.
1028 
 
1029 
 
1030 
 
1031 
 
1032 
Started process "Map".
1033 
 
1034 
PMSPEC -- Overriding Xilinx file
1035 
with local file
1036 
Using target part "3s1000ft256-5".
1037 
Mapping design into LUTs...
1038 
Running directed packing...
1039 
Running delay-based LUT packing...
1040 
Running related packing...
1041 
 
1042 
Design Summary:
1043 
Number of errors:      0
1044 
Number of warnings:    0
1045 
Logic Utilization:
1046 
  Number of Slice Flip Flops:         505 out of  15,360    3%
1047 
  Number of 4 input LUTs:           3,070 out of  15,360   19%
1048 
Logic Distribution:
1049 
  Number of occupied Slices:                        1,706 out of   7,680   22%
1050 
    Number of Slices containing only related logic:   1,706 out of   1,706  100%
1051 
    Number of Slices containing unrelated logic:          0 out of   1,706    0%
1052 
      *See NOTES below for an explanation of the effects of unrelated logic
1053 
Total Number 4 input LUTs:          3,085 out of  15,360   20%
1054 
  Number used as logic:              3,070
1055 
  Number used as a route-thru:          15
1056 
  Number of bonded IOBs:               67 out of     173   38%
1057 
  Number of Block RAMs:                3 out of      24   12%
1058 
  Number of MULT18X18s:                1 out of      24    4%
1059 
  Number of GCLKs:                     1 out of       8   12%
1060 
 
1061 
Total equivalent gate count for design:  223,800
1062 
Additional JTAG gate count for IOBs:  3,216
1063 
Peak Memory Usage:  136 MB
1064 
 
1065 
NOTES:
1066 
 
1067 
   Related logic is defined as being logic that shares connectivity - e.g. two
1068 
   LUTs are "related" if they share common inputs.  When assembling slices,
1069 
   Map gives priority to combine logic that is related.  Doing so results in
1070 
   the best timing performance.
1071 
 
1072 
   Unrelated logic shares no connectivity.  Map will only begin packing
1073 
   unrelated logic into a slice once 99% of the slices are occupied through
1074 
   related logic packing.
1075 
 
1076 
   Note that once logic distribution reaches the 99% level through related
1077 
   logic packing, this does not mean the device is completely utilized.
1078 
   Unrelated logic packing will then begin, continuing until all usable LUTs
1079 
   and FFs are occupied.  Depending on your timing budget, increased levels of
1080 
   unrelated logic packing may adversely affect the overall timing performance
1081 
   of your design.
1082 
 
1083 
Mapping completed.
1084 
See MAP report file "my_unicpu09_map.mrp" for details.
1085 
 
1086 
 
1087 
 
1088 
 
1089 
Started process "Place & Route".
1090 
 
1091 
 
1092 
 
1093 
 
1094 
Constraints file: my_unicpu09.pcf.
1095 
PMSPEC -- Overriding Xilinx file
1096 
with local file
1097 
Loading device for application Rf_Device from file '3s1000.nph' in environment
1098 
C:/Xilinx_ISE_7.1.
1099 
   "my_unicpu09" is an NCD, version 3.1, device xc3s1000, package ft256, speed
1100 
-5
1101 
 
1102 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
1103 
Celsius)
1104 
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
1105 
 
1106 
 
1107 
Device speed data version:  "PRODUCTION 1.37 2005-07-22".
1108 
 
1109 
 
1110 
Device Utilization Summary:
1111 
 
1112 
   Number of BUFGMUXs                  1 out of 8      12%
1113 
   Number of External IOBs            67 out of 173    38%
1114 
      Number of LOCed IOBs             0 out of 67      0%
1115 
 
1116 
   Number of MULT18X18s                1 out of 24      4%
1117 
   Number of RAMB16s                   3 out of 24     12%
1118 
   Number of Slices                 1706 out of 7680   22%
1119 
      Number of SLICEMs                8 out of 3840    1%
1120 
 
1121 
 
1122 
 
1123 
Overall effort level (-ol):   Standard (set by user)
1124 
Placer effort level (-pl):    Standard (set by user)
1125 
Placer cost table entry (-t): 1
1126 
Router effort level (-rl):    Standard (set by user)
1127 
 
1128 
 
1129 
Starting Placer
1130 
 
1131 
Phase 1.1
1132 
Phase 1.1 (Checksum:98e117) REAL time: 1 secs
1133 
 
1134 
Phase 2.31
1135 
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
1136 
 
1137 
Phase 3.2
1138 
.
1139 
 
1140 
 
1141 
Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs
1142 
 
1143 
Phase 4.3
1144 
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs
1145 
 
1146 
Phase 5.5
1147 
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs
1148 
 
1149 
Phase 6.8
1150 
....................................
1151 
Phase 6.8 (Checksum:e635dd) REAL time: 3 secs
1152 
 
1153 
Phase 7.5
1154 
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs
1155 
 
1156 
Phase 8.18
1157 
Phase 8.18 (Checksum:4c4b3f8) REAL time: 5 secs
1158 
 
1159 
Phase 9.5
1160 
Phase 9.5 (Checksum:55d4a77) REAL time: 5 secs
1161 
 
1162 
Writing design to file my_unicpu09.ncd
1163 
 
1164 
 
1165 
Total REAL time to Placer completion: 5 secs
1166 
Total CPU time to Placer completion: 5 secs
1167 
 
1168 
Starting Router
1169 
 
1170 
Phase 1: 12874 unrouted;       REAL time: 6 secs
1171 
 
1172 
Phase 2: 12434 unrouted;       REAL time: 6 secs
1173 
 
1174 
Phase 3: 4732 unrouted;       REAL time: 7 secs
1175 
 
1176 
Phase 4: 0 unrouted;       REAL time: 9 secs
1177 
 
1178 
 
1179 
Total REAL time to Router completion: 9 secs
1180 
Total CPU time to Router completion: 9 secs
1181 
 
1182 
Generating "PAR" statistics.
1183 
 
1184 
**************************
1185 
Generating Clock Report
1186 
**************************
1187 
 
1188 
+---------------------+--------------+------+------+------------+-------------+
1189 
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
1190 
+---------------------+--------------+------+------+------------+-------------+
1191 
|           clk_BUFGP |      BUFGMUX5| No   |  406 |  0.406     |  1.023      |
1192 
+---------------------+--------------+------+------+------------+-------------+
1193 
 
1194 
Generating Pad Report.
1195 
 
1196 
All signals are completely routed.
1197 
 
1198 
Total REAL time to PAR completion: 11 secs
1199 
Total CPU time to PAR completion: 10 secs
1200 
 
1201 
Peak Memory Usage:  111 MB
1202 
 
1203 
Placement: Completed - No errors found.
1204 
Routing: Completed - No errors found.
1205 
 
1206 
Number of error messages: 0
1207 
Number of warning messages: 0
1208 
Number of info messages: 1
1209 
 
1210 
Writing design to file my_unicpu09.ncd
1211 
 
1212 
 
1213 
 
1214 
PAR done!
1215 
 
1216 
Started process "Generate Post-Place & Route Static Timing".
1217 
 
1218 
PMSPEC -- Overriding Xilinx file
1219 
with local file
1220 
Loading device for application Rf_Device from file '3s1000.nph' in environment
1221 
C:/Xilinx_ISE_7.1.
1222 
   "my_unicpu09" is an NCD, version 3.1, device xc3s1000, package ft256, speed
1223 
-5
1224 
 
1225 
Analysis completed Sun Sep 07 22:57:50 2008
1226 
--------------------------------------------------------------------------------
1227 
 
1228 
Generating Report ...
1229 
 
1230 
Number of warnings: 0
1231 
Total time: 5 secs
1232 
 
1233 
 
1234 
 
1235 
 
1236 
 
1237 
 
1238 
 
1239 
Started process "Programming File Generation Report".
1240 
 
1241 
 
1242 
 
1243 
Project Navigator Auto-Make Log File
1244 
-------------------------------------
1245 
 
1246 
 
1247 
 
1248 
 
1249 
 
1250 
 
1251 
 
1252 
 
1253 
 
1254 
 
1255 
Started process "Synthesize".
1256 
 
1257 
 
1258 
=========================================================================
1259 
*                          HDL Compilation                              *
1260 
=========================================================================
1261 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd" in Library work.
1262 
Architecture rtl of Entity cpu09 is up to date.
1263 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd" in Library work.
1264 
Architecture rtl of Entity dat_ram is up to date.
1265 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd" in Library work.
1266 
Architecture rtl of Entity dpr_2k is up to date.
1267 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd" in Library work.
1268 
Entity  compiled.
1269 
Entity  (Architecture ) compiled.
1270 
Compiling vhdl file "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd" in Library work.
1271 
Architecture rtl of Entity my_unicpu09 is up to date.
1272 
 
1273 
=========================================================================
1274 
*                            HDL Analysis                               *
1275 
=========================================================================
1276 
Analyzing Entity  (Architecture ).
1277 
Entity  analyzed. Unit  generated.
1278 
 
1279 
Analyzing Entity  (Architecture ).
1280 
Entity  analyzed. Unit  generated.
1281 
 
1282 
Analyzing Entity  (Architecture ).
1283 
Entity  analyzed. Unit  generated.
1284 
 
1285 
Analyzing Entity  (Architecture ).
1286 
Entity  analyzed. Unit  generated.
1287 
 
1288 
Analyzing Entity  (Architecture ).
1289 
Entity  analyzed. Unit  generated.
1290 
 
1291 
 
1292 
=========================================================================
1293 
*                           HDL Synthesis                               *
1294 
=========================================================================
1295 
 
1296 
Synthesizing Unit .
1297 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/mul32.vhd".
1298 
    Found 8-bit 16-to-1 multiplexer for signal .
1299 
    Found 18x18-bit multiplier for signal <$n0000> created at line 194.
1300 
    Found 18x18-bit multiplier for signal <$n0001> created at line 195.
1301 
    Found 18x18-bit multiplier for signal <$n0002> created at line 196.
1302 
    Found 18x18-bit multiplier for signal <$n0003> created at line 197.
1303 
    Found 64-bit adder for signal <$n0004> created at line 198.
1304 
    Found 64-bit adder for signal <$n0013>.
1305 
    Found 64-bit adder for signal <$n0014>.
1306 
    Found 8-bit register for signal .
1307 
    Found 8-bit register for signal .
1308 
    Found 8-bit register for signal .
1309 
    Found 8-bit register for signal .
1310 
    Found 8-bit register for signal .
1311 
    Found 8-bit register for signal .
1312 
    Found 8-bit register for signal .
1313 
    Found 8-bit register for signal .
1314 
    Summary:
1315 
        inferred  64 D-type flip-flop(s).
1316 
        inferred   3 Adder/Subtractor(s).
1317 
        inferred   4 Multiplier(s).
1318 
        inferred   8 Multiplexer(s).
1319 
Unit  synthesized.
1320 
 
1321 
 
1322 
Synthesizing Unit .
1323 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../Spartan3/dpr2k_b16.vhd".
1324 
Unit  synthesized.
1325 
 
1326 
 
1327 
Synthesizing Unit .
1328 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/datram.vhd".
1329 
    Found 8-bit 16-to-1 multiplexer for signal <$n0000> created at line 176.
1330 
    Found 8-bit 16-to-1 multiplexer for signal <$n0002>.
1331 
    Found 8-bit 16-to-1 multiplexer for signal <$n0003>.
1332 
    Found 8-bit 16-to-1 multiplexer for signal <$n0004>.
1333 
    Found 8-bit 16-to-1 multiplexer for signal <$n0005>.
1334 
    Found 8-bit 16-to-1 multiplexer for signal <$n0006>.
1335 
    Found 8-bit 16-to-1 multiplexer for signal <$n0007>.
1336 
    Found 8-bit 16-to-1 multiplexer for signal <$n0008>.
1337 
    Found 8-bit 16-to-1 multiplexer for signal <$n0009>.
1338 
    Found 8-bit 16-to-1 multiplexer for signal <$n0010>.
1339 
    Found 8-bit 16-to-1 multiplexer for signal <$n0011>.
1340 
    Found 8-bit 16-to-1 multiplexer for signal <$n0012>.
1341 
    Found 8-bit 16-to-1 multiplexer for signal <$n0013>.
1342 
    Found 8-bit 16-to-1 multiplexer for signal <$n0014>.
1343 
    Found 8-bit 16-to-1 multiplexer for signal <$n0015>.
1344 
    Found 8-bit 16-to-1 multiplexer for signal <$n0016>.
1345 
    Found 8-bit 16-to-1 multiplexer for signal <$n0017>.
1346 
    Found 8-bit register for signal .
1347 
    Found 8-bit register for signal .
1348 
    Found 8-bit register for signal .
1349 
    Found 8-bit register for signal .
1350 
    Found 8-bit register for signal .
1351 
    Found 8-bit register for signal .
1352 
    Found 8-bit register for signal .
1353 
    Found 8-bit register for signal .
1354 
    Found 8-bit register for signal .
1355 
    Found 8-bit register for signal .
1356 
    Found 8-bit register for signal .
1357 
    Found 8-bit register for signal .
1358 
    Found 8-bit register for signal .
1359 
    Found 8-bit register for signal .
1360 
    Found 8-bit register for signal .
1361 
    Found 8-bit register for signal .
1362 
    Summary:
1363 
        inferred 136 Multiplexer(s).
1364 
Unit  synthesized.
1365 
 
1366 
 
1367 
Synthesizing Unit .
1368 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/cpu09.vhd".
1369 
    Using one-hot encoding for signal .
1370 
    Using one-hot encoding for signal .
1371 
    Using one-hot encoding for signal .
1372 
    Using one-hot encoding for signal .
1373 
    Using one-hot encoding for signal .
1374 
    Using one-hot encoding for signal .
1375 
    Using one-hot encoding for signal .
1376 
    Using one-hot encoding for signal .
1377 
    Using one-hot encoding for signal .
1378 
    Using one-hot encoding for signal .
1379 
    Using one-hot encoding for signal .
1380 
    Using one-hot encoding for signal .
1381 
    Using one-hot encoding for signal .
1382 
    Using one-hot encoding for signal .
1383 
    Using one-hot encoding for signal .
1384 
    Using one-hot encoding for signal .
1385 
    Using one-hot encoding for signal .
1386 
    Using one-hot encoding for signal .
1387 
    Using one-hot encoding for signal .
1388 
    Using one-hot encoding for signal .
1389 
    Using one-hot encoding for signal .
1390 
    Found 16x8-bit ROM for signal <$n0058> created at line 1153.
1391 
    Found 16x211-bit ROM for signal <$n0405>.
1392 
    Found 16x66-bit ROM for signal <$n0406>.
1393 
    Found 16x12-bit ROM for signal <$n0340> created at line 3917.
1394 
    Found 16x6-bit ROM for signal <$n0346> created at line 2637.
1395 
    Found 16-bit adder for signal <$n0003> created at line 457.
1396 
    Found 12-bit shifter logical left for signal <$n0091> created at line 3199.
1397 
    Found 16-bit addsub for signal <$n0278>.
1398 
    Found 16-bit addsub for signal <$n0279>.
1399 
    Found 5-bit 4-to-1 multiplexer for signal <$n0280> created at line 2833.
1400 
    Found 5-bit 4-to-1 multiplexer for signal <$n0281> created at line 3501.
1401 
    Found 5-bit 4-to-1 multiplexer for signal <$n0283> created at line 2029.
1402 
    Found 5-bit 16-to-1 multiplexer for signal <$n0284> created at line 1843.
1403 
    Found 16-bit 4-to-1 multiplexer for signal <$n0287> created at line 3137.
1404 
    Found 38-bit 4-to-1 multiplexer for signal <$n0297> created at line 2833.
1405 
    Found 38-bit 16-to-1 multiplexer for signal <$n0302> created at line 1843.
1406 
    Found 4-bit 16-to-1 multiplexer for signal <$n0309> created at line 1843.
1407 
    Found 4-bit 4-to-1 multiplexer for signal <$n0310>.
1408 
    Found 10-bit 4-to-1 multiplexer for signal <$n0318> created at line 2833.
1409 
    Found 10-bit 16-to-1 multiplexer for signal <$n0321> created at line 1843.
1410 
    Found 10-bit 4-to-1 multiplexer for signal <$n0324> created at line 2931.
1411 
    Found 12-bit 4-to-1 multiplexer for signal <$n0325> created at line 2833.
1412 
    Found 12-bit shifter logical left for signal <$n0326> created at line 3559.
1413 
    Found 12-bit shifter logical left for signal <$n0329> created at line 3404.
1414 
    Found 12-bit 16-to-1 multiplexer for signal <$n0330> created at line 1548.
1415 
    Found 12-bit 16-to-1 multiplexer for signal <$n0333> created at line 1684.
1416 
    Found 12-bit 16-to-1 multiplexer for signal <$n0334> created at line 1843.
1417 
    Found 6-bit 16-to-1 multiplexer for signal <$n0344> created at line 1843.
1418 
    Found 6-bit 4-to-1 multiplexer for signal <$n0347> created at line 2833.
1419 
    Found 5-bit 16-to-1 multiplexer for signal <$n0351> created at line 1548.
1420 
    Found 5-bit 4-to-1 multiplexer for signal <$n0352>.
1421 
    Found 5-bit 16-to-1 multiplexer for signal <$n0354> created at line 1843.
1422 
    Found 4-bit 4-to-1 multiplexer for signal <$n0363> created at line 3944.
1423 
    Found 4-bit 4-to-1 multiplexer for signal <$n0364> created at line 4013.
1424 
    Found 8-bit 16-to-1 multiplexer for signal <$n0373> created at line 1843.
1425 
    Found 8-bit 16-to-1 multiplexer for signal <$n0379> created at line 3197.
1426 
    Found 5-bit comparator lessequal for signal <$n0513> created at line 1151.
1427 
    Found 5-bit comparator lessequal for signal <$n0514> created at line 1150.
1428 
    Found 5-bit comparator lessequal for signal <$n0515> created at line 1168.
1429 
    Found 1-bit xor2 for signal <$n0980> created at line 3822.
1430 
    Found 1-bit xor2 for signal <$n1240> created at line 1398.
1431 
    Found 1-bit xor2 for signal <$n1241> created at line 1400.
1432 
    Found 1-bit xor3 for signal <$n1242> created at line 1407.
1433 
    Found 16-bit xor2 for signal <$n1482> created at line 1201.
1434 
    Found 8-bit register for signal .
1435 
    Found 8-bit register for signal .
1436 
    Found 8-bit register for signal .
1437 
    Found 8-bit register for signal .
1438 
    Found 16-bit register for signal .
1439 
    Found 3-bit register for signal .
1440 
    Found 16-bit register for signal .
1441 
    Found 1-bit register for signal .
1442 
    Found 1-bit register for signal .
1443 
    Found 1-bit register for signal .
1444 
    Found 8-bit register for signal .
1445 
    Found 16-bit register for signal .
1446 
    Found 8-bit register for signal .
1447 
    Found 16-bit register for signal .
1448 
    Found 8-bit register for signal .
1449 
    Found 24-bit register for signal .
1450 
    Found 16-bit register for signal .
1451 
    Found 16-bit register for signal .
1452 
    Found 16-bit register for signal .
1453 
    Summary:
1454 
        inferred   5 ROM(s).
1455 
        inferred 198 D-type flip-flop(s).
1456 
        inferred   3 Adder/Subtractor(s).
1457 
        inferred   3 Comparator(s).
1458 
        inferred 249 Multiplexer(s).
1459 
        inferred   3 Combinational logic shifter(s).
1460 
        inferred   1 Xor(s).
1461 
Unit  synthesized.
1462 
 
1463 
 
1464 
Synthesizing Unit .
1465 
    Related source file is "C:/Vhdl/System09/rtl/System09_Digilent_3S1000/../VHDL/unicpu09.vhd".
1466 
WARNING:Xst:653 - Signal  is used but never assigned. Tied to value 0.
1467 
WARNING:Xst:646 - Signal > is assigned but never used.
1468 
WARNING:Xst:646 - Signal > is assigned but never used.
1469 
WARNING:Xst:646 - Signal > is assigned but never used.
1470 
WARNING:Xst:646 - Signal > is assigned but never used.
1471 
WARNING:Xst:646 - Signal > is assigned but never used.
1472 
WARNING:Xst:646 - Signal > is assigned but never used.
1473 
WARNING:Xst:1780 - Signal  is never used or assigned.
1474 
    Found 8-bit comparator equal for signal <$n0015> created at line 389.
1475 
    Found 12-bit comparator equal for signal <$n0016> created at line 389.
1476 
    Found 8-bit comparator not equal for signal <$n0017> created at line 369.
1477 
    Found 12-bit comparator not equal for signal <$n0018> created at line 369.
1478 
    Found 1-bit 4-to-1 multiplexer for signal .
1479 
    Summary:
1480 
        inferred   4 Comparator(s).
1481 
        inferred   1 Multiplexer(s).
1482 
Unit  synthesized.
1483 
 
1484 
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
1485 
 
1486 
=========================================================================
1487 
*                       Advanced HDL Synthesis                          *
1488 
=========================================================================
1489 
 
1490 
Advanced RAM inference ...
1491 
Advanced multiplier inference ...
1492 
Advanced Registered AddSub inference ...
1493 
Dynamic shift register inference ...
1494 
 
1495 
=========================================================================
1496 
HDL Synthesis Report
1497 
 
1498 
Macro Statistics
1499 
# ROMs                             : 5
1500 
 16x12-bit ROM                     : 1
1501 
 16x211-bit ROM                    : 1
1502 
 16x6-bit ROM                      : 1
1503 
 16x66-bit ROM                     : 1
1504 
 16x8-bit ROM                      : 1
1505 
# Multipliers                      : 4
1506 
 18x18-bit multiplier              : 4
1507 
# Adders/Subtractors               : 6
1508 
 16-bit adder                      : 1
1509 
 16-bit addsub                     : 2
1510 
 64-bit adder                      : 3
1511 
# Registers                        : 150
1512 
 1-bit register                    : 115
1513 
 3-bit register                    : 1
1514 
 8-bit register                    : 34
1515 
# Comparators                      : 7
1516 
 12-bit comparator equal           : 1
1517 
 12-bit comparator not equal       : 1
1518 
 5-bit comparator lessequal        : 3
1519 
 8-bit comparator equal            : 1
1520 
 8-bit comparator not equal        : 1
1521 
# Multiplexers                     : 44
1522 
 1-bit 4-to-1 multiplexer          : 1
1523 
 10-bit 16-to-1 multiplexer        : 1
1524 
 10-bit 4-to-1 multiplexer         : 2
1525 
 12-bit 16-to-1 multiplexer        : 3
1526 
 12-bit 4-to-1 multiplexer         : 1
1527 
 16-bit 4-to-1 multiplexer         : 1
1528 
 38-bit 16-to-1 multiplexer        : 1
1529 
 38-bit 4-to-1 multiplexer         : 1
1530 
 4-bit 16-to-1 multiplexer         : 1
1531 
 4-bit 4-to-1 multiplexer          : 3
1532 
 5-bit 16-to-1 multiplexer         : 3
1533 
 5-bit 4-to-1 multiplexer          : 4
1534 
 6-bit 16-to-1 multiplexer         : 1
1535 
 6-bit 4-to-1 multiplexer          : 1
1536 
 8-bit 16-to-1 multiplexer         : 20
1537 
# Logic shifters                   : 3
1538 
 12-bit shifter logical left       : 3
1539 
# Xors                             : 5
1540 
 1-bit xor2                        : 3
1541 
 1-bit xor3                        : 1
1542 
 16-bit xor2                       : 1
1543 
 
1544 
=========================================================================
1545 
 
1546 
=========================================================================
1547 
*                         Low Level Synthesis                           *
1548 
=========================================================================
1549 
WARNING:Xst:1989 - Unit : instances ,  of unit  are equivalent, second instance is removed
1550 
 
1551 
Optimizing unit  ...
1552 
 
1553 
Optimizing unit  ...
1554 
 
1555 
Optimizing unit  ...
1556 
 
1557 
Optimizing unit  ...
1558 
Loading device for application Rf_Device from file '3s1000.nph' in environment C:/Xilinx_ISE_7.1.
1559 
 
1560 
Mapping all equations...
1561 
Building and optimizing final netlist ...
1562 
Found area constraint ratio of 100 (+ 5) on block my_unicpu09, actual ratio is 21.
1563 
FlipFlop my_cpu/ea_5 has been replicated 1 time(s)
1564 
FlipFlop my_cpu/ea_6 has been replicated 1 time(s)
1565 
FlipFlop my_cpu/md_0 has been replicated 3 time(s)
1566 
FlipFlop my_cpu/md_1 has been replicated 3 time(s)
1567 
FlipFlop my_cpu/md_2 has been replicated 2 time(s)
1568 
FlipFlop my_cpu/md_3 has been replicated 3 time(s)
1569 
FlipFlop my_cpu/md_4 has been replicated 1 time(s)
1570 
FlipFlop my_cpu/md_5 has been replicated 1 time(s)
1571 
FlipFlop my_cpu/md_6 has been replicated 1 time(s)
1572 
FlipFlop my_cpu/md_7 has been replicated 2 time(s)
1573 
FlipFlop my_cpu/op_code_0 has been replicated 3 time(s)
1574 
FlipFlop my_cpu/op_code_1 has been replicated 3 time(s)
1575 
FlipFlop my_cpu/op_code_2 has been replicated 2 time(s)
1576 
FlipFlop my_cpu/op_code_3 has been replicated 2 time(s)
1577 
FlipFlop my_cpu/op_code_4 has been replicated 3 time(s)
1578 
FlipFlop my_cpu/op_code_5 has been replicated 2 time(s)
1579 
FlipFlop my_cpu/op_code_6 has been replicated 2 time(s)
1580 
FlipFlop my_cpu/op_code_7 has been replicated 2 time(s)
1581 
FlipFlop my_cpu/state_0 has been replicated 11 time(s)
1582 
FlipFlop my_cpu/state_1 has been replicated 9 time(s)
1583 
FlipFlop my_cpu/state_2 has been replicated 10 time(s)
1584 
FlipFlop my_cpu/state_3 has been replicated 8 time(s)
1585 
FlipFlop my_cpu/state_4 has been replicated 12 time(s)
1586 
FlipFlop my_cpu/state_5 has been replicated 9 time(s)
1587 
FlipFlop my_cpu/state_6 has been replicated 11 time(s)
1588 
FlipFlop my_cpu/state_7 has been replicated 6 time(s)
1589 
PACKER Warning: Lut my_cpu/cpu09__n0279<5>lut driving carry my_cpu/cpu09__n0279<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1590 
PACKER Warning: Lut my_cpu/cpu09__n0279<6>lut driving carry my_cpu/cpu09__n0279<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1591 
PACKER Warning: Lut my_cpu/cpu09__n0279<7>lut driving carry my_cpu/cpu09__n0279<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1592 
PACKER Warning: Lut my_cpu/cpu09__n0279<13>lut driving carry my_cpu/cpu09__n0279<13>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1593 
PACKER Warning: Lut my_cpu/cpu09__n0278<3>lut driving carry my_cpu/cpu09__n0278<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1594 
PACKER Warning: Lut my_cpu/cpu09__n0278<4>lut driving carry my_cpu/cpu09__n0278<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1595 
PACKER Warning: Lut my_cpu/cpu09__n0278<5>lut driving carry my_cpu/cpu09__n0278<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1596 
PACKER Warning: Lut my_cpu/cpu09__n0278<6>lut driving carry my_cpu/cpu09__n0278<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1597 
PACKER Warning: Lut my_cpu/cpu09__n0278<7>lut driving carry my_cpu/cpu09__n0278<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1598 
PACKER Warning: Lut my_cpu/cpu09__n0278<8>lut driving carry my_cpu/cpu09__n0278<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1599 
PACKER Warning: Lut my_cpu/cpu09__n0278<9>lut driving carry my_cpu/cpu09__n0278<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1600 
PACKER Warning: Lut my_cpu/cpu09__n0278<10>lut driving carry my_cpu/cpu09__n0278<10>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1601 
PACKER Warning: Lut my_cpu/cpu09__n0278<11>lut driving carry my_cpu/cpu09__n0278<11>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1602 
PACKER Warning: Lut my_cpu/cpu09__n0278<12>lut driving carry my_cpu/cpu09__n0278<12>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1603 
PACKER Warning: Lut my_cpu/cpu09__n0278<13>lut driving carry my_cpu/cpu09__n0278<13>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1604 
PACKER Warning: Lut my_cpu/cpu09__n0278<14>lut driving carry my_cpu/cpu09__n0278<14>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
1605 
 
1606 
=========================================================================
1607 
*                            Final Report                               *
1608 
=========================================================================
1609 
 
1610 
Device utilization summary:
1611 
---------------------------
1612 
 
1613 
Selected Device : 3s1000ft256-5
1614 
 
1615 
 Number of Slices:                    1725  out of   7680    22%
1616 
 Number of Slice Flip Flops:           503  out of  15360     3%
1617 
 Number of 4 input LUTs:              3204  out of  15360    20%
1618 
 Number of bonded IOBs:                 67  out of    173    38%
1619 
 Number of BRAMs:                        3  out of     24    12%
1620 
 Number of MULT18X18s:                   4  out of     24    16%
1621 
 Number of GCLKs:                        1  out of      8    12%
1622 
 
1623 
 
1624 
=========================================================================
1625 
TIMING REPORT
1626 
 
1627 
 
1628 
Clock Information:
1629 
------------------
1630 
-----------------------------------+------------------------+-------+
1631 
Clock Signal                       | Clock buffer(FF name)  | Load  |
1632 
-----------------------------------+------------------------+-------+
1633 
clk                                | BUFGP                  | 506   |
1634 
-----------------------------------+------------------------+-------+
1635 
 
1636 
Timing Summary:
1637 
---------------
1638 
Speed Grade: -5
1639 
 
1640 
   Minimum period: 29.223ns (Maximum Frequency: 34.219MHz)
1641 
   Minimum input arrival time before clock: 11.983ns
1642 
   Maximum output required time after clock: 25.540ns
1643 
   Maximum combinational path delay: No path found
1644 
 
1645 
=========================================================================
1646 
 
1647 
 
1648 
 
1649 
 
1650 
Started process "Translate".
1651 
 
1652 
PMSPEC -- Overriding Xilinx file
1653 
with local file
1654 
 
1655 
Command Line: ngdbuild -intstyle ise -dd
1656 
c:\vhdl\system09\rtl\system09_digilent_3s1000/_ngo -nt timestamp -i -p
1657 
xc3s1000-ft256-5 my_unicpu09.ngc my_unicpu09.ngd
1658 
 
1659 
Reading NGO file 'C:/Vhdl/System09/rtl/System09_Digilent_3S1000/my_unicpu09.ngc'
1660 
...
1661 
 
1662 
Checking timing specifications ...
1663 
Checking expanded design ...
1664 
 
1665 
NGDBUILD Design Results Summary:
1666 
  Number of errors:     0
1667 
  Number of warnings:   0
1668 
 
1669 
Writing NGD file "my_unicpu09.ngd" ...
1670 
 
1671 
Writing NGDBUILD log file "my_unicpu09.bld"...
1672 
 
1673 
NGDBUILD done.
1674 
 
1675 
 
1676 
 
1677 
 
1678 
Started process "Map".
1679 
 
1680 
PMSPEC -- Overriding Xilinx file
1681 
with local file
1682 
Using target part "3s1000ft256-5".
1683 
Mapping design into LUTs...
1684 
Running directed packing...
1685 
Running delay-based LUT packing...
1686 
Running related packing...
1687 
 
1688 
Design Summary:
1689 
Number of errors:      0
1690 
Number of warnings:    0
1691 
Logic Utilization:
1692 
  Number of Slice Flip Flops:         503 out of  15,360    3%
1693 
  Number of 4 input LUTs:           3,145 out of  15,360   20%
1694 
Logic Distribution:
1695 
  Number of occupied Slices:                        1,767 out of   7,680   23%
1696 
    Number of Slices containing only related logic:   1,767 out of   1,767  100%
1697 
    Number of Slices containing unrelated logic:          0 out of   1,767    0%
1698 
      *See NOTES below for an explanation of the effects of unrelated logic
1699 
Total Number 4 input LUTs:          3,207 out of  15,360   20%
1700 
  Number used as logic:              3,145
1701 
  Number used as a route-thru:          62
1702 
  Number of bonded IOBs:               67 out of     173   38%
1703 
  Number of Block RAMs:                3 out of      24   12%
1704 
  Number of MULT18X18s:                4 out of      24   16%
1705 
  Number of GCLKs:                     1 out of       8   12%
1706 
 
1707 
Total equivalent gate count for design:  236,981
1708 
Additional JTAG gate count for IOBs:  3,216
1709 
Peak Memory Usage:  138 MB
1710 
 
1711 
NOTES:
1712 
 
1713 
   Related logic is defined as being logic that shares connectivity - e.g. two
1714 
   LUTs are "related" if they share common inputs.  When assembling slices,
1715 
   Map gives priority to combine logic that is related.  Doing so results in
1716 
   the best timing performance.
1717 
 
1718 
   Unrelated logic shares no connectivity.  Map will only begin packing
1719 
   unrelated logic into a slice once 99% of the slices are occupied through
1720 
   related logic packing.
1721 
 
1722 
   Note that once logic distribution reaches the 99% level through related
1723 
   logic packing, this does not mean the device is completely utilized.
1724 
   Unrelated logic packing will then begin, continuing until all usable LUTs
1725 
   and FFs are occupied.  Depending on your timing budget, increased levels of
1726 
   unrelated logic packing may adversely affect the overall timing performance
1727 
   of your design.
1728 
 
1729 
Mapping completed.
1730 
See MAP report file "my_unicpu09_map.mrp" for details.
1731 
 
1732 
 
1733 
 
1734 
 
1735 
Started process "Place & Route".
1736 
 
1737 
 
1738 
 
1739 
 
1740 
Constraints file: my_unicpu09.pcf.
1741 
PMSPEC -- Overriding Xilinx file
1742 
with local file
1743 
Loading device for application Rf_Device from file '3s1000.nph' in environment
1744 
C:/Xilinx_ISE_7.1.
1745 
   "my_unicpu09" is an NCD, version 3.1, device xc3s1000, package ft256, speed
1746 
-5
1747 
 
1748 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
1749 
Celsius)
1750 
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
1751 
 
1752 
 
1753 
Device speed data version:  "PRODUCTION 1.37 2005-07-22".
1754 
 
1755 
 
1756 
Device Utilization Summary:
1757 
 
1758 
   Number of BUFGMUXs                  1 out of 8      12%
1759 
   Number of External IOBs            67 out of 173    38%
1760 
      Number of LOCed IOBs             0 out of 67      0%
1761 
 
1762 
   Number of MULT18X18s                4 out of 24     16%
1763 
   Number of RAMB16s                   3 out of 24     12%
1764 
   Number of Slices                 1767 out of 7680   23%
1765 
      Number of SLICEMs               22 out of 3840    1%
1766 
 
1767 
 
1768 
 
1769 
Overall effort level (-ol):   Standard (set by user)
1770 
Placer effort level (-pl):    Standard (set by user)
1771 
Placer cost table entry (-t): 1
1772 
Router effort level (-rl):    Standard (set by user)
1773 
 
1774 
 
1775 
Starting Placer
1776 
 
1777 
Phase 1.1
1778 
Phase 1.1 (Checksum:98ef29) REAL time: 1 secs
1779 
 
1780 
Phase 2.31
1781 
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
1782 
 
1783 
Phase 3.2
1784 
.
1785 
 
1786 
 
1787 
Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs
1788 
 
1789 
Phase 4.3
1790 
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs
1791 
 
1792 
Phase 5.5
1793 
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs
1794 
 
1795 
Phase 6.8
1796 
.................................................
1797 
Phase 6.8 (Checksum:fb7411) REAL time: 4 secs
1798 
 
1799 
Phase 7.5
1800 
Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs
1801 
 
1802 
Phase 8.18
1803 
Phase 8.18 (Checksum:4c4b3f8) REAL time: 5 secs
1804 
 
1805 
Phase 9.5
1806 
Phase 9.5 (Checksum:55d4a77) REAL time: 5 secs
1807 
 
1808 
Writing design to file my_unicpu09.ncd
1809 
 
1810 
 
1811 
Total REAL time to Placer completion: 6 secs
1812 
Total CPU time to Placer completion: 6 secs
1813 
 
1814 
Starting Router
1815 
 
1816 
Phase 1: 13294 unrouted;       REAL time: 6 secs
1817 
 
1818 
Phase 2: 12845 unrouted;       REAL time: 7 secs
1819 
 
1820 
Phase 3: 5146 unrouted;       REAL time: 8 secs
1821 
 
1822 
Phase 4: 0 unrouted;       REAL time: 11 secs
1823 
 
1824 
 
1825 
Total REAL time to Router completion: 11 secs
1826 
Total CPU time to Router completion: 11 secs
1827 
 
1828 
Generating "PAR" statistics.
1829 
 
1830 
**************************
1831 
Generating Clock Report
1832 
**************************
1833 
 
1834 
+---------------------+--------------+------+------+------------+-------------+
1835 
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
1836 
+---------------------+--------------+------+------+------------+-------------+
1837 
|           clk_BUFGP |      BUFGMUX5| No   |  403 |  0.412     |  1.041      |
1838 
+---------------------+--------------+------+------+------------+-------------+
1839 
 
1840 
Generating Pad Report.
1841 
 
1842 
All signals are completely routed.
1843 
 
1844 
Total REAL time to PAR completion: 12 secs
1845 
Total CPU time to PAR completion: 12 secs
1846 
 
1847 
Peak Memory Usage:  120 MB
1848 
 
1849 
Placement: Completed - No errors found.
1850 
Routing: Completed - No errors found.
1851 
 
1852 
Number of error messages: 0
1853 
Number of warning messages: 0
1854 
Number of info messages: 1
1855 
 
1856 
Writing design to file my_unicpu09.ncd
1857 
 
1858 
 
1859 
 
1860 
PAR done!
1861 
 
1862 
Started process "Generate Post-Place & Route Static Timing".
1863 
 
1864 
PMSPEC -- Overriding Xilinx file
1865 
with local file
1866 
Loading device for application Rf_Device from file '3s1000.nph' in environment
1867 
C:/Xilinx_ISE_7.1.
1868 
   "my_unicpu09" is an NCD, version 3.1, device xc3s1000, package ft256, speed
1869 
-5
1870 
 
1871 
Analysis completed Sun Sep 07 23:06:23 2008
1872 
--------------------------------------------------------------------------------
1873 
 
1874 
Generating Report ...
1875 
 
1876 
Number of warnings: 0
1877 
Total time: 5 secs
1878 
 
1879 
 
1880 
 
1881 
 
1882 
 
1883 
 
1884 
 
1885 
Started process "Generate Programming File".
1886 
 
1887 
 
1888 
 
1889 
Project Navigator Auto-Make Log File
1890 
-------------------------------------
1891 
 
1892 
 
1893 
 
1894 
deleting "my_unicpu09.lso"
1895 
deleting "my_unicpu09_summary.html"
1896 
deleting "my_unicpu09.syr"
1897 
deleting "my_unicpu09.prj"
1898 
deleting "my_unicpu09.sprj"
1899 
deleting "my_unicpu09.ana"
1900 
deleting "my_unicpu09.stx"
1901 
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1902 
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1903 
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1904 
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1905 
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1906 
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1907 
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1908 
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1909 
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1910 
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1911 
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1912 
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1913 
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1914 
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1915 
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1916 
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1917 
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1918 
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1919 
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1920 
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1921 
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1922 
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1923 
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1924 
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1925 
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1926 
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1927 
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1928 
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1929 
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1930 
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1931 
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1932 
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1933 
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1934 
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1935 
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1936 
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1937 
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1938 
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1939 
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1940 
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1941 
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1942 
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1943 
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1944 
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1945 
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1946 
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1947 
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1948 
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1949 
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1950 
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1951 
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1952 
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1953 
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1954 
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1955 
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1956 
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1957 
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1958 
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1959 
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1960 
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1961 
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1962 
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1963 
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1964 
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1965 
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1966 
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1967 
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1968 
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1969 
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1970 
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1971 
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1972 
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1973 
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1974 
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1975 
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1976 
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1977 
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1978 
deleting "my_unicpu09.sprj"
1979 
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1980 
deleting "my_unicpu09.stx"
1981 
deleting "my_unicpu09.cmd_log"
1982 
deleting "my_unicpu09.lso"
1983 
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1984 
deleting "my_unicpu09.syr"
1985 
deleting "my_unicpu09.prj"
1986 
deleting "my_unicpu09.sprj"
1987 
deleting "my_unicpu09.ana"
1988 
deleting "my_unicpu09.stx"
1989 
deleting "my_unicpu09.cmd_log"
1990 
deleting "my_unicpu09.lso"
1991 
deleting "my_unicpu09_summary.html"
1992 
deleting "my_unicpu09.syr"
1993 
deleting "my_unicpu09.prj"
1994 
deleting "my_unicpu09.sprj"
1995 
deleting "my_unicpu09.ana"
1996 
deleting "my_unicpu09.stx"
1997 
deleting "my_unicpu09.cmd_log"
1998 
deleting "my_unicpu09.lso"
1999 
deleting "my_unicpu09_summary.html"
2000 
deleting "my_unicpu09.syr"
2001 
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2002 
deleting "my_unicpu09.sprj"
2003 
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2004 
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2005 
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2006 
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2007 
deleting "my_unicpu09_summary.html"
2008 
deleting "my_unicpu09.syr"
2009 
deleting "my_unicpu09.prj"
2010 
deleting "my_unicpu09.sprj"
2011 
deleting "my_unicpu09.ana"
2012 
deleting "my_unicpu09.stx"
2013 
deleting "my_unicpu09.cmd_log"
2014 
deleting "my_unicpu09.ngc"
2015 
deleting "my_unicpu09.ngr"
2016 
deleting "__projnav/ednTOngd_tcl.rsp"
2017 
deleting ""c:\vhdl\system09\rtl\system09_digilent_3s1000/_ngo""
2018 
deleting "my_unicpu09.ngd"
2019 
deleting "my_unicpu09_ngdbuild.nav"
2020 
deleting "my_unicpu09.bld"
2021 
deleting ".untf"
2022 
deleting "my_unicpu09.cmd_log"
2023 
deleting "my_unicpu09_summary.html"
2024 
deleting "my_unicpu09_map.ncd"
2025 
deleting "my_unicpu09.ngm"
2026 
deleting "my_unicpu09.pcf"
2027 
deleting "my_unicpu09.nc1"
2028 
deleting "my_unicpu09.mrp"
2029 
deleting "my_unicpu09_map.mrp"
2030 
deleting "my_unicpu09.mdf"
2031 
deleting "my_unicpu09.cmd_log"
2032 
deleting "my_unicpu09_map.ngm"
2033 
deleting "__projnav/ncdTOtwr_tcl.rsp"
2034 
deleting "my_unicpu09.twr"
2035 
deleting "my_unicpu09.twx"
2036 
deleting "my_unicpu09.tsi"
2037 
deleting "my_unicpu09.cmd_log"
2038 
deleting "my_unicpu09_summary.html"
2039 
deleting "__projnav/nc1TOncd_tcl.rsp"
2040 
deleting "my_unicpu09.ncd"
2041 
deleting "my_unicpu09.par"
2042 
deleting "my_unicpu09.pad"
2043 
deleting "my_unicpu09_pad.txt"
2044 
deleting "my_unicpu09_pad.csv"
2045 
deleting "my_unicpu09.pad_txt"
2046 
deleting "my_unicpu09.dly"
2047 
deleting "reportgen.log"
2048 
deleting "my_unicpu09.xpi"
2049 
deleting "my_unicpu09.grf"
2050 
deleting "my_unicpu09.itr"
2051 
deleting "my_unicpu09_last_par.ncd"
2052 
deleting "my_unicpu09.placed_ncd_tracker"
2053 
deleting "my_unicpu09.routed_ncd_tracker"
2054 
deleting "my_unicpu09.cmd_log"
2055 
deleting "__projnav/my_unicpu09_ncdTOut_tcl.rsp"
2056 
deleting "__projnav/bitgen.rsp"
2057 
deleting "bitgen.ut"
2058 
deleting "my_unicpu09.ut"
2059 
deleting "my_unicpu09.bgn"
2060 
deleting "my_unicpu09.rbt"
2061 
deleting "my_unicpu09.ll"
2062 
deleting "my_unicpu09.msk"
2063 
deleting "my_unicpu09.drc"
2064 
deleting "my_unicpu09.nky"
2065 
deleting "my_unicpu09.bit"
2066 
deleting "my_unicpu09.bin"
2067 
deleting "my_unicpu09.isc"
2068 
deleting "my_unicpu09.cmd_log"
2069 
deleting "my_unicpu09.lso"
2070 
deleting "my_unicpu09_summary.html"
2071 
deleting "my_unicpu09.syr"
2072 
deleting "my_unicpu09.prj"
2073 
deleting "my_unicpu09.sprj"
2074 
deleting "my_unicpu09.ana"
2075 
deleting "my_unicpu09.stx"
2076 
deleting "my_unicpu09.cmd_log"
2077 
deleting "my_unicpu09.ngc"
2078 
deleting "my_unicpu09.ngr"
2079 
deleting "__projnav/ednTOngd_tcl.rsp"
2080 
deleting ""c:\vhdl\system09\rtl\system09_digilent_3s1000/_ngo""
2081 
deleting "my_unicpu09.ngd"
2082 
deleting "my_unicpu09_ngdbuild.nav"
2083 
deleting "my_unicpu09.bld"
2084 
deleting ".untf"
2085 
deleting "my_unicpu09.cmd_log"
2086 
deleting "my_unicpu09_summary.html"
2087 
deleting "my_unicpu09_map.ncd"
2088 
deleting "my_unicpu09.ngm"
2089 
deleting "my_unicpu09.pcf"
2090 
deleting "my_unicpu09.nc1"
2091 
deleting "my_unicpu09.mrp"
2092 
deleting "my_unicpu09_map.mrp"
2093 
deleting "my_unicpu09.mdf"
2094 
deleting "my_unicpu09.cmd_log"
2095 
deleting "my_unicpu09_map.ngm"
2096 
deleting "__projnav/ncdTOtwr_tcl.rsp"
2097 
deleting "my_unicpu09.twr"
2098 
deleting "my_unicpu09.twx"
2099 
deleting "my_unicpu09.tsi"
2100 
deleting "my_unicpu09.cmd_log"
2101 
deleting "my_unicpu09_summary.html"
2102 
deleting "__projnav/nc1TOncd_tcl.rsp"
2103 
deleting "my_unicpu09.ncd"
2104 
deleting "my_unicpu09.par"
2105 
deleting "my_unicpu09.pad"
2106 
deleting "my_unicpu09_pad.txt"
2107 
deleting "my_unicpu09_pad.csv"
2108 
deleting "my_unicpu09.pad_txt"
2109 
deleting "my_unicpu09.dly"
2110 
deleting "reportgen.log"
2111 
deleting "my_unicpu09.xpi"
2112 
deleting "my_unicpu09.grf"
2113 
deleting "my_unicpu09.itr"
2114 
deleting "my_unicpu09_last_par.ncd"
2115 
deleting "my_unicpu09.placed_ncd_tracker"
2116 
deleting "my_unicpu09.routed_ncd_tracker"
2117 
deleting "my_unicpu09.cmd_log"
2118 
deleting "__projnav/my_unicpu09_ncdTOut_tcl.rsp"
2119 
deleting "__projnav/bitgen.rsp"
2120 
deleting "bitgen.ut"
2121 
deleting "my_unicpu09.ut"
2122 
deleting "my_unicpu09.bgn"
2123 
deleting "my_unicpu09.rbt"
2124 
deleting "my_unicpu09.ll"
2125 
deleting "my_unicpu09.msk"
2126 
deleting "my_unicpu09.drc"
2127 
deleting "my_unicpu09.nky"
2128 
deleting "my_unicpu09.bit"
2129 
deleting "my_unicpu09.bin"
2130 
deleting "my_unicpu09.isc"
2131 
deleting "my_unicpu09.cmd_log"
2132 
deleting "my_system09_summary.html"
2133 
deleting "my_unicpu09.prj"
2134 
deleting "my_unicpu09.prj"
2135 
deleting "__projnav/my_unicpu09.xst"
2136 
deleting "./xst"
2137 
deleting "my_unicpu09.prj"
2138 
deleting "my_unicpu09.prj"
2139 
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2140 
deleting "./xst"
2141 
deleting "my_unicpu09.prj"
2142 
deleting "my_unicpu09.prj"
2143 
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2144 
deleting "./xst"
2145 
deleting "my_unicpu09.prj"
2146 
deleting "my_unicpu09.prj"
2147 
deleting "__projnav/my_unicpu09.xst"
2148 
deleting "./xst"
2149 
deleting "my_unicpu09.prj"
2150 
deleting "my_unicpu09.prj"
2151 
deleting "__projnav/my_unicpu09.xst"
2152 
deleting "./xst"
2153 
deleting "my_unicpu09.prj"
2154 
deleting "my_unicpu09.prj"
2155 
deleting "__projnav/my_unicpu09.xst"
2156 
deleting "./xst"
2157 
deleting "my_unicpu09.prj"
2158 
deleting "my_unicpu09.prj"
2159 
deleting "__projnav/my_unicpu09.xst"
2160 
deleting "./xst"
2161 
deleting "my_unicpu09.prj"
2162 
deleting "my_unicpu09.prj"
2163 
deleting "__projnav/my_unicpu09.xst"
2164 
deleting "./xst"
2165 
deleting "my_unicpu09.prj"
2166 
deleting "my_unicpu09.prj"
2167 
deleting "__projnav/my_unicpu09.xst"
2168 
deleting "./xst"
2169 
deleting "my_unicpu09.prj"
2170 
deleting "my_unicpu09.prj"
2171 
deleting "__projnav/my_unicpu09.xst"
2172 
deleting "./xst"
2173 
deleting "my_unicpu09.prj"
2174 
deleting "my_unicpu09.prj"
2175 
deleting "__projnav/my_unicpu09.xst"
2176 
deleting "./xst"
2177 
deleting "my_unicpu09.prj"
2178 
deleting "my_unicpu09.prj"
2179 
deleting "__projnav/my_unicpu09.xst"
2180 
deleting "./xst"
2181 
deleting "my_unicpu09.prj"
2182 
deleting "my_unicpu09.prj"
2183 
deleting "__projnav/my_unicpu09.xst"
2184 
deleting "./xst"
2185 
deleting "my_unicpu09.prj"
2186 
deleting "my_unicpu09.prj"
2187 
deleting "__projnav/my_unicpu09.xst"
2188 
deleting "./xst"
2189 
deleting "my_unicpu09.prj"
2190 
deleting "my_unicpu09.prj"
2191 
deleting "__projnav/my_unicpu09.xst"
2192 
deleting "./xst"
2193 
deleting "my_unicpu09.prj"
2194 
deleting "my_unicpu09.prj"
2195 
deleting "__projnav/my_unicpu09.xst"
2196 
deleting "./xst"
2197 
deleting "__projnav/System09_Digilent_3S1000.gfl"
2198 
deleting "__projnav/System09_Digilent_3S1000_flowplus.gfl"
2199 
deleting System09_Digilent_3S1000.dhp
2200 
Finished cleaning up project
2201 
 

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