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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S200/] [System09_Digilent_3S200.vhd] - Blame information for rev 101

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Line No. Rev Author Line
1 99 davidgb
--=============================================================================--
2
--                                                                             --
3
--  System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
4
--                                                                             --
5
--=============================================================================--
6
--
7 19 dilbert57
--
8 99 davidgb
-- File name      : System09_Digilent_3S200.vhd
9
--
10
-- Entity name    : System09
11 19 dilbert57
--
12
-- Purpose        : Top level file for 6809 compatible system on a chip
13
--                  Designed with Xilinx XC3S200 Spartan 3 FPGA.
14
--                  Implemented With Digilent Xilinx Starter FPGA board,
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21 99 davidgb
-- Uses           : cpu09         (..\VHDL\cpu09.vhd)              CPU core
22
--                  dat_ram       (..\VHDL\datram.vhd)             Dynamic Address Translation
23
--                  SYS09BUG_F800 (..\Spartan3\sys093s3_b16.vhd)   Monitor ROM
24
--                  acia6850      (..\VHDL\acia6850.vhd)           ACIA (UART)
25
--                  ACIA_Clock    (..\VHDL\ACIA_Clock.vhd)         ACIA Baud Rate Clock Divider
26
--                  keyboard      (..\VHDL\keyboard.vhd)           PS/2 Keyboard register interface
27
--                  ps2_keyboard  (..\VHDL\ps2_keyboard.vhd)       PS/2 Keyboard interface logic
28
--                  keymap_rom    (..\Spartan2\keymap_rom.vhd)     PS/2 Keyboard key code look up table
29
--                  vdu8          (..\VHDL\vdu8.vhd)                      Video Display Unit
30
--                                (..\Spartan3\char_rom2K_b16.vhd) Character Generator ROM (B16_RAM)
31
--                                (..\Spartan3\ram2k_b16.vhd)      Text & Attribute RAM Buffer
32
--                  seven_segment (..\VHDL\SevenSegment.vhd)       Seven Segment Display
33 19 dilbert57
-- 
34
-- Author         : John E. Kent      
35
--                  dilbert57@opencores.org      
36 99 davidgb
--
37
-- Memory Map     :
38
--
39
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
40
-- $E000 - ACIA (SWTPc)
41
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
42
-- $E020 - Keyboard
43
-- $E030 - VDU
44
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
45
-- $E050 - Timer
46
-- $E060 - Reserved for Bus Trap (Hardware Breakpoint Logic)
47
-- $E070 - Reserved for Trace Buffer
48
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
49
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
50
-- $E0A0 - Switches in / LEDS out
51
-- $E0B0 - 7 Segment display
52
-- $E0C0 - Reserved
53
-- $E0D0 - Reserved
54
-- $E0E0 - Reserved
55
-- $E0F0 - Reserved
56
-- $E100 - $E13F Reserved IDE / Compact Flash Card
57
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
58
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
59
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
60
-- $E200 - $EFFF Reserved for Future I/O
61
-- $F000 - $F7FF RAM for Sys09bug monitor extensions
62
-- $F800 - $FFFF Sys09bug ROM (Read only)
63
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
64
--
65
--
66
--  Copyright (C) 2003 - 2010 John Kent
67
--
68
--  This program is free software: you can redistribute it and/or modify
69
--  it under the terms of the GNU General Public License as published by
70
--  the Free Software Foundation, either version 3 of the License, or
71
--  (at your option) any later version.
72
--
73
--  This program is distributed in the hope that it will be useful,
74
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
75
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
76
--  GNU General Public License for more details.
77
--
78
--  You should have received a copy of the GNU General Public License
79
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
80
--
81
--===========================================================================--
82 19 dilbert57
--
83 99 davidgb
--                              Revision History:
84 19 dilbert57
--
85 99 davidgb
--===========================================================================--
86
--
87 19 dilbert57
-- Version 0.1 - 20 March 2003
88
-- Version 0.2 - 30 March 2003
89
-- Version 0.3 - 29 April 2003
90
-- Version 0.4 - 29 June 2003
91
--
92
-- Version 0.5 - 19 July 2003
93
-- prints out "Hello World"
94
--
95
-- Version 0.6 - 5 September 2003
96
-- Runs SBUG
97
--
98
-- Version 1.0- 6 Sep 2003 - John Kent
99 22 dilbert57
-- Inverted sys_clk
100 19 dilbert57
-- Initial release to Open Cores
101
--
102
-- Version 1.1 - 17 Jan 2004 - John Kent
103
-- Updated miniUart.
104
--
105
-- Version 1.2 - 25 Jan 2004 - John Kent
106
-- removed signals "test_alu" and "test_cc" 
107
-- Trap hardware re-instated.
108
--
109
-- Version 1.3 - 11 Feb 2004 - John Kent
110
-- Designed forked off to produce System09_VDU
111
-- Added VDU component
112
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
113
-- UART Runs at 57.6 Kbps
114
--
115
-- Version 2.0 - 2 September 2004 - John Kent
116
-- ported to Digilent Xilinx Spartan3 starter board
117
--      removed Compaact Flash and Trap Logic.
118
-- Replaced SBUG with KBug9s
119
--
120
-- Version 2.1 - 21 November 2006 - John Kent
121
-- Replaced KBug9s with Sys09bug 1.0
122
-- Inverted bottom nybble of DAT register outputs
123
-- Changed ROM & I/O decoding to be compatible with SWTPc
124
-- Upped the serial baud rate to 115.2 KBd
125
-- added multiple global clock buffers
126
-- (Uart would not operate correctly)
127
--
128
-- Version 2.2 - 22 December 2006 - John Kent
129
-- Increased CPU clock from 12.5MHz to 25 MHz.
130
-- Removed some of the global clock buffers
131
-- Added LED output register
132
-- Changed address decoding to 4K Blocks
133
--
134 22 dilbert57
-- Version 2.3 - 1 June 2007 - John Kent
135 19 dilbert57
-- Updated VDU & ACIA
136
-- Changed decoding for Sys09Bug
137
--
138 22 dilbert57
-- Version 2.4 - 31 January 2008 - John Kent
139
--      ACIA does not appear to work.
140
-- Made RAM OE and WE strobes synchonous to sys_clk
141 99 davidgb
--
142
-- Version 2.5 - 23rd Feburary 2009 - John Kent
143
-- Implemented recommendation to remove vga_clk clock buffer
144
--
145
-- Version 2.6 - 5th september 2010 - John Kent
146
-- Renamed ACIA_6850 to acia6850
147
-- Updated generics on VDU8
148
-- Shortened the "keyboard" label
149
-- Fixed up address label on CPU09
150
-- Removed Flex RAM
151
-- Map RAM at $F000 - $F7FF
152 22 dilbert57
--
153 19 dilbert57
--===========================================================================--
154
library ieee;
155
   use ieee.std_logic_1164.all;
156
   use IEEE.STD_LOGIC_ARITH.ALL;
157
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
158
   use ieee.numeric_std.all;
159
 
160 59 davidgb
entity my_system09 is
161 19 dilbert57
  port(
162 22 dilbert57
    sys_clk     : in  Std_Logic;  -- System Clock input
163
         rst_sw    : in  Std_logic;  -- Master Reset input (active high)
164 19 dilbert57
         nmi_sw      : in  Std_logic;
165
 
166
    -- Memory Interface signals
167
    ram_addr    : out Std_Logic_Vector(17 downto 0);
168
    ram_wen     : out Std_Logic;
169
    ram_oen     : out Std_Logic;
170
 
171
    ram1_cen    : out Std_Logic;
172
         ram1_ubn    : out Std_Logic;
173
         ram1_lbn    : out Std_Logic;
174
    ram1_data   : inout Std_Logic_Vector(15 downto 0);
175
 
176
    ram2_cen    : out Std_Logic;
177
         ram2_ubn    : out Std_Logic;
178
         ram2_lbn    : out Std_Logic;
179
    ram2_data   : inout Std_Logic_Vector(15 downto 0);
180
 
181
         -- PS/2 Keyboard
182
         ps2c        : inout Std_logic;
183
         ps2d        : inout Std_Logic;
184
 
185 22 dilbert57
         -- ACIA Interface
186 19 dilbert57
    rxd         : in  Std_Logic;
187
         txd         : out Std_Logic;
188
 
189
         -- CRTC output signals
190
         vs          : out Std_Logic;
191
    hs          : out Std_Logic;
192
    blue        : out std_logic;
193
    green       : out std_logic;
194
    red         : out std_logic;
195
 
196
         -- LEDS & Switches
197
         leds        : out std_logic_vector(7 downto 0);
198
         switches    : in  std_logic_vector(7 downto 0);
199
 
200
         -- seven segment display
201
         segments    : out std_logic_vector(7 downto 0);
202
         digits      : out std_logic_vector(3 downto 0)
203
         );
204 59 davidgb
end my_system09;
205 19 dilbert57
 
206
-------------------------------------------------------------------------------
207
-- Architecture for System09
208
-------------------------------------------------------------------------------
209 59 davidgb
architecture my_computer of my_system09 is
210 19 dilbert57
  -----------------------------------------------------------------------------
211
  -- constants
212
  -----------------------------------------------------------------------------
213 99 davidgb
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
214
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
215
  constant CPU_CLK_FREQ  : integer := 25000000;  -- CPU Clock
216
  constant BAUD_Rate     : integer := 57600;      -- Baud Rate
217
  constant ACIA_CLK_FREQ : integer := BAUD_Rate * 16;
218 19 dilbert57
 
219
  type hold_state_type is ( hold_release_state, hold_request_state );
220
 
221
  -----------------------------------------------------------------------------
222
  -- Signals
223
  -----------------------------------------------------------------------------
224 99 davidgb
 
225
  -- CPU Interface signals
226
  signal cpu_clk       : Std_Logic;
227
  signal cpu_rst       : Std_Logic;
228
  signal cpu_rw        : std_logic;
229
  signal cpu_vma       : std_logic;
230
  signal cpu_halt      : std_logic;
231
  signal cpu_hold      : std_logic;
232
  signal cpu_firq      : std_logic;
233
  signal cpu_irq       : std_logic;
234
  signal cpu_nmi       : std_logic;
235
  signal cpu_addr      : std_logic_vector(15 downto 0);
236
  signal cpu_data_in   : std_logic_vector(7 downto 0);
237
  signal cpu_data_out  : std_logic_vector(7 downto 0);
238
 
239
  -- Dynamic Address Translation
240
  signal dat_cs        : std_logic;
241
  signal dat_addr      : std_logic_vector(7 downto 0);
242
 
243 19 dilbert57
  -- BOOT ROM
244
  signal rom_cs        : Std_logic;
245
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
246
 
247 22 dilbert57
  -- ACIA Interface signals
248 19 dilbert57
  signal acia_clk      : std_logic;
249 99 davidgb
  signal acia_cs       : Std_Logic;
250 19 dilbert57
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
251
  signal acia_irq      : Std_Logic;
252 22 dilbert57
  signal acia_rxd      : Std_Logic;
253
  signal acia_txd      : Std_Logic;
254
  signal acia_dcd_n    : Std_Logic;
255
--  signal acia_rts_n    : Std_Logic;
256
  signal acia_cts_n    : Std_Logic;
257 19 dilbert57
 
258
  -- keyboard port
259 99 davidgb
  signal kbd_data_out : std_logic_vector(7 downto 0);
260
  signal kbd_cs       : std_logic;
261
  signal kbd_irq      : std_logic;
262 19 dilbert57
 
263
  -- LEDs
264
  signal leds_data_out : std_logic_vector(7 downto 0);
265
  signal leds_cs       : std_logic;
266 99 davidgb
 
267
  -- Video Display Unit
268
  signal vdu_cs       : std_logic;
269
  signal vdu_data_out : std_logic_vector(7 downto 0);
270
  signal vga_clk      : std_logic;
271 19 dilbert57
 
272 99 davidgb
  -- 7 Segment Display
273
  signal seg_cs       : std_logic;
274
  signal seg_data_out : std_logic_vector(7 downto 0);
275
 
276 19 dilbert57
  -- RAM
277
  signal ram_cs       : std_logic; -- memory chip select
278
  signal ram_data_out : std_logic_vector(7 downto 0);
279
  signal ram1_ce      : std_logic;
280
  signal ram1_ub      : std_logic;
281
  signal ram1_lb      : std_logic;
282
  signal ram2_ce      : std_logic;
283
  signal ram2_ub      : std_logic;
284
  signal ram2_lb      : std_logic;
285
  signal ram_we       : std_logic;
286
  signal ram_oe       : std_logic;
287
 
288
  -- System Clock Prescaler
289
  signal clk_count    : std_logic;
290
 
291
-----------------------------------------------------------------
292
--
293
-- CPU09 CPU core
294
--
295
-----------------------------------------------------------------
296
 
297
component cpu09
298
  port (
299
         clk      :     in  std_logic;
300
    rst      : in  std_logic;
301
    vma      :  out std_logic;
302 99 davidgb
    addr     : out std_logic_vector(15 downto 0);
303
    rw       :  out std_logic;
304 19 dilbert57
    data_in  : in        std_logic_vector(7 downto 0);
305
         data_out : out std_logic_vector(7 downto 0);
306
         halt     : in  std_logic;
307
         hold     : in  std_logic;
308
         irq      : in  std_logic;
309
         nmi      : in  std_logic;
310
         firq     : in  std_logic
311
  );
312
end component;
313 99 davidgb
 
314 19 dilbert57
----------------------------------------
315
--
316 99 davidgb
-- Dynamic Address Translation Registers
317 19 dilbert57
--
318
----------------------------------------
319 99 davidgb
component dat_ram
320
  port (
321 19 dilbert57
    clk      : in  std_logic;
322 99 davidgb
         rst      : in  std_logic;
323
         cs       : in  std_logic;
324
         rw       : in  std_logic;
325
         addr_lo  : in  std_logic_vector(3 downto 0);
326
         addr_hi  : in  std_logic_vector(3 downto 0);
327
    data_in  : in  std_logic_vector(7 downto 0);
328
         data_out : out std_logic_vector(7 downto 0)
329
  );
330 19 dilbert57
end component;
331
 
332
----------------------------------------
333
--
334 99 davidgb
-- 4KByte Block RAM Monitor ROM
335 19 dilbert57
--
336
----------------------------------------
337 99 davidgb
component SYS09BUG_F800
338 19 dilbert57
  Port (
339
    clk      : in  std_logic;
340
    rst      : in  std_logic;
341
    cs       : in  std_logic;
342
    rw       : in  std_logic;
343 99 davidgb
    addr     : in  std_logic_vector (10 downto 0);
344
    data_in  : in  std_logic_vector (7 downto 0);
345
    data_out : out std_logic_vector (7 downto 0)
346 19 dilbert57
    );
347
end component;
348
 
349
-----------------------------------------------------------------
350
--
351 22 dilbert57
-- 6850 ACIA
352 19 dilbert57
--
353
-----------------------------------------------------------------
354
 
355 99 davidgb
component acia6850
356 19 dilbert57
  port (
357
    clk      : in  Std_Logic;  -- System Clock
358
    rst      : in  Std_Logic;  -- Reset input (active high)
359 22 dilbert57
    cs       : in  Std_Logic;  -- ACIA Chip Select
360 19 dilbert57
    rw       : in  Std_Logic;  -- Read / Not Write
361 99 davidgb
    addr     : in  Std_Logic;  -- Register Select
362
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
363
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
364 19 dilbert57
    irq      : out Std_Logic;  -- Interrupt
365
    RxC      : in  Std_Logic;  -- Receive Baud Clock
366
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
367
    RxD      : in  Std_Logic;  -- Receive Data
368
    TxD      : out Std_Logic;  -- Transmit Data
369
         DCD_n    : in  Std_Logic;  -- Data Carrier Detect
370
    CTS_n    : in  Std_Logic;  -- Clear To Send
371
    RTS_n    : out Std_Logic   -- Request To send
372
  );
373
end component;
374
 
375
-----------------------------------------------------------------
376
--
377
-- ACIA Clock divider
378
--
379
-----------------------------------------------------------------
380
 
381
component ACIA_Clock
382
  generic (
383 99 davidgb
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
384
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
385 19 dilbert57
  );
386
  port (
387
     clk      : in  Std_Logic;  -- System Clock Input
388 99 davidgb
          acia_clk : out Std_logic   -- ACIA Clock output
389 19 dilbert57
  );
390
end component;
391
 
392
----------------------------------------
393
--
394
-- PS/2 Keyboard
395
--
396
----------------------------------------
397
 
398
component keyboard
399
  generic(
400 99 davidgb
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
401 19 dilbert57
  );
402
  port(
403 99 davidgb
    clk             : in    std_logic;
404
    rst             : in    std_logic;
405
    cs              : in    std_logic;
406
    addr            : in    std_logic;
407
    rw              : in    std_logic;
408
    data_in         : in    std_logic_vector(7 downto 0);
409
    data_out        : out   std_logic_vector(7 downto 0);
410
    irq             : out   std_logic;
411
    kbd_clk         : inout std_logic;
412
    kbd_data        : inout std_logic
413 19 dilbert57
  );
414
end component;
415
 
416
----------------------------------------
417
--
418
-- Video Display Unit.
419
--
420
----------------------------------------
421
component vdu8
422 99 davidgb
  generic(
423
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
424
         VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
425
         VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
426
         VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
427
         VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
428
         VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
429
         VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
430
         VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
431
         VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
432
         VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
433
         VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
434
  );
435
  port(
436
    -- control register interface
437
    vdu_clk      : in  std_logic;        -- CPU Clock - 12.5MHz
438
    vdu_rst      : in  std_logic;
439
    vdu_cs       : in  std_logic;
440
    vdu_rw       : in  std_logic;
441
    vdu_addr     : in  std_logic_vector(2 downto 0);
442
    vdu_data_in  : in  std_logic_vector(7 downto 0);
443
    vdu_data_out : out std_logic_vector(7 downto 0);
444 19 dilbert57
 
445 99 davidgb
    -- vga port connections
446
    vga_clk      : in  std_logic;       -- VGA Pixel Clock - 25 MHz
447
    vga_red_o    : out std_logic;
448
    vga_green_o  : out std_logic;
449
    vga_blue_o   : out std_logic;
450
    vga_hsync_o  : out std_logic;
451
    vga_vsync_o  : out std_logic
452
  );
453 19 dilbert57
end component;
454
 
455
----------------------------------------
456
--
457
-- Seven Segment Display driver
458
--
459
----------------------------------------
460
 
461
component seven_segment is
462 99 davidgb
  port (
463
    clk         : in  std_logic;
464
    rst         : in  std_logic;
465
    cs          : in  std_logic;
466
    addr        : in  std_logic_vector(1 downto 0);
467
    rw          : in  std_logic;
468
    data_in     : in  std_logic_vector(7 downto 0);
469
         data_out    : out std_logic_vector(7 downto 0);
470
         segments    : out std_logic_vector(7 downto 0);
471
         digits      : out std_logic_vector(3 downto 0)
472
  );
473 19 dilbert57
end component;
474
 
475
component BUFG
476
  port (
477
    i            : in  std_logic;
478
    o            : out std_logic
479
  );
480
end component;
481
 
482
begin
483
  -----------------------------------------------------------------------------
484
  -- Instantiation of internal components
485
  -----------------------------------------------------------------------------
486
 
487
my_cpu : cpu09  port map (
488
         clk         => cpu_clk,
489 99 davidgb
    rst       => cpu_rst,
490
    vma       => cpu_vma,
491
    addr      => cpu_addr(15 downto 0),
492 19 dilbert57
    rw       => cpu_rw,
493
    data_in   => cpu_data_in,
494
         data_out  => cpu_data_out,
495
         halt      => cpu_halt,
496
         hold      => cpu_hold,
497
         irq       => cpu_irq,
498
         nmi       => cpu_nmi,
499
         firq      => cpu_firq
500
    );
501
 
502
my_dat : dat_ram port map (
503
    clk       => cpu_clk,
504 99 davidgb
         rst       => cpu_rst,
505 19 dilbert57
         cs        => dat_cs,
506
         addr_hi   => cpu_addr(15 downto 12),
507
         addr_lo   => cpu_addr(3 downto 0),
508 99 davidgb
         rw        => cpu_rw,
509 19 dilbert57
    data_in   => cpu_data_out,
510
         data_out  => dat_addr(7 downto 0)
511
         );
512
 
513 99 davidgb
my_rom : SYS09BUG_F800 port map (
514
    clk       => cpu_clk,
515
    rst       => cpu_rst,
516
         cs        => rom_cs,
517
         rw        => '1',
518
    addr      => cpu_addr(10 downto 0),
519
    data_in   => cpu_data_out,
520
    data_out  => rom_data_out
521
    );
522
 
523
my_acia  : acia6850 port map (
524 19 dilbert57
         clk         => cpu_clk,
525 99 davidgb
         rst       => cpu_rst,
526 19 dilbert57
    cs        => acia_cs,
527 99 davidgb
    addr      => cpu_addr(0),
528 19 dilbert57
         rw        => cpu_rw,
529 99 davidgb
         data_in   => cpu_data_out,
530
         data_out  => acia_data_out,
531 19 dilbert57
    irq       => acia_irq,
532
         RxC       => acia_clk,
533
         TxC       => acia_clk,
534 22 dilbert57
         RxD       => acia_rxd,
535
         TxD       => acia_txd,
536
         DCD_n     => acia_dcd_n,
537
         CTS_n     => acia_cts_n,
538
         RTS_n     => open
539 99 davidgb
    );
540 19 dilbert57
 
541
 
542
----------------------------------------
543
--
544
-- ACIA Clock
545
--
546
----------------------------------------
547
my_ACIA_Clock : ACIA_Clock
548
  generic map(
549 99 davidgb
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
550
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
551 19 dilbert57
  )
552
  port map(
553 22 dilbert57
    clk        => sys_clk,
554 19 dilbert57
    acia_clk   => acia_clk
555
  );
556
 
557
 
558
----------------------------------------
559
--
560
-- PS/2 Keyboard Interface
561
--
562
----------------------------------------
563
my_keyboard : keyboard
564
   generic map (
565 99 davidgb
          KBD_CLK_FREQ => CPU_CLK_FREQ
566 19 dilbert57
        )
567
   port map(
568 99 davidgb
          clk          => cpu_clk,
569
          rst          => cpu_rst,
570
          cs           => kbd_cs,
571
          addr         => cpu_addr(0),
572
          rw           => cpu_rw,
573
          data_in      => cpu_data_out(7 downto 0),
574
          data_out     => kbd_data_out(7 downto 0),
575
          irq          => kbd_irq,
576
          kbd_clk      => ps2c,
577
          kbd_data     => ps2d
578 19 dilbert57
        );
579 99 davidgb
 
580 19 dilbert57
----------------------------------------
581
--
582
-- Video Display Unit instantiation
583
--
584
----------------------------------------
585
my_vdu : vdu8
586
  generic map(
587 99 davidgb
    VGA_CLK_FREQ           => VGA_CLK_FREQ, -- 25MHZ
588
    VGA_HOR_CHARS          => 80, -- CHARACTERS 25.6us
589
    VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS 0.32us
590
    VGA_HOR_FRONT_PORCH    => 16, -- PIXELS 0.64us
591
    VGA_HOR_SYNC           => 96, -- PIXELS 3.84us
592
    VGA_HOR_BACK_PORCH     => 48, -- PIXELS 1.92us
593
    VGA_VER_CHARS          => 25, -- CHARACTERS 12.8ms
594
    VGA_VER_CHAR_LINES     => 16, -- LINES 0.512ms
595
    VGA_VER_FRONT_PORCH    => 10, -- LINES 0.320ms
596
    VGA_VER_SYNC           => 2,  -- LINES 0.064ms
597
    VGA_VER_BACK_PORCH     => 34  -- LINES 1.088ms
598 19 dilbert57
  )
599
  port map(
600
 
601 99 davidgb
    -- Control Registers
602
    vdu_clk       => cpu_clk,                                    -- 12.5 MHz System Clock in
603
    vdu_rst       => cpu_rst,
604
    vdu_cs        => vdu_cs,
605
    vdu_addr      => cpu_addr(2 downto 0),
606
    vdu_rw        => cpu_rw,
607
    vdu_data_in   => cpu_data_out,
608
    vdu_data_out  => vdu_data_out,
609 19 dilbert57
 
610 99 davidgb
    -- vga port connections
611
    vga_clk       => vga_clk,                                    -- 25 MHz VDU pixel clock
612
    vga_red_o     => red,
613
    vga_green_o   => green,
614
    vga_blue_o    => blue,
615
    vga_hsync_o   => hs,
616
    vga_vsync_o   => vs
617
  );
618 19 dilbert57
 
619
 
620
----------------------------------------
621
--
622
-- Seven Segment Display instantiation
623
--
624
----------------------------------------
625
 
626
my_seg : seven_segment port map (
627
    clk        => cpu_clk,
628 99 davidgb
         rst        => cpu_rst,
629 19 dilbert57
         cs         => seg_cs,
630
         rw         => cpu_rw,
631
         addr       => cpu_addr(1 downto 0),
632
    data_in    => cpu_data_out,
633
         data_out   => seg_data_out,
634
         segments   => segments,
635
         digits     => digits
636
         );
637
 
638 99 davidgb
--vga_clk_buffer : BUFG port map(
639
--    i => clk_count,
640
--       o => vga_clk
641
--    );
642
 
643
vga_clk <= cpu_clk;
644 19 dilbert57
 
645
cpu_clk_buffer : BUFG port map(
646
    i => clk_count,
647
         o => cpu_clk
648
    );
649
 
650
--
651
-- Clock divider
652
-- Assumes 50 MHz system clock
653
-- 25MHz pixel clock
654
-- 25MHz CPU clock
655
--
656 22 dilbert57
sys09_clock : process( sys_clk, clk_count )
657 19 dilbert57
begin
658 22 dilbert57
        if sys_clk'event and sys_clk='1' then
659 19 dilbert57
           clk_count <= not clk_count;
660
   end if;
661
end process;
662
 
663
----------------------------------------------------------------------
664
--
665
-- Process to decode memory map
666
--
667
----------------------------------------------------------------------
668
 
669 22 dilbert57
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
670 19 dilbert57
                                              dat_cs, dat_addr,
671
                                              rom_data_out,
672
                                                   acia_data_out,
673 99 davidgb
                                                        kbd_data_out,
674 19 dilbert57
                                                        vdu_data_out,
675
                                                        seg_data_out,
676
                                                        leds_data_out,
677
                                                        ram_data_out
678
                                                        )
679
begin
680 22 dilbert57
      cpu_data_in <= (others=>'0');
681
      dat_cs      <= '0';
682
      rom_cs      <= '0';
683
      acia_cs     <= '0';
684 99 davidgb
      kbd_cs      <= '0';
685 22 dilbert57
      vdu_cs      <= '0';
686
      seg_cs      <= '0';
687
      leds_cs     <= '0';
688
      ram_cs      <= '0';
689
--           timer_cs    <= '0';
690
--      trap_cs     <= '0';
691
--           pb_cs       <= '0';
692
--      ide_cs      <= '0';
693
--      ether_cs    <= '0';
694
--           slot1_cs    <= '0';
695
--      slot2_cs    <= '0';
696
 
697
      if cpu_addr( 15 downto 8 ) = "11111111" then
698 19 dilbert57
             cpu_data_in <= rom_data_out;
699
        dat_cs      <= cpu_vma;              -- write DAT
700
        rom_cs      <= cpu_vma;              -- read  ROM
701
           --
702 22 dilbert57
                -- Sys09Bug Monitor ROM $F000 - $FFFF
703
                --
704 99 davidgb
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
705
        if cpu_addr(11) = '1' then
706
          --
707
                    -- Monitor ROM $F800 - $FFFF
708
                    --
709
          cpu_data_in <= rom_data_out;
710
          rom_cs      <= cpu_vma;          -- read  ROM
711
        else
712
          --
713
                    -- SRAM $F000 - $F7FF
714
                    --
715
          cpu_data_in <= ram_data_out;
716
          ram_cs      <= cpu_vma;
717
        end if;
718 19 dilbert57
      --
719
                -- IO Devices $E000 - $EFFF
720
                --
721 22 dilbert57
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
722
                        case cpu_addr(11 downto 8) is
723 19 dilbert57
                        --
724 22 dilbert57
                        -- SWTPC peripherals from $E000 to $E0FF
725 19 dilbert57
                        --
726
                        when "0000" =>
727 22 dilbert57
                     case cpu_addr(7 downto 4) is
728
                          --
729
                          -- ACIA ($E000 - $E00F)
730
                          --
731
                          when "0000" =>
732
                       cpu_data_in <= acia_data_out;
733
                            acia_cs     <= cpu_vma;
734 19 dilbert57
 
735 22 dilbert57
                --
736
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
737
           --
738 19 dilbert57
 
739 22 dilbert57
                          --
740
           -- Keyboard port ($E020 - $E02F)
741
                          --
742
                          when "0010" =>
743 99 davidgb
             cpu_data_in <= kbd_data_out;
744
                            kbd_cs <= cpu_vma;
745 19 dilbert57
 
746 22 dilbert57
           --
747
           -- VDU port ($E030 - $E03F)
748
                          --
749
                          when "0011" =>
750
             cpu_data_in <= vdu_data_out;
751
                            vdu_cs      <= cpu_vma;
752 19 dilbert57
 
753 22 dilbert57
           --
754
                          -- Reserved - SWTPc MP-T ($E040 - $E04F)
755
                          --
756 19 dilbert57
 
757 22 dilbert57
           --
758
           -- Reserved - Timer ($E050 - $E05F) (B5-X300)
759
                          --
760 19 dilbert57
 
761 22 dilbert57
           --
762
           -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300)
763
                          --
764 19 dilbert57
 
765 22 dilbert57
           --
766
           -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
767
                          --
768 19 dilbert57
 
769 22 dilbert57
                          --
770
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
771
                          --
772 19 dilbert57
 
773 22 dilbert57
                          --
774
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
775
                          --
776
 
777
           --
778
                          -- Read Switched port ($E0A0 - $E0AF)
779
                          -- Write LEDS
780
                          --
781
                          when "1010" =>
782
             cpu_data_in <= leds_data_out;
783
                            leds_cs     <= cpu_vma;
784
 
785
           --
786
           -- 7 segment display port ($E0B0 - $E0BF)
787
                          --
788
                          when "1011" =>
789
             cpu_data_in <= seg_data_out;
790
                            seg_cs      <= cpu_vma;
791
 
792
 
793
                          when others => -- $EXC0 to $EXFF
794
                            null;
795
                     end case;
796 19 dilbert57
         --
797 99 davidgb
                        --      $E100 to $EFFF reserved for future use
798 19 dilbert57
                        --
799 22 dilbert57
                when others =>
800
                          null;
801
         end case;
802 19 dilbert57
                --
803
                -- Everything else is RAM
804
                --
805 22 dilbert57
                else
806 19 dilbert57
                  cpu_data_in <= ram_data_out;
807
                  ram_cs      <= cpu_vma;
808
    end if;
809
end process;
810
 
811
 
812
--
813
-- 1M byte SRAM Control
814
-- Processes to read and write memory based on bus signals
815
--
816 99 davidgb
ram_process: process( cpu_rst, sys_clk,
817 19 dilbert57
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
818
                                               dat_addr, ram_cs,
819
                      ram1_ce, ram1_ub, ram1_lb, ram1_data,
820
                      ram2_ce, ram2_ub, ram2_lb, ram2_data,
821
                                                         ram_we, ram_oe )
822
begin
823 22 dilbert57
    --
824
    -- ram_hold signal helps 
825
    --
826 99 davidgb
    if( cpu_rst = '1' ) then
827 22 dilbert57
           ram_we   <= '0';
828
           ram_oe   <= '0';
829
    --
830
         -- Clock Hold on rising edge
831
         --
832
    elsif( sys_clk'event and sys_clk='1' ) then
833
           if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then
834
             ram_we   <= not cpu_rw;
835
             ram_oe   <=     cpu_rw;
836
      else
837
             ram_we   <= '0';
838
             ram_oe   <= '0';
839
      end if;
840
    end if;
841
 
842 19 dilbert57
         ram_wen  <= not ram_we;
843
         ram_oen  <= not ram_oe;
844
 
845
    ram1_ce   <= ram_cs and (not cpu_addr(1));
846
    ram1_ub   <= not cpu_addr(0);
847
    ram1_lb   <= cpu_addr(0);
848
    ram1_cen  <= not ram1_ce;
849
    ram1_ubn  <= not ram1_ub;
850
    ram1_lbn  <= not ram1_lb;
851
 
852
    ram2_ce   <= ram_cs and cpu_addr(1);
853
    ram2_ub   <= not cpu_addr(0);
854
    ram2_lb   <= cpu_addr(0);
855
    ram2_cen  <= not ram2_ce;
856
    ram2_ubn  <= not ram2_ub;
857
    ram2_lbn  <= not ram2_lb;
858
 
859
         ram_addr(17 downto 10) <= dat_addr(7 downto 0);
860
         ram_addr(9 downto 0) <= cpu_addr(11 downto 2);
861
 
862
    if ram_we = '1' and ram1_ce = '1' and ram1_lb = '1' then
863
                ram1_data(7 downto 0) <= cpu_data_out;
864
         else
865
      ram1_data(7 downto 0)  <= "ZZZZZZZZ";
866
         end if;
867
 
868
    if ram_we = '1' and ram1_ce = '1' and ram1_ub = '1' then
869
                ram1_data(15 downto 8) <= cpu_data_out;
870
         else
871
      ram1_data(15 downto 8)  <= "ZZZZZZZZ";
872
         end if;
873
 
874
    if ram_we = '1' and ram2_ce = '1' and ram2_lb = '1' then
875
                ram2_data(7 downto 0) <= cpu_data_out;
876
         else
877
      ram2_data(7 downto 0)  <= "ZZZZZZZZ";
878
         end if;
879
 
880
    if ram_we = '1' and ram2_ce = '1' and ram2_ub = '1' then
881
                ram2_data(15 downto 8) <= cpu_data_out;
882
         else
883
      ram2_data(15 downto 8)  <= "ZZZZZZZZ";
884
         end if;
885
 
886
         case cpu_addr(1 downto 0) is
887
         when "00" =>
888
      ram_data_out <= ram1_data(15 downto 8);
889
         when "01" =>
890
      ram_data_out <= ram1_data(7 downto 0);
891
         when "10" =>
892
      ram_data_out <= ram2_data(15 downto 8);
893
    when others =>
894
      ram_data_out <= ram2_data(7 downto 0);
895
    end case;
896
end process;
897
 
898
--
899
-- LEDS output register
900
--
901 99 davidgb
leds_output : process( cpu_clk, cpu_rst, switches )
902 19 dilbert57
begin
903 99 davidgb
        if cpu_rst = '1' then
904 19 dilbert57
                leds <= "00000000";
905
        elsif cpu_clk'event and cpu_clk='0' then
906
                if      leds_cs = '1' and cpu_rw = '0' then
907
                        leds <= cpu_data_out;
908
                end if;
909
        end if;
910
        leds_data_out <= switches;
911
end process;
912
 
913
--
914
-- Interrupts and other bus control signals
915
--
916 99 davidgb
interrupts : process(   sys_clk, rst_sw,
917
                                                                acia_irq, kbd_irq, nmi_sw )
918 19 dilbert57
begin
919 22 dilbert57
   if sys_clk'event and sys_clk = '1' then
920 99 davidgb
          cpu_rst  <= rst_sw; -- CPU reset is active high
921 22 dilbert57
   end if;
922 99 davidgb
        cpu_firq   <= kbd_irq;
923 22 dilbert57
        cpu_nmi    <= nmi_sw;
924
        cpu_irq    <= acia_irq;
925
        cpu_halt   <= '0';
926
        cpu_hold   <= '0';
927
end process;
928 19 dilbert57
 
929 22 dilbert57
--
930
-- ACIA pin assignments
931
--
932
acia_assignments : process( rxd, acia_txd )
933
begin
934
        acia_dcd_n <= '0';
935
        acia_cts_n <= '0';
936
        acia_rxd   <= rxd;
937
        txd        <= acia_txd;
938 19 dilbert57
end process;
939
 
940
 
941
end my_computer; --===================== End of architecture =======================--
942
 

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