OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S500E/] [System09_Digilent_3S500E.vhd] - Blame information for rev 115

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 109 davidgb
-- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008/04/08 14:59:48 davidgb Exp $
2 19 dilbert57
--===========================================================================----
3
--
4
--  S Y N T H E Z I A B L E    System09 - SOC.
5
--
6 109 davidgb
--===========================================================================----
7
--
8 19 dilbert57
--  This core adheres to the GNU public license  
9
--
10 109 davidgb
-- File name      : System09_Digilent_3S500E.vhd
11 19 dilbert57
--
12
-- Purpose        : Top level file for 6809 compatible system on a chip
13
--                  Designed with Xilinx XC3S500E Spartan 3E FPGA.
14
--                  Implemented With Digilent Xilinx Starter FPGA board,
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21 109 davidgb
-- Uses           : mon_rom  (kbug_rom2k.vhd) Monitor ROM
22 19 dilbert57
--                  cpu09    (cpu09.vhd)      CPU core
23
--                  miniuart (minitUART3.vhd) ACIA / MiniUART
24
--                           (rxunit3.vhd)
25
--                           (tx_unit3.vhd)
26
-- 
27
-- Author         : John E. Kent      
28
--                  dilbert57@opencores.org      
29
--
30
--===========================================================================----
31
--
32
-- Revision History:
33
--===========================================================================--
34
-- Version 0.1 - 20 March 2003
35
-- Version 0.2 - 30 March 2003
36
-- Version 0.3 - 29 April 2003
37
-- Version 0.4 - 29 June 2003
38
--
39
-- Version 0.5 - 19 July 2003
40
-- prints out "Hello World"
41
--
42
-- Version 0.6 - 5 September 2003
43
-- Runs SBUG
44
--
45
-- Version 1.0- 6 Sep 2003 - John Kent
46
-- Inverted CLK_50MHZ
47
-- Initial release to Open Cores
48
--
49
-- Version 1.1 - 17 Jan 2004 - John Kent
50
-- Updated miniUart.
51
--
52
-- Version 1.2 - 25 Jan 2004 - John Kent
53
-- removed signals "test_alu" and "test_cc" 
54
-- Trap hardware re-instated.
55
--
56
-- Version 1.3 - 11 Feb 2004 - John Kent
57
-- Designed forked off to produce System09_VDU
58
-- Added VDU component
59
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
60
-- UART Runs at 57.6 Kbps
61
--
62
-- Version 2.0 - 2 September 2004 - John Kent
63
-- ported to Digilent Xilinx Spartan3 starter board
64
--      removed Compaact Flash and Trap Logic.
65
-- Replaced SBUG with KBug9s
66
--
67
-- Version 3.0 - 22 April 2006 - John Kent
68
-- Port to Digilent Spartan 3E Starter board
69
-- Removed keyboard, vdu, timer, and trap logic
70
-- added PIA with counters attached.
71
-- Uses 32Kbytes of internal Block RAM
72 20 dilbert57
--
73
-- Version 4.0 - 8th April 2007 - John kent
74
-- Added VDU and PS/2 keyboard
75
-- Updated miniUART to ACIA6850
76
-- Reduce monitor ROM to 2KB
77
-- Re-assigned I/O port assignments so it is possible to run KBUG9
78
-- $E000 - ACIA
79
-- $E020 - Keyboard
80
-- $E030 - VDU
81
-- $E040 - Compact Flash (not implemented)
82
-- $E050 - Timer
83
-- $E060 - Bus trap
84
-- $E070 - Parallel I/O
85
--
86 19 dilbert57
--===========================================================================--
87
library ieee;
88
   use ieee.std_logic_1164.all;
89
   use IEEE.STD_LOGIC_ARITH.ALL;
90
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
91
   use ieee.numeric_std.all;
92
 
93 59 davidgb
entity my_system09 is
94 19 dilbert57
  port(
95
    CLK_50MHZ     : in  Std_Logic;  -- System Clock input
96
    BTN_SOUTH     : in  Std_Logic;
97
 
98 20 dilbert57
         -- PS/2 Keyboard
99
         PS2_CLK      : inout Std_logic;
100
         PS2_DATA     : inout Std_Logic;
101
 
102
         -- CRTC output signals
103
         VGA_VSYNC     : out Std_Logic;
104
    VGA_HSYNC     : out Std_Logic;
105
    VGA_BLUE      : out std_logic;
106
    VGA_GREEN     : out std_logic;
107
    VGA_RED       : out std_logic;
108
 
109 19 dilbert57
         -- Uart Interface
110
         RS232_DCE_RXD : in  std_logic;
111
    RS232_DCE_TXD : out std_logic;
112
 
113
         -- LEDS & Switches
114
         LED           : out std_logic_vector(7 downto 0)
115
         );
116 59 davidgb
end my_system09;
117 19 dilbert57
 
118
-------------------------------------------------------------------------------
119
-- Architecture for System09
120
-------------------------------------------------------------------------------
121 59 davidgb
architecture my_computer of my_system09 is
122 19 dilbert57
  -----------------------------------------------------------------------------
123 20 dilbert57
  -- constants
124
  -----------------------------------------------------------------------------
125 109 davidgb
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
126
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
127
  constant CPU_CLK_FREQ  : integer := 25000000;  -- CPU Clock
128
  constant BAUD_RATE     : integer := 57600;      -- Baud Rate
129
  constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
130 20 dilbert57
 
131
  -----------------------------------------------------------------------------
132 19 dilbert57
  -- Signals
133
  -----------------------------------------------------------------------------
134
  -- BOOT ROM
135 20 dilbert57
  signal rom_cs         : Std_logic;
136
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
137 19 dilbert57
 
138
  -- UART Interface signals
139 20 dilbert57
  signal uart_data_out  : Std_Logic_Vector(7 downto 0);
140
  signal uart_cs        : Std_Logic;
141
  signal uart_irq       : Std_Logic;
142
  signal uart_clk       : Std_Logic;
143
  signal rxbit          : Std_Logic;
144
  signal txbit          : Std_Logic;
145
  signal DCD_n          : Std_Logic;
146
  signal RTS_n          : Std_Logic;
147
  signal CTS_n          : Std_Logic;
148 19 dilbert57
 
149 20 dilbert57
  -- timer
150
  signal timer_data_out : std_logic_vector(7 downto 0);
151
  signal timer_cs       : std_logic;
152
  signal timer_irq      : std_logic;
153
 
154
  -- trap
155
  signal trap_cs        : std_logic;
156
  signal trap_data_out  : std_logic_vector(7 downto 0);
157
  signal trap_irq       : std_logic;
158
 
159 19 dilbert57
  -- PIA Interface signals
160 20 dilbert57
  signal pia_data_out   : Std_Logic_Vector(7 downto 0);
161
  signal pia_cs         : Std_Logic;
162
  signal pia_irq_a      : Std_Logic;
163
  signal pia_irq_b      : Std_Logic;
164 19 dilbert57
 
165 20 dilbert57
  -- keyboard port
166
  signal keyboard_data_out : std_logic_vector(7 downto 0);
167
  signal keyboard_cs       : std_logic;
168
  signal keyboard_irq      : std_logic;
169
 
170
  -- Video Display Unit
171 109 davidgb
  signal vga_clk      : std_logic;
172 20 dilbert57
  signal vdu_cs       : std_logic;
173
  signal vdu_data_out : std_logic_vector(7 downto 0);
174
 
175 19 dilbert57
  -- RAM
176
  signal ram_cs       : std_logic; -- memory chip select
177
  signal ram_data_out : std_logic_vector(7 downto 0);
178
 
179
  -- CPU Interface signals
180
  signal cpu_reset    : Std_Logic;
181
  signal cpu_clk      : Std_Logic;
182
  signal cpu_rw       : std_logic;
183
  signal cpu_vma      : std_logic;
184
  signal cpu_halt     : std_logic;
185
  signal cpu_hold     : std_logic;
186
  signal cpu_firq     : std_logic;
187
  signal cpu_irq      : std_logic;
188
  signal cpu_nmi      : std_logic;
189
  signal cpu_addr     : std_logic_vector(15 downto 0);
190
  signal cpu_data_in  : std_logic_vector(7 downto 0);
191
  signal cpu_data_out : std_logic_vector(7 downto 0);
192
 
193 20 dilbert57
  -- CLK_50MHZ clock divide by 2
194
  signal clock_div    : std_logic_vector(1 downto 0);
195
  signal SysClk       : std_logic;
196
  signal Reset_n      : std_logic;
197 19 dilbert57
  signal CountL       : std_logic_vector(23 downto 0);
198
 
199
-----------------------------------------------------------------
200
--
201
-- CPU09 CPU core
202
--
203
-----------------------------------------------------------------
204
 
205
component cpu09
206
  port (
207 109 davidgb
         clk      :      in std_logic;
208
    rst      :  in std_logic;
209
    rw       :  out std_logic;
210
    vma      :  out std_logic;
211
    address  : out std_logic_vector(15 downto 0);
212
         data_out : out std_logic_vector(7 downto 0);
213
    data_in  :  in std_logic_vector(7 downto 0);
214
         irq      :  in std_logic;
215
         nmi      :  in std_logic;
216
         firq     :  in std_logic;
217
         halt     :  in std_logic;
218
         hold     :  in std_logic
219 19 dilbert57
  );
220
end component;
221
 
222
 
223
----------------------------------------
224
--
225
-- Block RAM Monitor ROM
226
--
227
----------------------------------------
228 20 dilbert57
component mon_rom
229 19 dilbert57
    Port (
230 109 davidgb
       clk      : in  std_logic;
231
                 rst      : in  std_logic;
232
                 cs       : in  std_logic;
233
                 rw       : in  std_logic;
234
       addr     : in  std_logic_vector (10 downto 0);
235
       data_in  : in  std_logic_vector (7 downto 0);
236
       data_out : out std_logic_vector (7 downto 0)
237 19 dilbert57
    );
238
end component;
239
 
240
----------------------------------------
241
--
242
-- Block RAM Monitor
243
--
244
----------------------------------------
245
component ram_32k
246
    Port (
247 109 davidgb
       clk      : in  std_logic;
248
                 rst      : in  std_logic;
249
                 cs       : in  std_logic;
250
                 rw       : in  std_logic;
251
       addr     : in  std_logic_vector (14 downto 0);
252
       data_in  : in  std_logic_vector (7 downto 0);
253
       data_out : out std_logic_vector (7 downto 0)
254 19 dilbert57
    );
255
end component;
256
 
257
-----------------------------------------------------------------
258
--
259
-- 6822 compatible PIA with counters
260
--
261
-----------------------------------------------------------------
262
 
263
component pia_timer
264
        port (
265
         clk       : in    std_logic;
266
    rst       : in    std_logic;
267
    cs        : in    std_logic;
268
    rw        : in    std_logic;
269
    addr      : in    std_logic_vector(1 downto 0);
270
    data_in   : in    std_logic_vector(7 downto 0);
271
         data_out  : out   std_logic_vector(7 downto 0);
272
         irqa      : out   std_logic;
273
         irqb      : out   std_logic
274
         );
275
end component;
276
 
277 20 dilbert57
 
278 19 dilbert57
-----------------------------------------------------------------
279
--
280 20 dilbert57
-- 6850 ACIA/UART
281 19 dilbert57
--
282
-----------------------------------------------------------------
283
 
284 20 dilbert57
component ACIA_6850
285 19 dilbert57
  port (
286
     clk      : in  Std_Logic;  -- System Clock
287
     rst      : in  Std_Logic;  -- Reset input (active high)
288
     cs       : in  Std_Logic;  -- miniUART Chip Select
289
     rw       : in  Std_Logic;  -- Read / Not Write
290 109 davidgb
     addr     : in  Std_Logic;  -- Register Select
291
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
292
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
293 19 dilbert57
     irq      : out Std_Logic;  -- Interrupt
294
     RxC      : in  Std_Logic;  -- Receive Baud Clock
295
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
296
     RxD      : in  Std_Logic;  -- Receive Data
297
     TxD      : out Std_Logic;  -- Transmit Data
298
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
299
     CTS_n    : in  Std_Logic;  -- Clear To Send
300
     RTS_n    : out Std_Logic );  -- Request To send
301
end component;
302
 
303 20 dilbert57
-----------------------------------------------------------------
304
--
305
-- ACIA Clock divider
306
--
307
-----------------------------------------------------------------
308 19 dilbert57
 
309 20 dilbert57
component ACIA_Clock
310
  generic (
311 109 davidgb
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
312
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
313 20 dilbert57
  );
314
  port (
315
     clk      : in  Std_Logic;  -- System Clock Input
316
          ACIA_clk : out Std_logic   -- ACIA Clock output
317
  );
318
end component;
319
 
320
----------------------------------------
321
--
322
-- Timer module
323
--
324
----------------------------------------
325
 
326
component timer
327
  port (
328
     clk       : in std_logic;
329
     rst       : in std_logic;
330
     cs        : in std_logic;
331
     rw        : in std_logic;
332
     addr      : in std_logic;
333
     data_in   : in std_logic_vector(7 downto 0);
334
          data_out  : out std_logic_vector(7 downto 0);
335 59 davidgb
          irq       : out std_logic
336 20 dilbert57
          );
337
end component;
338
 
339
------------------------------------------------------------
340
--
341
-- Bus Trap logic
342
--
343
------------------------------------------------------------
344
 
345
component trap
346
        port (
347
         clk        : in  std_logic;
348
    rst        : in  std_logic;
349
    cs         : in  std_logic;
350
    rw         : in  std_logic;
351
    vma        : in  std_logic;
352
    addr       : in  std_logic_vector(15 downto 0);
353
    data_in    : in  std_logic_vector(7 downto 0);
354
         data_out   : out std_logic_vector(7 downto 0);
355
         irq        : out std_logic
356
  );
357
end component;
358
 
359
----------------------------------------
360
--
361
-- PS/2 Keyboard
362
--
363
----------------------------------------
364
 
365
component keyboard
366
  generic(
367 109 davidgb
  KBD_CLK_FREQ : integer := CPU_CLK_FREQ
368 20 dilbert57
  );
369
  port(
370
  clk             : in    std_logic;
371
  rst             : in    std_logic;
372
  cs              : in    std_logic;
373
  rw              : in    std_logic;
374
  addr            : in    std_logic;
375
  data_in         : in    std_logic_vector(7 downto 0);
376
  data_out        : out   std_logic_vector(7 downto 0);
377
  irq             : out   std_logic;
378
  kbd_clk         : inout std_logic;
379
  kbd_data        : inout std_logic
380
  );
381
end component;
382
 
383
----------------------------------------
384
--
385
-- Video Display Unit.
386
--
387
----------------------------------------
388
component vdu8
389
      generic(
390 109 davidgb
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- 25MHz
391
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
392
             VGA_HOR_CHAR_PIXELS    : integer :=  8; -- PIXELS 0.32us
393
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
394
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
395
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
396
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
397
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
398
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
399
             VGA_VER_SYNC           : integer :=  2; -- LINES 0.064ms
400
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
401 20 dilbert57
      );
402
      port(
403
                -- control register interface
404
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
405
      vdu_rst      : in  std_logic;
406
                vdu_cs       : in  std_logic;
407
                vdu_rw       : in  std_logic;
408
                vdu_addr     : in  std_logic_vector(2 downto 0);
409
      vdu_data_in  : in  std_logic_vector(7 downto 0);
410
      vdu_data_out : out std_logic_vector(7 downto 0);
411
 
412
      -- vga port connections
413
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
414
      vga_red_o    : out std_logic;
415
      vga_green_o  : out std_logic;
416
      vga_blue_o   : out std_logic;
417
      vga_hsync_o  : out std_logic;
418
      vga_vsync_o  : out std_logic
419
   );
420
end component;
421
 
422
 
423 19 dilbert57
component BUFG
424
port (
425
     i: in std_logic;
426
          o: out std_logic
427
  );
428
end component;
429
 
430
begin
431
  -----------------------------------------------------------------------------
432
  -- Instantiation of internal components
433
  -----------------------------------------------------------------------------
434
 
435
my_cpu : cpu09  port map (
436
         clk         => cpu_clk,
437
    rst       => cpu_reset,
438
    rw       => cpu_rw,
439
    vma       => cpu_vma,
440
    address   => cpu_addr(15 downto 0),
441 109 davidgb
         data_out  => cpu_data_out,
442 19 dilbert57
    data_in   => cpu_data_in,
443
         irq       => cpu_irq,
444
         nmi       => cpu_nmi,
445 109 davidgb
         firq      => cpu_firq,
446
         halt      => cpu_halt,
447
         hold      => cpu_hold
448 19 dilbert57
  );
449
 
450 20 dilbert57
my_rom : mon_rom port map (
451 109 davidgb
       clk      => cpu_clk,
452
                 rst      => cpu_reset,
453
                 cs       => rom_cs,
454
                 rw       => '1',
455
       addr     => cpu_addr(10 downto 0),
456
       data_in  => cpu_data_out,
457
       data_out => rom_data_out
458 19 dilbert57
    );
459
 
460
my_ram : ram_32k port map (
461 109 davidgb
       clk      => cpu_clk,
462
                 rst      => cpu_reset,
463
                 cs       => ram_cs,
464
                 rw       => cpu_rw,
465
       addr     => cpu_addr(14 downto 0),
466
       data_in  => cpu_data_out,
467
       data_out => ram_data_out
468 19 dilbert57
    );
469
 
470
my_pia  : pia_timer port map (
471
         clk         => cpu_clk,
472
         rst       => cpu_reset,
473
    cs        => pia_cs,
474
         rw        => cpu_rw,
475
    addr      => cpu_addr(1 downto 0),
476
         data_in   => cpu_data_out,
477
         data_out  => pia_data_out,
478
    irqa      => pia_irq_a,
479
    irqb      => pia_irq_b
480
         );
481
 
482 20 dilbert57
 
483
----------------------------------------
484
--
485
-- ACIA/UART Serial interface
486
--
487
----------------------------------------
488
my_ACIA  : ACIA_6850 port map (
489 19 dilbert57
         clk         => cpu_clk,
490
         rst       => cpu_reset,
491
    cs        => uart_cs,
492
         rw        => cpu_rw,
493 109 davidgb
    addr      => cpu_addr(0),
494
         data_in   => cpu_data_out,
495
         data_out  => uart_data_out,
496 19 dilbert57
    irq       => uart_irq,
497 20 dilbert57
         RxC       => uart_clk,
498
         TxC       => uart_clk,
499
         RxD       => rxbit,
500
         TxD       => txbit,
501 19 dilbert57
         DCD_n     => dcd_n,
502
         CTS_n     => cts_n,
503
         RTS_n     => rts_n
504
         );
505
 
506 20 dilbert57
----------------------------------------
507
--
508
-- ACIA Clock
509
--
510
----------------------------------------
511
my_ACIA_Clock : ACIA_Clock
512
  generic map(
513 109 davidgb
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
514
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
515 20 dilbert57
  )
516
  port map(
517
    clk        => SysClk,
518
    acia_clk   => uart_clk
519
  );
520 19 dilbert57
 
521 20 dilbert57
 
522
 
523
----------------------------------------
524
--
525
-- PS/2 Keyboard Interface
526
--
527
----------------------------------------
528
my_keyboard : keyboard
529
   generic map (
530 109 davidgb
        KBD_CLK_FREQ => CPU_CLK_FREQ
531 20 dilbert57
        )
532
   port map(
533
        clk          => cpu_clk,
534
        rst          => cpu_reset,
535
        cs           => keyboard_cs,
536
        rw           => cpu_rw,
537
        addr         => cpu_addr(0),
538
        data_in      => cpu_data_out(7 downto 0),
539
        data_out     => keyboard_data_out(7 downto 0),
540
        irq          => keyboard_irq,
541
        kbd_clk      => PS2_CLK,
542
        kbd_data     => PS2_DATA
543
        );
544
 
545
----------------------------------------
546
--
547
-- Video Display Unit instantiation
548
--
549
----------------------------------------
550
my_vdu : vdu8
551
  generic map(
552 109 davidgb
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
553 20 dilbert57
           VGA_HOR_CHARS          => 80, -- CHARACTERS
554 109 davidgb
           VGA_HOR_CHAR_PIXELS    =>  8,  -- PIXELS
555
           VGA_HOR_FRONT_PORCH    => 16, -- PIXELS
556
           VGA_HOR_SYNC           => 96, -- PIXELS
557
           VGA_HOR_BACK_PORCH     => 48, -- PIXELS
558 20 dilbert57
           VGA_VER_CHARS          => 25, -- CHARACTERS
559 109 davidgb
           VGA_VER_CHAR_LINES     => 16, -- LINES
560
           VGA_VER_FRONT_PORCH    => 10, -- LINES
561
           VGA_VER_SYNC           =>  2, -- LINES
562
           VGA_VER_FRONT_PORCH    => 34  -- LINES
563 20 dilbert57
  )
564
  port map(
565
 
566
                -- Control Registers
567
                vdu_clk       => cpu_clk,                                        -- 25 MHz System Clock in
568
      vdu_rst       => cpu_reset,
569
                vdu_cs        => vdu_cs,
570
                vdu_rw        => cpu_rw,
571
                vdu_addr      => cpu_addr(2 downto 0),
572
                vdu_data_in   => cpu_data_out,
573
                vdu_data_out  => vdu_data_out,
574
 
575
      -- vga port connections
576 109 davidgb
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
577 20 dilbert57
      vga_red_o     => vga_red,
578
      vga_green_o   => vga_green,
579
      vga_blue_o    => vga_blue,
580
      vga_hsync_o   => vga_hsync,
581
      vga_vsync_o   => vga_vsync
582
   );
583
 
584
 
585
----------------------------------------
586
--
587
-- Timer Module
588
--
589
----------------------------------------
590
my_timer  : timer port map (
591
    clk       => cpu_clk,
592
         rst       => cpu_reset,
593
    cs        => timer_cs,
594
         rw        => cpu_rw,
595
    addr      => cpu_addr(0),
596
         data_in   => cpu_data_out,
597
         data_out  => timer_data_out,
598 59 davidgb
    irq       => timer_irq
599 20 dilbert57
    );
600
 
601
----------------------------------------
602
--
603
-- Bus Trap Interrupt logic
604
--
605
----------------------------------------
606
my_trap : trap port map (
607
         clk        => cpu_clk,
608
    rst        => cpu_reset,
609
    cs         => trap_cs,
610
    rw         => cpu_rw,
611
         vma        => cpu_vma,
612
    addr       => cpu_addr,
613
    data_in    => cpu_data_out,
614
         data_out   => trap_data_out,
615
         irq        => trap_irq
616
    );
617
 
618
--
619
-- 25 MHz CPU clock
620
--
621
cpu_clk_buffer : BUFG port map(
622
    i => clock_div(0),
623 19 dilbert57
         o => cpu_clk
624 20 dilbert57
    );
625
 
626
--
627
-- 25 MHz VGA Pixel clock
628
--
629
vga_clk_buffer : BUFG port map(
630
    i => clock_div(0),
631 109 davidgb
         o => vga_clk
632 19 dilbert57
    );
633
 
634
----------------------------------------------------------------------
635
--
636
-- Process to decode memory map
637
--
638
----------------------------------------------------------------------
639
 
640 20 dilbert57
mem_decode: process( cpu_clk, Reset_n,
641 19 dilbert57
                     cpu_addr, cpu_rw, cpu_vma,
642 20 dilbert57
                                              rom_data_out,
643 19 dilbert57
                                                        ram_data_out,
644 20 dilbert57
                                                   timer_data_out,
645
                                                        trap_data_out,
646
                                                        pia_data_out,
647 19 dilbert57
                                                   uart_data_out,
648 20 dilbert57
                                                        keyboard_data_out,
649
                                                        vdu_data_out )
650
variable decode_addr : std_logic_vector(3 downto 0);
651 19 dilbert57
begin
652 20 dilbert57
--    decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
653
    decode_addr := cpu_addr(15 downto 12);
654
 
655
      case decode_addr is
656 19 dilbert57
           --
657 20 dilbert57
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
658 19 dilbert57
                --
659 20 dilbert57
                when "1111" => -- $F000 - $FFFF
660 19 dilbert57
                   cpu_data_in <= rom_data_out;
661 20 dilbert57
                        rom_cs      <= cpu_vma;              -- read ROM
662 19 dilbert57
                        ram_cs      <= '0';
663
                        uart_cs     <= '0';
664 20 dilbert57
                        timer_cs    <= '0';
665
                        trap_cs     <= '0';
666 19 dilbert57
                        pia_cs      <= '0';
667 20 dilbert57
                        keyboard_cs <= '0';
668
                        vdu_cs      <= '0';
669
 
670 19 dilbert57
      --
671 20 dilbert57
                -- IO Devices $E000 - $EFFF
672 19 dilbert57
                --
673 20 dilbert57
                when "1110" => -- $E000 - $E7FF
674 19 dilbert57
                        rom_cs    <= '0';
675
                        ram_cs    <= '0';
676 20 dilbert57
                   case cpu_addr(7 downto 4) is
677 19 dilbert57
                        --
678 20 dilbert57
                        -- UART / ACIA $E000
679 19 dilbert57
                        --
680 20 dilbert57
                        when "0000" => -- $E000
681
                     cpu_data_in <= uart_data_out;
682
                          uart_cs     <= cpu_vma;
683
                          timer_cs    <= '0';
684
                          trap_cs     <= '0';
685
                          pia_cs      <= '0';
686
                          keyboard_cs <= '0';
687
                          vdu_cs      <= '0';
688
 
689
                        --
690
                        -- WD1771 FDC sites at $E010-$E01F
691
                        --
692
                        when "0001" => -- $E010
693
           cpu_data_in <= (others => '0');
694 19 dilbert57
                          uart_cs     <= '0';
695 20 dilbert57
                          timer_cs    <= '0';
696
                          trap_cs     <= '0';
697
                          pia_cs      <= '0';
698
                          keyboard_cs <= '0';
699
                          vdu_cs      <= '0';
700
 
701
         --
702
         -- Keyboard port $E020 - $E02F
703 19 dilbert57
                        --
704 20 dilbert57
                        when "0010" => -- $E020
705
           cpu_data_in <= keyboard_data_out;
706
                          uart_cs     <= '0';
707
           timer_cs    <= '0';
708
                          trap_cs     <= '0';
709
                          pia_cs      <= '0';
710
                          keyboard_cs <= cpu_vma;
711
                          vdu_cs      <= '0';
712
 
713
         --
714
         -- VDU port $E030 - $E03F
715 19 dilbert57
                        --
716 20 dilbert57
                        when "0011" => -- $E030
717
           cpu_data_in <= vdu_data_out;
718
                          uart_cs     <= '0';
719
           timer_cs    <= '0';
720
                          trap_cs     <= '0';
721
                          pia_cs      <= '0';
722
                          keyboard_cs <= '0';
723
                          vdu_cs      <= cpu_vma;
724 19 dilbert57
 
725 20 dilbert57
         --
726
                        -- Compact Flash $E040 - $E04F
727
                        --
728
                        when "0100" => -- $E040
729
           cpu_data_in <= (others => '0');
730 19 dilbert57
                          uart_cs     <= '0';
731 20 dilbert57
                          timer_cs    <= '0';
732
                          trap_cs     <= '0';
733
                          pia_cs      <= '0';
734
                          keyboard_cs <= '0';
735
                          vdu_cs      <= '0';
736
 
737
         --
738
         -- Timer $E050 - $E05F
739
                        --
740
                        when "0101" => -- $E050
741
           cpu_data_in <= timer_data_out;
742
                          uart_cs     <= '0';
743
           timer_cs    <= cpu_vma;
744
                          trap_cs     <= '0';
745
                          pia_cs      <= '0';
746
                          keyboard_cs <= '0';
747
                          vdu_cs      <= '0';
748
 
749
         --
750
         -- Bus Trap Logic $E060 - $E06F
751
                        --
752
                        when "0110" => -- $E060
753
           cpu_data_in <= trap_data_out;
754
                          uart_cs     <= '0';
755
           timer_cs    <= '0';
756
                          trap_cs     <= cpu_vma;
757
                          pia_cs      <= '0';
758
                          keyboard_cs <= '0';
759
                          vdu_cs      <= '0';
760
 
761
         --
762
         -- I/O port $E070 - $E07F
763
                        --
764
                        when "0111" => -- $E070
765
           cpu_data_in <= pia_data_out;
766
                          uart_cs     <= '0';
767
           timer_cs    <= '0';
768
                          trap_cs     <= '0';
769
                          pia_cs      <= cpu_vma;
770
                          keyboard_cs <= '0';
771
                          vdu_cs      <= '0';
772
 
773
                        when others => -- $E080 to $E7FF
774
           cpu_data_in <= (others => '0');
775
                          uart_cs     <= '0';
776
                          timer_cs    <= '0';
777
                          trap_cs     <= '0';
778
                          pia_cs      <= '0';
779
                          keyboard_cs <= '0';
780
                          vdu_cs      <= '0';
781 19 dilbert57
                   end case;
782 20 dilbert57
 
783 19 dilbert57
                --
784 20 dilbert57
                -- $8000 to $DFFF = null
785
                --
786
      when "1101" | "1100" | "1011" | "1010" |
787
                     "1001" | "1000" =>
788
                  cpu_data_in <= (others => '0');
789
                  rom_cs      <= '0';
790
                  ram_cs      <= '0';
791
                  uart_cs     <= '0';
792
                  timer_cs    <= '0';
793
                  trap_cs     <= '0';
794
                  pia_cs      <= '0';
795
                  keyboard_cs <= '0';
796
                  vdu_cs      <= '0';
797
                --
798 19 dilbert57
                -- Everything else is RAM
799
                --
800
                when others =>
801
                  cpu_data_in <= ram_data_out;
802
                  rom_cs      <= '0';
803
                  ram_cs      <= cpu_vma;
804
                  uart_cs     <= '0';
805 20 dilbert57
                  timer_cs    <= '0';
806
                  trap_cs     <= '0';
807
                  pia_cs      <= '0';
808
                  keyboard_cs <= '0';
809
                  vdu_cs      <= '0';
810
                end case;
811 19 dilbert57
end process;
812
 
813
--
814
-- Interrupts and other bus control signals
815
--
816 20 dilbert57
interrupts : process( Reset_n,
817
                      pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
818 19 dilbert57
                                                         )
819
begin
820 20 dilbert57
         cpu_reset <= not Reset_n; -- CPU reset is active high
821
    cpu_irq   <= uart_irq or keyboard_irq;
822
         cpu_nmi   <= pia_irq_a or trap_irq;
823
         cpu_firq  <= pia_irq_b or timer_irq;
824 19 dilbert57
         cpu_halt  <= '0';
825
    cpu_hold  <= '0';
826
end process;
827
 
828
--
829
--
830 20 dilbert57
my_led_flasher: process( SysClk, Reset_n, CountL )
831 19 dilbert57
begin
832 20 dilbert57
    if Reset_n = '0' then
833
                   CountL <= "000000000000000000000000";
834
    elsif(SysClk'event and SysClk = '0') then
835
                   CountL <= CountL + 1;
836 19 dilbert57
    end if;
837 20 dilbert57
         LED(7 downto 0) <= CountL(23 downto 16);
838 19 dilbert57
end process;
839
 
840
--
841 20 dilbert57
-- Clock divider
842 19 dilbert57
--
843 20 dilbert57
my_clock_divider: process( SysClk )
844 19 dilbert57
begin
845 20 dilbert57
        if SysClk'event and SysClk='0' then
846
                clock_div <= clock_div + "01";
847
        end if;
848 19 dilbert57
end process;
849
 
850
DCD_n <= '0';
851
CTS_n <= '0';
852 20 dilbert57
Reset_n <= not BTN_SOUTH; -- CPU reset is active high
853
SysClk <= CLK_50MHZ;
854
rxbit <= RS232_DCE_RXD;
855
RS232_DCE_TXD <= txbit;
856 19 dilbert57
 
857
end my_computer; --===================== End of architecture =======================--
858
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.