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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S500E/] [System09_Digilent_3S500E.vhd] - Blame information for rev 127

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Line No. Rev Author Line
1 109 davidgb
-- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008/04/08 14:59:48 davidgb Exp $
2 118 dilbert57
--===========================================================================
3 19 dilbert57
--
4 118 dilbert57
--          System09 - SoC for the Digilent Spartan 3E Starter board
5 19 dilbert57
--
6 118 dilbert57
--===========================================================================
7 109 davidgb
--
8 118 dilbert57
-- File name      : System09_Digilent_3S500E.vhd
9
--
10
-- Entity name    : my_system09
11 19 dilbert57
--
12
-- Purpose        : Top level file for 6809 compatible system on a chip
13
--                  Designed with Xilinx XC3S500E Spartan 3E FPGA.
14
--                  Implemented With Digilent Xilinx Starter FPGA board,
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21 118 dilbert57
-- Uses           : clock_div  (../vhdl/clock_div.vhd)      System clock divider
22
--                  flasher    (../vhdl/flasher.vhd)        LED flasher
23
--                  ram_32k    (../Spartan3/ram32k_b16.vhd) 32K block RAM
24
--                  cpu09      (../vhdl/cpu09.vhd)          CPU core
25
--                  mon_rom    (../spartan3/sys09bug_3se_rom2k_b16.vhd) Monitor ROM
26
--                  acia6850   (../vhdl/acia6850.vhd)       ACIA
27
--                  ACIA_Clock (../vhdl/ACIA_Clock.vhd)     ACIA Baud Clock Divider
28
--                  keyboard   (../vhdl/keyboard.vhd)       PS/2 Keyboard Interface
29
--                  vdu8       (../vhdl/vdu8.vhd)           80 x 25 Video Display
30
--                  timer      (../vhdl/timer.vhd)          Timer component
31
--                  pia_timer  (../vhdl/pia_timer.vhd)      PIA interrupt Timer cmponent
32
--                  trap            (../vhdl/trap.vhd)           Hardware Breakpoint Bus Trap
33
--                  vdu8       (../vhdl/vdu8.vhd)           VDU
34 19 dilbert57
-- 
35
-- Author         : John E. Kent      
36
--                  dilbert57@opencores.org      
37 118 dilbert57
--      Memory Map     :
38
--
39
-- $0000 - $7FFF System Block RAM
40
-- $E000 - ACIA (SWTPc)
41
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
42
-- $E020 - Keyboard
43
-- $E030 - VDU
44
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
45
-- $E050 - Timer
46
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
47
-- $E070 - PIA Single Step Timer (was Reserved for Trace Buffer)
48
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
49
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
50
-- $E0A0 - reserved for SPP Printer Port
51
-- $E0B0 - Reserved
52
-- $E0C0 - Reserved
53
-- $E100 - $E13F Reserved IDE / Compact Flash Card
54
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
55
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
56
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
57
-- $E200 - $EFFF Dual Port RAM interface
58
-- $F000 - $F7FF Reserved SWTPc DMAF-2
59
-- $F800 - $FFFF Sys09bug ROM (Read only)
60
-- $FFF0 - $FFFF Reserved for DAT - Dynamic Address Translation (Write Only)
61 19 dilbert57
--
62 118 dilbert57
--  Copyright (C) 2003 - 2010 John Kent
63
--
64
--  This program is free software: you can redistribute it and/or modify
65
--  it under the terms of the GNU General Public License as published by
66
--  the Free Software Foundation, either version 3 of the License, or
67
--  (at your option) any later version.
68
--
69
--  This program is distributed in the hope that it will be useful,
70
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
71
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
72
--  GNU General Public License for more details.
73
--
74
--  You should have received a copy of the GNU General Public License
75
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
76
--
77
--===========================================================================
78 19 dilbert57
--
79 118 dilbert57
--                              Revision History:
80
--
81
--===========================================================================
82 19 dilbert57
-- Version 0.1 - 20 March 2003
83
-- Version 0.2 - 30 March 2003
84
-- Version 0.3 - 29 April 2003
85
-- Version 0.4 - 29 June 2003
86
--
87
-- Version 0.5 - 19 July 2003
88
-- prints out "Hello World"
89
--
90
-- Version 0.6 - 5 September 2003
91
-- Runs SBUG
92
--
93
-- Version 1.0- 6 Sep 2003 - John Kent
94
-- Inverted CLK_50MHZ
95
-- Initial release to Open Cores
96
--
97
-- Version 1.1 - 17 Jan 2004 - John Kent
98
-- Updated miniUart.
99
--
100
-- Version 1.2 - 25 Jan 2004 - John Kent
101
-- removed signals "test_alu" and "test_cc" 
102
-- Trap hardware re-instated.
103
--
104
-- Version 1.3 - 11 Feb 2004 - John Kent
105
-- Designed forked off to produce System09_VDU
106
-- Added VDU component
107
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
108
-- UART Runs at 57.6 Kbps
109
--
110
-- Version 2.0 - 2 September 2004 - John Kent
111
-- ported to Digilent Xilinx Spartan3 starter board
112
--      removed Compaact Flash and Trap Logic.
113
-- Replaced SBUG with KBug9s
114
--
115
-- Version 3.0 - 22 April 2006 - John Kent
116
-- Port to Digilent Spartan 3E Starter board
117
-- Removed keyboard, vdu, timer, and trap logic
118
-- added PIA with counters attached.
119
-- Uses 32Kbytes of internal Block RAM
120 20 dilbert57
--
121
-- Version 4.0 - 8th April 2007 - John kent
122
-- Added VDU and PS/2 keyboard
123
-- Updated miniUART to ACIA6850
124
-- Reduce monitor ROM to 2KB
125
-- Re-assigned I/O port assignments so it is possible to run KBUG9
126
-- $E000 - ACIA
127
-- $E020 - Keyboard
128
-- $E030 - VDU
129
-- $E040 - Compact Flash (not implemented)
130
-- $E050 - Timer
131
-- $E060 - Bus trap
132
-- $E070 - Parallel I/O
133 118 dilbert57
--
134
-- Version 4.1 - July / september 2010
135
-- Updated VDU interface
136
-- and possible other changes.
137
--
138
-- Version 4.2 - 14th September 2010
139
-- Replaced ACIA_6850 with acia6850
140
-- Cleaned up decoding
141
-- Added Flasher component
142
-- Added Clock Divider component
143
--
144 19 dilbert57
--===========================================================================--
145
library ieee;
146
   use ieee.std_logic_1164.all;
147
   use IEEE.STD_LOGIC_ARITH.ALL;
148
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
149
   use ieee.numeric_std.all;
150
 
151 59 davidgb
entity my_system09 is
152 19 dilbert57
  port(
153
    CLK_50MHZ     : in  Std_Logic;  -- System Clock input
154
    BTN_SOUTH     : in  Std_Logic;
155
 
156 20 dilbert57
         -- PS/2 Keyboard
157
         PS2_CLK      : inout Std_logic;
158
         PS2_DATA     : inout Std_Logic;
159
 
160
         -- CRTC output signals
161
         VGA_VSYNC     : out Std_Logic;
162
    VGA_HSYNC     : out Std_Logic;
163
    VGA_BLUE      : out std_logic;
164
    VGA_GREEN     : out std_logic;
165
    VGA_RED       : out std_logic;
166
 
167 19 dilbert57
         -- Uart Interface
168
         RS232_DCE_RXD : in  std_logic;
169
    RS232_DCE_TXD : out std_logic;
170
 
171
         -- LEDS & Switches
172
         LED           : out std_logic_vector(7 downto 0)
173
         );
174 59 davidgb
end my_system09;
175 19 dilbert57
 
176
-------------------------------------------------------------------------------
177
-- Architecture for System09
178
-------------------------------------------------------------------------------
179 59 davidgb
architecture my_computer of my_system09 is
180 19 dilbert57
  -----------------------------------------------------------------------------
181 20 dilbert57
  -- constants
182
  -----------------------------------------------------------------------------
183 109 davidgb
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
184
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
185
  constant CPU_CLK_FREQ  : integer := 25000000;  -- CPU Clock
186
  constant BAUD_RATE     : integer := 57600;      -- Baud Rate
187
  constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
188 20 dilbert57
 
189
  -----------------------------------------------------------------------------
190 19 dilbert57
  -- Signals
191
  -----------------------------------------------------------------------------
192 118 dilbert57
  -- Clocks
193
  signal sys_clk        : std_logic;
194
  signal vga_clk        : std_logic;
195
 
196 19 dilbert57
  -- BOOT ROM
197 20 dilbert57
  signal rom_cs         : Std_logic;
198
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
199 19 dilbert57
 
200
  -- UART Interface signals
201 20 dilbert57
  signal uart_data_out  : Std_Logic_Vector(7 downto 0);
202
  signal uart_cs        : Std_Logic;
203
  signal uart_irq       : Std_Logic;
204
  signal uart_clk       : Std_Logic;
205 19 dilbert57
 
206 20 dilbert57
  -- timer
207
  signal timer_data_out : std_logic_vector(7 downto 0);
208
  signal timer_cs       : std_logic;
209
  signal timer_irq      : std_logic;
210
 
211
  -- trap
212
  signal trap_cs        : std_logic;
213
  signal trap_data_out  : std_logic_vector(7 downto 0);
214
  signal trap_irq       : std_logic;
215
 
216 19 dilbert57
  -- PIA Interface signals
217 20 dilbert57
  signal pia_data_out   : Std_Logic_Vector(7 downto 0);
218
  signal pia_cs         : Std_Logic;
219
  signal pia_irq_a      : Std_Logic;
220
  signal pia_irq_b      : Std_Logic;
221 19 dilbert57
 
222 20 dilbert57
  -- keyboard port
223 118 dilbert57
  signal kbd_data_out   : std_logic_vector(7 downto 0);
224
  signal kbd_cs         : std_logic;
225
  signal kbd_irq        : std_logic;
226 20 dilbert57
 
227
  -- Video Display Unit
228 118 dilbert57
  signal vdu_cs         : std_logic;
229
  signal vdu_data_out   : std_logic_vector(7 downto 0);
230 20 dilbert57
 
231 19 dilbert57
  -- RAM
232 118 dilbert57
  signal ram_cs         : std_logic; -- memory chip select
233
  signal ram_data_out   : std_logic_vector(7 downto 0);
234 19 dilbert57
 
235
  -- CPU Interface signals
236 118 dilbert57
  signal cpu_rst        : Std_Logic;
237
  signal cpu_clk        : Std_Logic;
238
  signal cpu_rw         : std_logic;
239
  signal cpu_vma        : std_logic;
240
  signal cpu_halt       : std_logic;
241
  signal cpu_hold       : std_logic;
242
  signal cpu_firq       : std_logic;
243
  signal cpu_irq        : std_logic;
244
  signal cpu_nmi        : std_logic;
245
  signal cpu_addr       : std_logic_vector(15 downto 0);
246
  signal cpu_data_in    : std_logic_vector(7 downto 0);
247
  signal cpu_data_out   : std_logic_vector(7 downto 0);
248
 
249
-----------------------------------------------------------------
250
--
251
--                     Clock generator
252
--
253
-----------------------------------------------------------------
254
 
255
component clock_div
256
  port(
257
    clk_in      : in  std_Logic;  -- System Clock input
258
         sys_clk     : out std_logic;  -- System Clock Out    (1/1)
259
         vga_clk     : out std_logic;  -- VGA Pixel Clock Out (1/2)
260
    cpu_clk     : out std_logic   -- CPU Clock Out       (1/4)
261
  );
262
end component;
263
 
264
-----------------------------------------------------------------
265
--
266
--                      LED Flasher
267
--
268
-----------------------------------------------------------------
269 19 dilbert57
 
270 118 dilbert57
component flasher
271
  port (
272
    clk      : in  std_logic;           -- Clock input
273
    rst      : in  std_logic;           -- Reset input (active high)
274
    LED      : out Std_Logic            -- LED output        
275
  );
276
end component;
277 19 dilbert57
 
278
-----------------------------------------------------------------
279
--
280
-- CPU09 CPU core
281
--
282
-----------------------------------------------------------------
283
 
284
component cpu09
285
  port (
286 109 davidgb
         clk      :      in std_logic;
287
    rst      :  in std_logic;
288 118 dilbert57
    vma      :  out std_logic;
289
    addr     : out std_logic_vector(15 downto 0);
290 109 davidgb
    rw       :  out std_logic;
291
         data_out : out std_logic_vector(7 downto 0);
292
    data_in  :  in std_logic_vector(7 downto 0);
293
         irq      :  in std_logic;
294
         nmi      :  in std_logic;
295
         firq     :  in std_logic;
296
         halt     :  in std_logic;
297
         hold     :  in std_logic
298 19 dilbert57
  );
299
end component;
300
 
301
 
302
----------------------------------------
303
--
304
-- Block RAM Monitor ROM
305
--
306
----------------------------------------
307 20 dilbert57
component mon_rom
308 19 dilbert57
    Port (
309 109 davidgb
       clk      : in  std_logic;
310
                 rst      : in  std_logic;
311
                 cs       : in  std_logic;
312
                 rw       : in  std_logic;
313
       addr     : in  std_logic_vector (10 downto 0);
314
       data_in  : in  std_logic_vector (7 downto 0);
315
       data_out : out std_logic_vector (7 downto 0)
316 19 dilbert57
    );
317
end component;
318
 
319
----------------------------------------
320
--
321
-- Block RAM Monitor
322
--
323
----------------------------------------
324
component ram_32k
325
    Port (
326 109 davidgb
       clk      : in  std_logic;
327
                 rst      : in  std_logic;
328
                 cs       : in  std_logic;
329 118 dilbert57
       addr     : in  std_logic_vector (14 downto 0);
330 109 davidgb
                 rw       : in  std_logic;
331
       data_in  : in  std_logic_vector (7 downto 0);
332
       data_out : out std_logic_vector (7 downto 0)
333 19 dilbert57
    );
334
end component;
335
 
336
-----------------------------------------------------------------
337
--
338
-- 6822 compatible PIA with counters
339
--
340
-----------------------------------------------------------------
341
 
342
component pia_timer
343
        port (
344
         clk       : in    std_logic;
345
    rst       : in    std_logic;
346
    cs        : in    std_logic;
347 118 dilbert57
    addr      : in    std_logic_vector(1 downto 0);
348 19 dilbert57
    rw        : in    std_logic;
349
    data_in   : in    std_logic_vector(7 downto 0);
350
         data_out  : out   std_logic_vector(7 downto 0);
351
         irqa      : out   std_logic;
352
         irqb      : out   std_logic
353
         );
354
end component;
355
 
356 20 dilbert57
 
357 19 dilbert57
-----------------------------------------------------------------
358
--
359 20 dilbert57
-- 6850 ACIA/UART
360 19 dilbert57
--
361
-----------------------------------------------------------------
362
 
363 118 dilbert57
component acia6850
364 19 dilbert57
  port (
365
     clk      : in  Std_Logic;  -- System Clock
366
     rst      : in  Std_Logic;  -- Reset input (active high)
367
     cs       : in  Std_Logic;  -- miniUART Chip Select
368
     rw       : in  Std_Logic;  -- Read / Not Write
369 109 davidgb
     addr     : in  Std_Logic;  -- Register Select
370
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
371
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
372 19 dilbert57
     irq      : out Std_Logic;  -- Interrupt
373
     RxC      : in  Std_Logic;  -- Receive Baud Clock
374
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
375
     RxD      : in  Std_Logic;  -- Receive Data
376
     TxD      : out Std_Logic;  -- Transmit Data
377
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
378
     CTS_n    : in  Std_Logic;  -- Clear To Send
379
     RTS_n    : out Std_Logic );  -- Request To send
380
end component;
381
 
382 20 dilbert57
-----------------------------------------------------------------
383
--
384
-- ACIA Clock divider
385
--
386
-----------------------------------------------------------------
387 19 dilbert57
 
388 20 dilbert57
component ACIA_Clock
389
  generic (
390 109 davidgb
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
391
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
392 20 dilbert57
  );
393
  port (
394
     clk      : in  Std_Logic;  -- System Clock Input
395
          ACIA_clk : out Std_logic   -- ACIA Clock output
396
  );
397
end component;
398
 
399
----------------------------------------
400
--
401
-- Timer module
402
--
403
----------------------------------------
404
 
405
component timer
406
  port (
407 118 dilbert57
     clk       : in  std_logic;
408
     rst       : in  std_logic;
409
     cs        : in  std_logic;
410
     addr      : in  std_logic;
411
     rw        : in  std_logic;
412
     data_in   : in  std_logic_vector(7 downto 0);
413 20 dilbert57
          data_out  : out std_logic_vector(7 downto 0);
414 59 davidgb
          irq       : out std_logic
415 20 dilbert57
          );
416
end component;
417
 
418
------------------------------------------------------------
419
--
420
-- Bus Trap logic
421
--
422
------------------------------------------------------------
423
 
424
component trap
425
        port (
426
         clk        : in  std_logic;
427
    rst        : in  std_logic;
428
    cs         : in  std_logic;
429 118 dilbert57
    vma        : in  std_logic;
430 20 dilbert57
    rw         : in  std_logic;
431
    addr       : in  std_logic_vector(15 downto 0);
432
    data_in    : in  std_logic_vector(7 downto 0);
433
         data_out   : out std_logic_vector(7 downto 0);
434
         irq        : out std_logic
435
  );
436
end component;
437
 
438
----------------------------------------
439
--
440
-- PS/2 Keyboard
441
--
442
----------------------------------------
443
 
444
component keyboard
445
  generic(
446 118 dilbert57
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
447 20 dilbert57
  );
448
  port(
449 118 dilbert57
    clk             : in    std_logic;
450
    rst             : in    std_logic;
451
    cs              : in    std_logic;
452
    addr            : in    std_logic;
453
    rw              : in    std_logic;
454
    data_in         : in    std_logic_vector(7 downto 0);
455
    data_out        : out   std_logic_vector(7 downto 0);
456
    irq             : out   std_logic;
457
    kbd_clk         : inout std_logic;
458
    kbd_data        : inout std_logic
459 20 dilbert57
  );
460
end component;
461
 
462
----------------------------------------
463
--
464
-- Video Display Unit.
465
--
466
----------------------------------------
467
component vdu8
468
      generic(
469 109 davidgb
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- 25MHz
470
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
471
             VGA_HOR_CHAR_PIXELS    : integer :=  8; -- PIXELS 0.32us
472
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
473
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
474
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
475
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
476
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
477
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
478
             VGA_VER_SYNC           : integer :=  2; -- LINES 0.064ms
479
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
480 20 dilbert57
      );
481
      port(
482
                -- control register interface
483
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
484
      vdu_rst      : in  std_logic;
485
                vdu_cs       : in  std_logic;
486
                vdu_rw       : in  std_logic;
487
                vdu_addr     : in  std_logic_vector(2 downto 0);
488
      vdu_data_in  : in  std_logic_vector(7 downto 0);
489
      vdu_data_out : out std_logic_vector(7 downto 0);
490
 
491
      -- vga port connections
492
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
493
      vga_red_o    : out std_logic;
494
      vga_green_o  : out std_logic;
495
      vga_blue_o   : out std_logic;
496
      vga_hsync_o  : out std_logic;
497
      vga_vsync_o  : out std_logic
498
   );
499
end component;
500
 
501 118 dilbert57
begin
502
 
503
-----------------------------------------------------------------------------
504
-- Instantiation of internal components
505
-----------------------------------------------------------------------------
506
 
507
----------------------------------------
508
--
509
-- Clock generator
510
--
511
----------------------------------------
512
 
513
my_clock_div: clock_div port map (
514
    clk_in   => CLK_50MHZ,  -- Clock input
515
    sys_clk  => sys_clk,  -- System Clock Out        (1/1)
516
    vga_clk  => vga_clk,  -- CPU/VGA Pixel Clock Out (1/2)
517
    cpu_clk  => open      --                         (1/4)
518
  );
519
 
520
-----------------------------------------
521
--
522
-- LED Flasher
523
--
524
-----------------------------------------
525 20 dilbert57
 
526 118 dilbert57
my_LED_flasher : flasher port map (
527
    clk      => cpu_clk,
528
    rst      => cpu_rst,
529
    LED      => LED(0)
530 19 dilbert57
  );
531 118 dilbert57
 
532
----------------------------------------
533
--
534
-- 6809 compatible CPU
535
--
536
----------------------------------------
537 19 dilbert57
 
538
my_cpu : cpu09  port map (
539
         clk         => cpu_clk,
540 118 dilbert57
    rst       => cpu_rst,
541
    vma       => cpu_vma,
542
    addr      => cpu_addr(15 downto 0),
543 19 dilbert57
    rw       => cpu_rw,
544 109 davidgb
         data_out  => cpu_data_out,
545 19 dilbert57
    data_in   => cpu_data_in,
546
         irq       => cpu_irq,
547
         nmi       => cpu_nmi,
548 109 davidgb
         firq      => cpu_firq,
549
         halt      => cpu_halt,
550
         hold      => cpu_hold
551 19 dilbert57
  );
552
 
553 20 dilbert57
my_rom : mon_rom port map (
554 109 davidgb
       clk      => cpu_clk,
555 118 dilbert57
                 rst      => cpu_rst,
556 109 davidgb
                 cs       => rom_cs,
557 118 dilbert57
       addr     => cpu_addr(10 downto 0),
558 109 davidgb
                 rw       => '1',
559
       data_in  => cpu_data_out,
560
       data_out => rom_data_out
561 19 dilbert57
    );
562
 
563
my_ram : ram_32k port map (
564 109 davidgb
       clk      => cpu_clk,
565 118 dilbert57
                 rst      => cpu_rst,
566 109 davidgb
                 cs       => ram_cs,
567 118 dilbert57
       addr     => cpu_addr(14 downto 0),
568 109 davidgb
                 rw       => cpu_rw,
569
       data_in  => cpu_data_out,
570
       data_out => ram_data_out
571 19 dilbert57
    );
572
 
573
my_pia  : pia_timer port map (
574
         clk         => cpu_clk,
575 118 dilbert57
         rst       => cpu_rst,
576 19 dilbert57
    cs        => pia_cs,
577 118 dilbert57
    addr      => cpu_addr(1 downto 0),
578 19 dilbert57
         rw        => cpu_rw,
579
         data_in   => cpu_data_out,
580
         data_out  => pia_data_out,
581
    irqa      => pia_irq_a,
582
    irqb      => pia_irq_b
583
         );
584
 
585 20 dilbert57
----------------------------------------
586
--
587
-- ACIA/UART Serial interface
588
--
589
----------------------------------------
590 118 dilbert57
my_ACIA  : acia6850 port map (
591 19 dilbert57
         clk         => cpu_clk,
592 118 dilbert57
         rst       => cpu_rst,
593 19 dilbert57
    cs        => uart_cs,
594 118 dilbert57
    addr      => cpu_addr(0),
595 19 dilbert57
         rw        => cpu_rw,
596 109 davidgb
         data_in   => cpu_data_out,
597
         data_out  => uart_data_out,
598 19 dilbert57
    irq       => uart_irq,
599 20 dilbert57
         RxC       => uart_clk,
600
         TxC       => uart_clk,
601 118 dilbert57
         RxD       => RS232_DCE_RXD,
602
         TxD       => RS232_DCE_TXD,
603
         DCD_n     => '0',
604
         CTS_n     => '0',
605
         RTS_n     => open
606 19 dilbert57
         );
607
 
608 20 dilbert57
----------------------------------------
609
--
610
-- ACIA Clock
611
--
612
----------------------------------------
613
my_ACIA_Clock : ACIA_Clock
614
  generic map(
615 109 davidgb
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
616
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
617 20 dilbert57
  )
618
  port map(
619 118 dilbert57
    clk        => sys_clk,
620 20 dilbert57
    acia_clk   => uart_clk
621
  );
622 19 dilbert57
 
623 20 dilbert57
 
624
 
625
----------------------------------------
626
--
627
-- PS/2 Keyboard Interface
628
--
629
----------------------------------------
630
my_keyboard : keyboard
631
   generic map (
632 118 dilbert57
     KBD_CLK_FREQ => CPU_CLK_FREQ
633 20 dilbert57
        )
634
   port map(
635 118 dilbert57
          clk          => cpu_clk,
636
          rst          => cpu_rst,
637
          cs           => kbd_cs,
638
          addr         => cpu_addr(0),
639
          rw           => cpu_rw,
640
          data_in      => cpu_data_out(7 downto 0),
641
          data_out     => kbd_data_out(7 downto 0),
642
          irq          => kbd_irq,
643
          kbd_clk      => PS2_CLK,
644
          kbd_data     => PS2_DATA
645 20 dilbert57
        );
646
 
647
----------------------------------------
648
--
649
-- Video Display Unit instantiation
650
--
651
----------------------------------------
652
my_vdu : vdu8
653
  generic map(
654 109 davidgb
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
655 20 dilbert57
           VGA_HOR_CHARS          => 80, -- CHARACTERS
656 109 davidgb
           VGA_HOR_CHAR_PIXELS    =>  8,  -- PIXELS
657
           VGA_HOR_FRONT_PORCH    => 16, -- PIXELS
658
           VGA_HOR_SYNC           => 96, -- PIXELS
659
           VGA_HOR_BACK_PORCH     => 48, -- PIXELS
660 20 dilbert57
           VGA_VER_CHARS          => 25, -- CHARACTERS
661 109 davidgb
           VGA_VER_CHAR_LINES     => 16, -- LINES
662
           VGA_VER_FRONT_PORCH    => 10, -- LINES
663
           VGA_VER_SYNC           =>  2, -- LINES
664 118 dilbert57
           VGA_VER_BACK_PORCH     => 34  -- LINES
665 20 dilbert57
  )
666
  port map(
667
 
668
                -- Control Registers
669
                vdu_clk       => cpu_clk,                                        -- 25 MHz System Clock in
670 118 dilbert57
      vdu_rst       => cpu_rst,
671 20 dilbert57
                vdu_cs        => vdu_cs,
672 118 dilbert57
                vdu_addr      => cpu_addr(2 downto 0),
673 20 dilbert57
                vdu_rw        => cpu_rw,
674
                vdu_data_in   => cpu_data_out,
675
                vdu_data_out  => vdu_data_out,
676
 
677
      -- vga port connections
678 109 davidgb
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
679 20 dilbert57
      vga_red_o     => vga_red,
680
      vga_green_o   => vga_green,
681
      vga_blue_o    => vga_blue,
682
      vga_hsync_o   => vga_hsync,
683
      vga_vsync_o   => vga_vsync
684
   );
685
 
686
 
687
----------------------------------------
688
--
689
-- Timer Module
690
--
691
----------------------------------------
692
my_timer  : timer port map (
693
    clk       => cpu_clk,
694 118 dilbert57
         rst       => cpu_rst,
695 20 dilbert57
    cs        => timer_cs,
696
         rw        => cpu_rw,
697
    addr      => cpu_addr(0),
698
         data_in   => cpu_data_out,
699
         data_out  => timer_data_out,
700 59 davidgb
    irq       => timer_irq
701 20 dilbert57
    );
702
 
703
----------------------------------------
704
--
705
-- Bus Trap Interrupt logic
706
--
707
----------------------------------------
708
my_trap : trap port map (
709
         clk        => cpu_clk,
710 118 dilbert57
    rst        => cpu_rst,
711 20 dilbert57
    cs         => trap_cs,
712
    rw         => cpu_rw,
713
         vma        => cpu_vma,
714
    addr       => cpu_addr,
715
    data_in    => cpu_data_out,
716
         data_out   => trap_data_out,
717
         irq        => trap_irq
718
    );
719 19 dilbert57
 
720
----------------------------------------------------------------------
721
--
722
-- Process to decode memory map
723
--
724
----------------------------------------------------------------------
725
 
726 118 dilbert57
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
727 20 dilbert57
                                              rom_data_out,
728 19 dilbert57
                                                        ram_data_out,
729 20 dilbert57
                                                   timer_data_out,
730
                                                        trap_data_out,
731
                                                        pia_data_out,
732 19 dilbert57
                                                   uart_data_out,
733 118 dilbert57
                                                        kbd_data_out,
734 20 dilbert57
                                                        vdu_data_out )
735 19 dilbert57
begin
736 118 dilbert57
 
737
        rom_cs   <= '0';
738
        ram_cs   <= '0';
739
        uart_cs  <= '0';
740
        timer_cs <= '0';
741
        trap_cs  <= '0';
742
        pia_cs   <= '0';
743
        kbd_cs   <= '0';
744
        vdu_cs   <= '0';
745 20 dilbert57
 
746 118 dilbert57
      case cpu_addr(15 downto 12) is
747 19 dilbert57
           --
748 20 dilbert57
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
749 19 dilbert57
                --
750 20 dilbert57
                when "1111" => -- $F000 - $FFFF
751 19 dilbert57
                   cpu_data_in <= rom_data_out;
752 20 dilbert57
                        rom_cs      <= cpu_vma;              -- read ROM
753
 
754 19 dilbert57
      --
755 20 dilbert57
                -- IO Devices $E000 - $EFFF
756 19 dilbert57
                --
757 20 dilbert57
                when "1110" => -- $E000 - $E7FF
758
                   case cpu_addr(7 downto 4) is
759 19 dilbert57
                        --
760 20 dilbert57
                        -- UART / ACIA $E000
761 19 dilbert57
                        --
762 20 dilbert57
                        when "0000" => -- $E000
763
                     cpu_data_in <= uart_data_out;
764
                          uart_cs     <= cpu_vma;
765
 
766
                        --
767
                        -- WD1771 FDC sites at $E010-$E01F
768
                        --
769
                        when "0001" => -- $E010
770
           cpu_data_in <= (others => '0');
771
 
772
         --
773
         -- Keyboard port $E020 - $E02F
774 19 dilbert57
                        --
775 20 dilbert57
                        when "0010" => -- $E020
776 118 dilbert57
           cpu_data_in <= kbd_data_out;
777
                          kbd_cs <= cpu_vma;
778 20 dilbert57
 
779
         --
780
         -- VDU port $E030 - $E03F
781 19 dilbert57
                        --
782 20 dilbert57
                        when "0011" => -- $E030
783
           cpu_data_in <= vdu_data_out;
784
                          vdu_cs      <= cpu_vma;
785 19 dilbert57
 
786 20 dilbert57
         --
787
                        -- Compact Flash $E040 - $E04F
788
                        --
789
                        when "0100" => -- $E040
790
           cpu_data_in <= (others => '0');
791
 
792
         --
793
         -- Timer $E050 - $E05F
794
                        --
795
                        when "0101" => -- $E050
796
           cpu_data_in <= timer_data_out;
797
           timer_cs    <= cpu_vma;
798
 
799
         --
800
         -- Bus Trap Logic $E060 - $E06F
801
                        --
802
                        when "0110" => -- $E060
803
           cpu_data_in <= trap_data_out;
804
                          trap_cs     <= cpu_vma;
805
 
806
         --
807 118 dilbert57
         -- PIA Timer $E070 - $E07F
808 20 dilbert57
                        --
809
                        when "0111" => -- $E070
810
           cpu_data_in <= pia_data_out;
811
                          pia_cs      <= cpu_vma;
812
 
813
                        when others => -- $E080 to $E7FF
814
           cpu_data_in <= (others => '0');
815 19 dilbert57
                   end case;
816 20 dilbert57
 
817 19 dilbert57
                --
818 20 dilbert57
                -- $8000 to $DFFF = null
819
                --
820
      when "1101" | "1100" | "1011" | "1010" |
821
                     "1001" | "1000" =>
822
                  cpu_data_in <= (others => '0');
823 118 dilbert57
 
824 20 dilbert57
                --
825 19 dilbert57
                -- Everything else is RAM
826
                --
827
                when others =>
828
                  cpu_data_in <= ram_data_out;
829
                  ram_cs      <= cpu_vma;
830 20 dilbert57
                end case;
831 19 dilbert57
end process;
832
 
833
--
834 118 dilbert57
-- Assign CPU clock, reset, interrupt, halt & hold signals
835
-- as well as LED signals
836 19 dilbert57
--
837 118 dilbert57
assign_signals : process( vga_clk, BTN_SOUTH,
838
                      pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, kbd_irq
839 19 dilbert57
                                                         )
840 118 dilbert57
begin
841
    cpu_clk  <= vga_clk;
842
         cpu_rst  <= BTN_SOUTH; -- CPU reset is active high
843
    cpu_irq  <= uart_irq or kbd_irq;
844
         cpu_nmi  <= pia_irq_a or trap_irq;
845
         cpu_firq <= pia_irq_b or timer_irq;
846
         cpu_halt <= '0';
847
    cpu_hold <= '0';
848 19 dilbert57
 
849 118 dilbert57
    -- LED outputs
850
    LED(7 downto 1) <= (others=>'1');
851
 
852 19 dilbert57
end process;
853
 
854
 
855
end my_computer; --===================== End of architecture =======================--
856
 

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