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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S500E/] [System09_Digilent_3S500E.vhd] - Blame information for rev 20

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1 20 dilbert57 
-- $Id: System09_Digilent_3S500E.vhd,v 1.2 2008-01-08 01:59:09 dilbert57 Exp $
2 19 dilbert57 
--===========================================================================----
3 
--
4 
--  S Y N T H E Z I A B L E    System09 - SOC.
5 
--
6 
--  This core adheres to the GNU public license
7 
--
8 
-- File name      : System09.vhd
9 
--
10 
-- Purpose        : Top level file for 6809 compatible system on a chip
11 
--                  Designed with Xilinx XC3S500E Spartan 3E FPGA.
12 
--                  Implemented With Digilent Xilinx Starter FPGA board,
13 
--
14 
-- Dependencies   : ieee.Std_Logic_1164
15 
--                  ieee.std_logic_unsigned
16 
--                  ieee.std_logic_arith
17 
--                  ieee.numeric_std
18 
--
19 
-- Uses           : mon_rom  (kbug_rom2k.vhd)       Monitor ROM
20 
--                  cpu09    (cpu09.vhd)      CPU core
21 
--                  miniuart (minitUART3.vhd) ACIA / MiniUART
22 
--                           (rxunit3.vhd)
23 
--                           (tx_unit3.vhd)
24 
--
25 
-- Author         : John E. Kent
26 
--                  dilbert57@opencores.org
27 
--
28 
--===========================================================================----
29 
--
30 
-- Revision History:
31 
--===========================================================================--
32 
-- Version 0.1 - 20 March 2003
33 
-- Version 0.2 - 30 March 2003
34 
-- Version 0.3 - 29 April 2003
35 
-- Version 0.4 - 29 June 2003
36 
--
37 
-- Version 0.5 - 19 July 2003
38 
-- prints out "Hello World"
39 
--
40 
-- Version 0.6 - 5 September 2003
41 
-- Runs SBUG
42 
--
43 
-- Version 1.0- 6 Sep 2003 - John Kent
44 
-- Inverted CLK_50MHZ
45 
-- Initial release to Open Cores
46 
--
47 
-- Version 1.1 - 17 Jan 2004 - John Kent
48 
-- Updated miniUart.
49 
--
50 
-- Version 1.2 - 25 Jan 2004 - John Kent
51 
-- removed signals "test_alu" and "test_cc"
52 
-- Trap hardware re-instated.
53 
--
54 
-- Version 1.3 - 11 Feb 2004 - John Kent
55 
-- Designed forked off to produce System09_VDU
56 
-- Added VDU component
57 
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
58 
-- UART Runs at 57.6 Kbps
59 
--
60 
-- Version 2.0 - 2 September 2004 - John Kent
61 
-- ported to Digilent Xilinx Spartan3 starter board
62 
--      removed Compaact Flash and Trap Logic.
63 
-- Replaced SBUG with KBug9s
64 
--
65 
-- Version 3.0 - 22 April 2006 - John Kent
66 
-- Port to Digilent Spartan 3E Starter board
67 
-- Removed keyboard, vdu, timer, and trap logic
68 
-- added PIA with counters attached.
69 
-- Uses 32Kbytes of internal Block RAM
70 20 dilbert57 
--
71 
-- Version 4.0 - 8th April 2007 - John kent
72 
-- Added VDU and PS/2 keyboard
73 
-- Updated miniUART to ACIA6850
74 
-- Reduce monitor ROM to 2KB
75 
-- Re-assigned I/O port assignments so it is possible to run KBUG9
76 
-- $E000 - ACIA
77 
-- $E020 - Keyboard
78 
-- $E030 - VDU
79 
-- $E040 - Compact Flash (not implemented)
80 
-- $E050 - Timer
81 
-- $E060 - Bus trap
82 
-- $E070 - Parallel I/O
83 
--
84 19 dilbert57 
--===========================================================================--
85 
library ieee;
86 
   use ieee.std_logic_1164.all;
87 
   use IEEE.STD_LOGIC_ARITH.ALL;
88 
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
89 
   use ieee.numeric_std.all;
90 
 
91 
entity My_System09 is
92 
  port(
93 
    CLK_50MHZ     : in  Std_Logic;  -- System Clock input
94 
    BTN_SOUTH     : in  Std_Logic;
95 
 
96 20 dilbert57 
         -- PS/2 Keyboard
97 
         PS2_CLK      : inout Std_logic;
98 
         PS2_DATA     : inout Std_Logic;
99 
 
100 
         -- CRTC output signals
101 
         VGA_VSYNC     : out Std_Logic;
102 
    VGA_HSYNC     : out Std_Logic;
103 
    VGA_BLUE      : out std_logic;
104 
    VGA_GREEN     : out std_logic;
105 
    VGA_RED       : out std_logic;
106 
 
107 19 dilbert57 
         -- Uart Interface
108 
         RS232_DCE_RXD : in  std_logic;
109 
    RS232_DCE_TXD : out std_logic;
110 
 
111 
         -- LEDS & Switches
112 
         LED           : out std_logic_vector(7 downto 0)
113 
         );
114 
end My_System09;
115 
 
116 
-------------------------------------------------------------------------------
117 
-- Architecture for System09
118 
-------------------------------------------------------------------------------
119 
architecture my_computer of My_System09 is
120 
  -----------------------------------------------------------------------------
121 20 dilbert57 
  -- constants
122 
  -----------------------------------------------------------------------------
123 
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
124 
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
125 
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
126 
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
127 
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
128 
 
129 
  -----------------------------------------------------------------------------
130 19 dilbert57 
  -- Signals
131 
  -----------------------------------------------------------------------------
132 
  -- BOOT ROM
133 20 dilbert57 
  signal rom_cs         : Std_logic;
134 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
135 19 dilbert57 
 
136 
  -- UART Interface signals
137 20 dilbert57 
  signal uart_data_out  : Std_Logic_Vector(7 downto 0);
138 
  signal uart_cs        : Std_Logic;
139 
  signal uart_irq       : Std_Logic;
140 
  signal uart_clk       : Std_Logic;
141 
  signal rxbit          : Std_Logic;
142 
  signal txbit          : Std_Logic;
143 
  signal DCD_n          : Std_Logic;
144 
  signal RTS_n          : Std_Logic;
145 
  signal CTS_n          : Std_Logic;
146 19 dilbert57 
 
147 20 dilbert57 
  -- timer
148 
  signal timer_data_out : std_logic_vector(7 downto 0);
149 
  signal timer_cs       : std_logic;
150 
  signal timer_irq      : std_logic;
151 
 
152 
  -- trap
153 
  signal trap_cs        : std_logic;
154 
  signal trap_data_out  : std_logic_vector(7 downto 0);
155 
  signal trap_irq       : std_logic;
156 
 
157 19 dilbert57 
  -- PIA Interface signals
158 20 dilbert57 
  signal pia_data_out   : Std_Logic_Vector(7 downto 0);
159 
  signal pia_cs         : Std_Logic;
160 
  signal pia_irq_a      : Std_Logic;
161 
  signal pia_irq_b      : Std_Logic;
162 19 dilbert57 
 
163 20 dilbert57 
  -- keyboard port
164 
  signal keyboard_data_out : std_logic_vector(7 downto 0);
165 
  signal keyboard_cs       : std_logic;
166 
  signal keyboard_irq      : std_logic;
167 
 
168 
  -- Video Display Unit
169 
  signal pix_clk      : std_logic;
170 
  signal vdu_cs       : std_logic;
171 
  signal vdu_data_out : std_logic_vector(7 downto 0);
172 
 
173 19 dilbert57 
  -- RAM
174 
  signal ram_cs       : std_logic; -- memory chip select
175 
  signal ram_data_out : std_logic_vector(7 downto 0);
176 
 
177 
  -- CPU Interface signals
178 
  signal cpu_reset    : Std_Logic;
179 
  signal cpu_clk      : Std_Logic;
180 
  signal cpu_rw       : std_logic;
181 
  signal cpu_vma      : std_logic;
182 
  signal cpu_halt     : std_logic;
183 
  signal cpu_hold     : std_logic;
184 
  signal cpu_firq     : std_logic;
185 
  signal cpu_irq      : std_logic;
186 
  signal cpu_nmi      : std_logic;
187 
  signal cpu_addr     : std_logic_vector(15 downto 0);
188 
  signal cpu_data_in  : std_logic_vector(7 downto 0);
189 
  signal cpu_data_out : std_logic_vector(7 downto 0);
190 
 
191 20 dilbert57 
  -- CLK_50MHZ clock divide by 2
192 
  signal clock_div    : std_logic_vector(1 downto 0);
193 
  signal SysClk       : std_logic;
194 
  signal Reset_n      : std_logic;
195 19 dilbert57 
  signal CountL       : std_logic_vector(23 downto 0);
196 
 
197 
-----------------------------------------------------------------
198 
--
199 
-- CPU09 CPU core
200 
--
201 
-----------------------------------------------------------------
202 
 
203 
component cpu09
204 
  port (
205 
         clk:        in std_logic;
206 
    rst:      in        std_logic;
207 
    rw:      out        std_logic;              -- Asynchronous memory interface
208 
    vma:             out        std_logic;
209 
    address:  out       std_logic_vector(15 downto 0);
210 
    data_in:  in        std_logic_vector(7 downto 0);
211 
         data_out: out std_logic_vector(7 downto 0);
212 
         halt:     in  std_logic;
213 
         hold:     in  std_logic;
214 
         irq:      in  std_logic;
215 
         nmi:      in  std_logic;
216 
         firq:     in  std_logic
217 
  );
218 
end component;
219 
 
220 
 
221 
----------------------------------------
222 
--
223 
-- Block RAM Monitor ROM
224 
--
225 
----------------------------------------
226 20 dilbert57 
component mon_rom
227 19 dilbert57 
    Port (
228 
       clk   : in  std_logic;
229 
                 rst   : in  std_logic;
230 
                 cs    : in  std_logic;
231 
                 rw    : in  std_logic;
232 20 dilbert57 
       addr  : in  std_logic_vector (10 downto 0);
233 19 dilbert57 
       rdata : out std_logic_vector (7 downto 0);
234 
       wdata : in  std_logic_vector (7 downto 0)
235 
    );
236 
end component;
237 
 
238 
----------------------------------------
239 
--
240 
-- Block RAM Monitor
241 
--
242 
----------------------------------------
243 
component ram_32k
244 
    Port (
245 
       clk   : in  std_logic;
246 
                 rst   : in  std_logic;
247 
                 cs    : in  std_logic;
248 
                 rw    : in  std_logic;
249 
       addr  : in  std_logic_vector (14 downto 0);
250 
       rdata : out std_logic_vector (7 downto 0);
251 
       wdata : in  std_logic_vector (7 downto 0)
252 
    );
253 
end component;
254 
 
255 
-----------------------------------------------------------------
256 
--
257 
-- 6822 compatible PIA with counters
258 
--
259 
-----------------------------------------------------------------
260 
 
261 
component pia_timer
262 
        port (
263 
         clk       : in    std_logic;
264 
    rst       : in    std_logic;
265 
    cs        : in    std_logic;
266 
    rw        : in    std_logic;
267 
    addr      : in    std_logic_vector(1 downto 0);
268 
    data_in   : in    std_logic_vector(7 downto 0);
269 
         data_out  : out   std_logic_vector(7 downto 0);
270 
         irqa      : out   std_logic;
271 
         irqb      : out   std_logic
272 
         );
273 
end component;
274 
 
275 20 dilbert57 
 
276 19 dilbert57 
-----------------------------------------------------------------
277 
--
278 20 dilbert57 
-- 6850 ACIA/UART
279 19 dilbert57 
--
280 
-----------------------------------------------------------------
281 
 
282 20 dilbert57 
component ACIA_6850
283 19 dilbert57 
  port (
284 
     clk      : in  Std_Logic;  -- System Clock
285 
     rst      : in  Std_Logic;  -- Reset input (active high)
286 
     cs       : in  Std_Logic;  -- miniUART Chip Select
287 
     rw       : in  Std_Logic;  -- Read / Not Write
288 
     irq      : out Std_Logic;  -- Interrupt
289 
     Addr     : in  Std_Logic;  -- Register Select
290 
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In
291 
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
292 
     RxC      : in  Std_Logic;  -- Receive Baud Clock
293 
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
294 
     RxD      : in  Std_Logic;  -- Receive Data
295 
     TxD      : out Std_Logic;  -- Transmit Data
296 
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
297 
     CTS_n    : in  Std_Logic;  -- Clear To Send
298 
     RTS_n    : out Std_Logic );  -- Request To send
299 
end component;
300 
 
301 20 dilbert57 
-----------------------------------------------------------------
302 
--
303 
-- ACIA Clock divider
304 
--
305 
-----------------------------------------------------------------
306 19 dilbert57 
 
307 20 dilbert57 
component ACIA_Clock
308 
  generic (
309 
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
310 
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
311 
  );
312 
  port (
313 
     clk      : in  Std_Logic;  -- System Clock Input
314 
          ACIA_clk : out Std_logic   -- ACIA Clock output
315 
  );
316 
end component;
317 
 
318 
----------------------------------------
319 
--
320 
-- Timer module
321 
--
322 
----------------------------------------
323 
 
324 
component timer
325 
  port (
326 
     clk       : in std_logic;
327 
     rst       : in std_logic;
328 
     cs        : in std_logic;
329 
     rw        : in std_logic;
330 
     addr      : in std_logic;
331 
     data_in   : in std_logic_vector(7 downto 0);
332 
          data_out  : out std_logic_vector(7 downto 0);
333 
          irq       : out std_logic;
334 
     timer_in  : in std_logic;
335 
          timer_out : out std_logic
336 
          );
337 
end component;
338 
 
339 
------------------------------------------------------------
340 
--
341 
-- Bus Trap logic
342 
--
343 
------------------------------------------------------------
344 
 
345 
component trap
346 
        port (
347 
         clk        : in  std_logic;
348 
    rst        : in  std_logic;
349 
    cs         : in  std_logic;
350 
    rw         : in  std_logic;
351 
    vma        : in  std_logic;
352 
    addr       : in  std_logic_vector(15 downto 0);
353 
    data_in    : in  std_logic_vector(7 downto 0);
354 
         data_out   : out std_logic_vector(7 downto 0);
355 
         irq        : out std_logic
356 
  );
357 
end component;
358 
 
359 
----------------------------------------
360 
--
361 
-- PS/2 Keyboard
362 
--
363 
----------------------------------------
364 
 
365 
component keyboard
366 
  generic(
367 
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
368 
  );
369 
  port(
370 
  clk             : in    std_logic;
371 
  rst             : in    std_logic;
372 
  cs              : in    std_logic;
373 
  rw              : in    std_logic;
374 
  addr            : in    std_logic;
375 
  data_in         : in    std_logic_vector(7 downto 0);
376 
  data_out        : out   std_logic_vector(7 downto 0);
377 
  irq             : out   std_logic;
378 
  kbd_clk         : inout std_logic;
379 
  kbd_data        : inout std_logic
380 
  );
381 
end component;
382 
 
383 
----------------------------------------
384 
--
385 
-- Video Display Unit.
386 
--
387 
----------------------------------------
388 
component vdu8
389 
      generic(
390 
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
391 
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
392 
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
393 
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
394 
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
395 
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
396 
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
397 
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
398 
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
399 
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
400 
             VGA_VER_SYNC           : integer := 1;  -- LINES
401 
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
402 
      );
403 
      port(
404 
                -- control register interface
405 
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
406 
      vdu_rst      : in  std_logic;
407 
                vdu_cs       : in  std_logic;
408 
                vdu_rw       : in  std_logic;
409 
                vdu_addr     : in  std_logic_vector(2 downto 0);
410 
      vdu_data_in  : in  std_logic_vector(7 downto 0);
411 
      vdu_data_out : out std_logic_vector(7 downto 0);
412 
 
413 
      -- vga port connections
414 
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
415 
      vga_red_o    : out std_logic;
416 
      vga_green_o  : out std_logic;
417 
      vga_blue_o   : out std_logic;
418 
      vga_hsync_o  : out std_logic;
419 
      vga_vsync_o  : out std_logic
420 
   );
421 
end component;
422 
 
423 
 
424 19 dilbert57 
component BUFG
425 
port (
426 
     i: in std_logic;
427 
          o: out std_logic
428 
  );
429 
end component;
430 
 
431 
begin
432 
  -----------------------------------------------------------------------------
433 
  -- Instantiation of internal components
434 
  -----------------------------------------------------------------------------
435 
 
436 
my_cpu : cpu09  port map (
437 
         clk         => cpu_clk,
438 
    rst       => cpu_reset,
439 
    rw       => cpu_rw,
440 
    vma       => cpu_vma,
441 
    address   => cpu_addr(15 downto 0),
442 
    data_in   => cpu_data_in,
443 
         data_out  => cpu_data_out,
444 
         halt      => cpu_halt,
445 
         hold      => cpu_hold,
446 
         irq       => cpu_irq,
447 
         nmi       => cpu_nmi,
448 
         firq      => cpu_firq
449 
  );
450 
 
451 20 dilbert57 
my_rom : mon_rom port map (
452 19 dilbert57 
       clk   => cpu_clk,
453 
                 rst   => cpu_reset,
454 
                 cs    => rom_cs,
455 
                 rw    => '1',
456 20 dilbert57 
       addr  => cpu_addr(10 downto 0),
457 19 dilbert57 
       rdata => rom_data_out,
458 
       wdata => cpu_data_out
459 
    );
460 
 
461 
my_ram : ram_32k port map (
462 
       clk   => cpu_clk,
463 
                 rst   => cpu_reset,
464 
                 cs    => ram_cs,
465 
                 rw    => cpu_rw,
466 
       addr  => cpu_addr(14 downto 0),
467 
       rdata => ram_data_out,
468 
       wdata => cpu_data_out
469 
    );
470 
 
471 
my_pia  : pia_timer port map (
472 
         clk         => cpu_clk,
473 
         rst       => cpu_reset,
474 
    cs        => pia_cs,
475 
         rw        => cpu_rw,
476 
    addr      => cpu_addr(1 downto 0),
477 
         data_in   => cpu_data_out,
478 
         data_out  => pia_data_out,
479 
    irqa      => pia_irq_a,
480 
    irqb      => pia_irq_b
481 
         );
482 
 
483 20 dilbert57 
 
484 
----------------------------------------
485 
--
486 
-- ACIA/UART Serial interface
487 
--
488 
----------------------------------------
489 
my_ACIA  : ACIA_6850 port map (
490 19 dilbert57 
         clk         => cpu_clk,
491 
         rst       => cpu_reset,
492 
    cs        => uart_cs,
493 
         rw        => cpu_rw,
494 
    irq       => uart_irq,
495 
    Addr      => cpu_addr(0),
496 
         Datain    => cpu_data_out,
497 
         DataOut   => uart_data_out,
498 20 dilbert57 
         RxC       => uart_clk,
499 
         TxC       => uart_clk,
500 
         RxD       => rxbit,
501 
         TxD       => txbit,
502 19 dilbert57 
         DCD_n     => dcd_n,
503 
         CTS_n     => cts_n,
504 
         RTS_n     => rts_n
505 
         );
506 
 
507 20 dilbert57 
----------------------------------------
508 
--
509 
-- ACIA Clock
510 
--
511 
----------------------------------------
512 
my_ACIA_Clock : ACIA_Clock
513 
  generic map(
514 
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
515 
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
516 
  )
517 
  port map(
518 
    clk        => SysClk,
519 
    acia_clk   => uart_clk
520 
  );
521 19 dilbert57 
 
522 20 dilbert57 
 
523 
 
524 
----------------------------------------
525 
--
526 
-- PS/2 Keyboard Interface
527 
--
528 
----------------------------------------
529 
my_keyboard : keyboard
530 
   generic map (
531 
        KBD_Clock_Frequency => CPU_Clock_frequency
532 
        )
533 
   port map(
534 
        clk          => cpu_clk,
535 
        rst          => cpu_reset,
536 
        cs           => keyboard_cs,
537 
        rw           => cpu_rw,
538 
        addr         => cpu_addr(0),
539 
        data_in      => cpu_data_out(7 downto 0),
540 
        data_out     => keyboard_data_out(7 downto 0),
541 
        irq          => keyboard_irq,
542 
        kbd_clk      => PS2_CLK,
543 
        kbd_data     => PS2_DATA
544 
        );
545 
 
546 
----------------------------------------
547 
--
548 
-- Video Display Unit instantiation
549 
--
550 
----------------------------------------
551 
my_vdu : vdu8
552 
  generic map(
553 
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
554 
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
555 
           VGA_HOR_CHARS          => 80, -- CHARACTERS
556 
           VGA_VER_CHARS          => 25, -- CHARACTERS
557 
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
558 
           VGA_LINES_PER_CHAR     => 16, -- LINES
559 
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
560 
           VGA_HOR_SYNC           => 96, -- PIXELS
561 
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
562 
           VGA_VER_BACK_PORCH     => 13, -- LINES
563 
           VGA_VER_SYNC           => 1,  -- LINES
564 
           VGA_VER_FRONT_PORCH    => 36  -- LINES
565 
  )
566 
  port map(
567 
 
568 
                -- Control Registers
569 
                vdu_clk       => cpu_clk,                                        -- 25 MHz System Clock in
570 
      vdu_rst       => cpu_reset,
571 
                vdu_cs        => vdu_cs,
572 
                vdu_rw        => cpu_rw,
573 
                vdu_addr      => cpu_addr(2 downto 0),
574 
                vdu_data_in   => cpu_data_out,
575 
                vdu_data_out  => vdu_data_out,
576 
 
577 
      -- vga port connections
578 
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
579 
      vga_red_o     => vga_red,
580 
      vga_green_o   => vga_green,
581 
      vga_blue_o    => vga_blue,
582 
      vga_hsync_o   => vga_hsync,
583 
      vga_vsync_o   => vga_vsync
584 
   );
585 
 
586 
 
587 
----------------------------------------
588 
--
589 
-- Timer Module
590 
--
591 
----------------------------------------
592 
my_timer  : timer port map (
593 
    clk       => cpu_clk,
594 
         rst       => cpu_reset,
595 
    cs        => timer_cs,
596 
         rw        => cpu_rw,
597 
    addr      => cpu_addr(0),
598 
         data_in   => cpu_data_out,
599 
         data_out  => timer_data_out,
600 
    irq       => timer_irq,
601 
         timer_in  => CountL(5)
602 
--       timer_out => timer_out
603 
    );
604 
 
605 
----------------------------------------
606 
--
607 
-- Bus Trap Interrupt logic
608 
--
609 
----------------------------------------
610 
my_trap : trap port map (
611 
         clk        => cpu_clk,
612 
    rst        => cpu_reset,
613 
    cs         => trap_cs,
614 
    rw         => cpu_rw,
615 
         vma        => cpu_vma,
616 
    addr       => cpu_addr,
617 
    data_in    => cpu_data_out,
618 
         data_out   => trap_data_out,
619 
         irq        => trap_irq
620 
    );
621 
 
622 
--
623 
-- 25 MHz CPU clock
624 
--
625 
cpu_clk_buffer : BUFG port map(
626 
    i => clock_div(0),
627 19 dilbert57 
         o => cpu_clk
628 20 dilbert57 
    );
629 
 
630 
--
631 
-- 25 MHz VGA Pixel clock
632 
--
633 
vga_clk_buffer : BUFG port map(
634 
    i => clock_div(0),
635 
         o => pix_clk
636 19 dilbert57 
    );
637 
 
638 
----------------------------------------------------------------------
639 
--
640 
-- Process to decode memory map
641 
--
642 
----------------------------------------------------------------------
643 
 
644 20 dilbert57 
mem_decode: process( cpu_clk, Reset_n,
645 19 dilbert57 
                     cpu_addr, cpu_rw, cpu_vma,
646 20 dilbert57 
                                              rom_data_out,
647 19 dilbert57 
                                                        ram_data_out,
648 20 dilbert57 
                                                   timer_data_out,
649 
                                                        trap_data_out,
650 
                                                        pia_data_out,
651 19 dilbert57 
                                                   uart_data_out,
652 20 dilbert57 
                                                        keyboard_data_out,
653 
                                                        vdu_data_out )
654 
variable decode_addr : std_logic_vector(3 downto 0);
655 19 dilbert57 
begin
656 20 dilbert57 
--    decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
657 
    decode_addr := cpu_addr(15 downto 12);
658 
 
659 
      case decode_addr is
660 19 dilbert57 
           --
661 20 dilbert57 
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
662 19 dilbert57 
                --
663 20 dilbert57 
                when "1111" => -- $F000 - $FFFF
664 19 dilbert57 
                   cpu_data_in <= rom_data_out;
665 20 dilbert57 
                        rom_cs      <= cpu_vma;              -- read ROM
666 19 dilbert57 
                        ram_cs      <= '0';
667 
                        uart_cs     <= '0';
668 20 dilbert57 
                        timer_cs    <= '0';
669 
                        trap_cs     <= '0';
670 19 dilbert57 
                        pia_cs      <= '0';
671 20 dilbert57 
                        keyboard_cs <= '0';
672 
                        vdu_cs      <= '0';
673 
 
674 19 dilbert57 
      --
675 20 dilbert57 
                -- IO Devices $E000 - $EFFF
676 19 dilbert57 
                --
677 20 dilbert57 
                when "1110" => -- $E000 - $E7FF
678 19 dilbert57 
                        rom_cs    <= '0';
679 
                        ram_cs    <= '0';
680 20 dilbert57 
                   case cpu_addr(7 downto 4) is
681 19 dilbert57 
                        --
682 20 dilbert57 
                        -- UART / ACIA $E000
683 19 dilbert57 
                        --
684 20 dilbert57 
                        when "0000" => -- $E000
685 
                     cpu_data_in <= uart_data_out;
686 
                          uart_cs     <= cpu_vma;
687 
                          timer_cs    <= '0';
688 
                          trap_cs     <= '0';
689 
                          pia_cs      <= '0';
690 
                          keyboard_cs <= '0';
691 
                          vdu_cs      <= '0';
692 
 
693 
                        --
694 
                        -- WD1771 FDC sites at $E010-$E01F
695 
                        --
696 
                        when "0001" => -- $E010
697 
           cpu_data_in <= (others => '0');
698 19 dilbert57 
                          uart_cs     <= '0';
699 20 dilbert57 
                          timer_cs    <= '0';
700 
                          trap_cs     <= '0';
701 
                          pia_cs      <= '0';
702 
                          keyboard_cs <= '0';
703 
                          vdu_cs      <= '0';
704 
 
705 
         --
706 
         -- Keyboard port $E020 - $E02F
707 19 dilbert57 
                        --
708 20 dilbert57 
                        when "0010" => -- $E020
709 
           cpu_data_in <= keyboard_data_out;
710 
                          uart_cs     <= '0';
711 
           timer_cs    <= '0';
712 
                          trap_cs     <= '0';
713 
                          pia_cs      <= '0';
714 
                          keyboard_cs <= cpu_vma;
715 
                          vdu_cs      <= '0';
716 
 
717 
         --
718 
         -- VDU port $E030 - $E03F
719 19 dilbert57 
                        --
720 20 dilbert57 
                        when "0011" => -- $E030
721 
           cpu_data_in <= vdu_data_out;
722 
                          uart_cs     <= '0';
723 
           timer_cs    <= '0';
724 
                          trap_cs     <= '0';
725 
                          pia_cs      <= '0';
726 
                          keyboard_cs <= '0';
727 
                          vdu_cs      <= cpu_vma;
728 19 dilbert57 
 
729 20 dilbert57 
         --
730 
                        -- Compact Flash $E040 - $E04F
731 
                        --
732 
                        when "0100" => -- $E040
733 
           cpu_data_in <= (others => '0');
734 19 dilbert57 
                          uart_cs     <= '0';
735 20 dilbert57 
                          timer_cs    <= '0';
736 
                          trap_cs     <= '0';
737 
                          pia_cs      <= '0';
738 
                          keyboard_cs <= '0';
739 
                          vdu_cs      <= '0';
740 
 
741 
         --
742 
         -- Timer $E050 - $E05F
743 
                        --
744 
                        when "0101" => -- $E050
745 
           cpu_data_in <= timer_data_out;
746 
                          uart_cs     <= '0';
747 
           timer_cs    <= cpu_vma;
748 
                          trap_cs     <= '0';
749 
                          pia_cs      <= '0';
750 
                          keyboard_cs <= '0';
751 
                          vdu_cs      <= '0';
752 
 
753 
         --
754 
         -- Bus Trap Logic $E060 - $E06F
755 
                        --
756 
                        when "0110" => -- $E060
757 
           cpu_data_in <= trap_data_out;
758 
                          uart_cs     <= '0';
759 
           timer_cs    <= '0';
760 
                          trap_cs     <= cpu_vma;
761 
                          pia_cs      <= '0';
762 
                          keyboard_cs <= '0';
763 
                          vdu_cs      <= '0';
764 
 
765 
         --
766 
         -- I/O port $E070 - $E07F
767 
                        --
768 
                        when "0111" => -- $E070
769 
           cpu_data_in <= pia_data_out;
770 
                          uart_cs     <= '0';
771 
           timer_cs    <= '0';
772 
                          trap_cs     <= '0';
773 
                          pia_cs      <= cpu_vma;
774 
                          keyboard_cs <= '0';
775 
                          vdu_cs      <= '0';
776 
 
777 
                        when others => -- $E080 to $E7FF
778 
           cpu_data_in <= (others => '0');
779 
                          uart_cs     <= '0';
780 
                          timer_cs    <= '0';
781 
                          trap_cs     <= '0';
782 
                          pia_cs      <= '0';
783 
                          keyboard_cs <= '0';
784 
                          vdu_cs      <= '0';
785 19 dilbert57 
                   end case;
786 20 dilbert57 
 
787 19 dilbert57 
                --
788 20 dilbert57 
                -- $8000 to $DFFF = null
789 
                --
790 
      when "1101" | "1100" | "1011" | "1010" |
791 
                     "1001" | "1000" =>
792 
                  cpu_data_in <= (others => '0');
793 
                  rom_cs      <= '0';
794 
                  ram_cs      <= '0';
795 
                  uart_cs     <= '0';
796 
                  timer_cs    <= '0';
797 
                  trap_cs     <= '0';
798 
                  pia_cs      <= '0';
799 
                  keyboard_cs <= '0';
800 
                  vdu_cs      <= '0';
801 
                --
802 19 dilbert57 
                -- Everything else is RAM
803 
                --
804 
                when others =>
805 
                  cpu_data_in <= ram_data_out;
806 
                  rom_cs      <= '0';
807 
                  ram_cs      <= cpu_vma;
808 
                  uart_cs     <= '0';
809 20 dilbert57 
                  timer_cs    <= '0';
810 
                  trap_cs     <= '0';
811 
                  pia_cs      <= '0';
812 
                  keyboard_cs <= '0';
813 
                  vdu_cs      <= '0';
814 
                end case;
815 19 dilbert57 
end process;
816 
 
817 
--
818 
-- Interrupts and other bus control signals
819 
--
820 20 dilbert57 
interrupts : process( Reset_n,
821 
                      pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
822 19 dilbert57 
                                                         )
823 
begin
824 20 dilbert57 
         cpu_reset <= not Reset_n; -- CPU reset is active high
825 
    cpu_irq   <= uart_irq or keyboard_irq;
826 
         cpu_nmi   <= pia_irq_a or trap_irq;
827 
         cpu_firq  <= pia_irq_b or timer_irq;
828 19 dilbert57 
         cpu_halt  <= '0';
829 
    cpu_hold  <= '0';
830 
end process;
831 
 
832 
--
833 
--
834 20 dilbert57 
my_led_flasher: process( SysClk, Reset_n, CountL )
835 19 dilbert57 
begin
836 20 dilbert57 
    if Reset_n = '0' then
837 
                   CountL <= "000000000000000000000000";
838 
    elsif(SysClk'event and SysClk = '0') then
839 
                   CountL <= CountL + 1;
840 19 dilbert57 
    end if;
841 20 dilbert57 
         LED(7 downto 0) <= CountL(23 downto 16);
842 19 dilbert57 
end process;
843 
 
844 
--
845 20 dilbert57 
-- Clock divider
846 19 dilbert57 
--
847 20 dilbert57 
my_clock_divider: process( SysClk )
848 19 dilbert57 
begin
849 20 dilbert57 
        if SysClk'event and SysClk='0' then
850 
                clock_div <= clock_div + "01";
851 
        end if;
852 19 dilbert57 
end process;
853 
 
854 
DCD_n <= '0';
855 
CTS_n <= '0';
856 20 dilbert57 
Reset_n <= not BTN_SOUTH; -- CPU reset is active high
857 
SysClk <= CLK_50MHZ;
858 
rxbit <= RS232_DCE_RXD;
859 
RS232_DCE_TXD <= txbit;
860 19 dilbert57 
 
861 
end my_computer; --===================== End of architecture =======================--
862 
 

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