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# XSA-3S1000 Board FPGA pin assignment constraints

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# Clocks

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# clock pin for Atlys rev C board

 NET "CLKA"   LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK

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# Push button switches

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 NET "SW2_N" LOC = "N4";  # Bank = 3, Pin name = IO_L1P,                          Sch name = BTNU

 NET "SW3_N" LOC = "P3";  # Bank = 3, Pin name = IO_L2N,                          Sch name = BTND

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# Status LED

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 NET "S<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15,          Sch name = LD0

 NET "S<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P,                         Sch name = LD1

 NET "S<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF,            Sch name = LD2

 NET "S<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P,                         Sch name = LD3

 NET "S<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N,                         Sch name = LD4

 NET "S<5>" LOC = "D4";  # Bank = 0, Pin name = IO_L1P_HSWAPEN_0,        Sch name = HSWAP/LD5

 NET "S<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6

 NET "S<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2,            Sch name = M1/LD7

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# RS232 PORT

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 NET "RS232_RXD" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD

 NET "RS232_TXD" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD

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# Timing Constraints

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NET "CLKA" TNM_NET="CLKA";

TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;