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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Blame information for rev 159

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1 141 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
30
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
31
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
32
--                             (ps2_keyboard.vhd)
33
--                             (keymap_rom_slice.vhd) Key map table 
34
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
35
--                             (char_rom2k_b16.vhd)
36
--                             (ram2k_b16.vhd)
37
--                  timer      (timer.vhd)            Interrupt timer
38
--                  trap       (trap.vhd)             Bus condition trap logic
39
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
40
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
41
--                  
42
-- 
43
-- Author         : John E. Kent      
44
--                  dilbert57@opencores.org      
45
--
46
-- Memory Map     :
47
--
48
-- $0000 - User program RAM (32K Bytes)
49
-- $C000 - Flex Operating System memory (8K Bytes)
50
-- $E000 - ACIA (SWTPc)
51
-- $E010 - Reserved for FD1771 FDC (SWTPc)
52
-- $E020 - Keyboard
53
-- $E030 - VDU
54
-- $E040 - IDE / Compact Flash interface
55
-- $E050 - Timer
56
-- $E060 - Bus trap
57
-- $E070 - Reserced for Parallel I/O (B5-X300)
58
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
59
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
60
-- $F000 - Sys09Bug monitor Program (4K Bytes)
61
--
62
--===========================================================================----
63
--
64
-- Revision History:
65
--===========================================================================--
66
-- Version 0.1 - 20 March 2003
67
-- Version 0.2 - 30 March 2003
68
-- Version 0.3 - 29 April 2003
69
-- Version 0.4 - 29 June 2003
70
--
71
-- Version 0.5 - 19 July 2003
72
-- prints out "Hello World"
73
--
74
-- Version 0.6 - 5 September 2003
75
-- Runs SBUG
76
--
77
-- Version 1.0- 6 Sep 2003 - John Kent
78
-- Inverted SysClk
79
-- Initial release to Open Cores
80
--
81
-- Version 1.1 - 17 Jan 2004 - John Kent
82
-- Updated miniUart.
83
--
84
-- Version 1.2 - 25 Jan 2004 - John Kent
85
-- removed signals "test_alu" and "test_cc" 
86
-- Trap hardware re-instated.
87
--
88
-- Version 1.3 - 11 Feb 2004 - John Kent
89
-- Designed forked off to produce System09_VDU
90
-- Added VDU component
91
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
92
-- UART Runs at 57.6 Kbps
93
--
94
-- Version 2.0 - 2 September 2004 - John Kent
95
-- ported to Digilent Xilinx Spartan3 starter board
96
-- removed Compact Flash and Trap Logic.
97
-- Replaced SBUG with KBug9s
98
--
99
-- Version 3.0 - 29th August 2006 - John Kent
100
-- Adapted to XSA-3S1000 board.
101
-- Removed DAT and miniUART.
102
-- Used 32KBytes of Block RAM.
103
--
104
-- Version 3.1 - 15th January 2007 - John Kent
105
-- Modified vdu8 interface
106
-- Added a clock divider
107
--
108
-- Version 3.2 - 25th February 2007 - John Kent
109
-- reinstated ACIA_6850 and ACIA_Clock
110
-- Updated VDU8 & Keyboard with generic parameters
111
-- Defined Constants for clock speed calculations
112
--
113
-- Version 3.3 - 1st July 2007 - John Kent
114
-- Made VDU mono to save on one RAMB16
115
-- Used distributed memory for Key Map ROM to save one RAMB16
116
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
117
-- Added timer and trap logic
118
-- Added IDE Interface for Compact Flash
119
-- Replaced KBug9s and stack with Sys09Bug.
120
--
121
-- Version 4.0 - 1st February 2008 - John kent
122
-- Replaced Block RAM with SDRAM Interface
123
-- Modified Hold timing for SDRAM
124
-- Added CF and Ethernet interface 
125
-- via the 16 bit peripheral bus at $E100
126
--
127
--===========================================================================--
128
library ieee;
129
   use ieee.std_logic_1164.all;
130
   use IEEE.STD_LOGIC_ARITH.ALL;
131
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
132
   use ieee.numeric_std.all;
133
library work;
134
   use work.common.all;
135
library unisim;
136
   use unisim.vcomponents.all;
137
 
138
entity system09 is
139
  port(
140
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
141
--    CLKB         : in  Std_Logic;  -- 50MHz Clock input
142
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
143
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
144
 
145
 
146
 
147
    -- RS232 Port
148
    RS232_RXD    : in  Std_Logic;
149
    RS232_TXD    : out Std_Logic;
150
 
151 148 davidgb
 
152 141 davidgb
    -- Status 7 segment LED
153 148 davidgb
    S            : out std_logic_vector(7 downto 0)
154 141 davidgb
 
155
 
156
-- CPU Debug Interface signals
157
--    cpu_reset_o     : out Std_Logic;
158
--    cpu_clk_o       : out Std_Logic;
159
--    cpu_rw_o        : out std_logic;
160
--    cpu_vma_o       : out std_logic;
161
--    cpu_halt_o      : out std_logic;
162
--    cpu_hold_o      : out std_logic;
163
--    cpu_firq_o      : out std_logic;
164
--    cpu_irq_o       : out std_logic;
165
--    cpu_nmi_o       : out std_logic;
166
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
167
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
168
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
169
 
170 148 davidgb
  );
171 141 davidgb
end system09;
172
 
173
-------------------------------------------------------------------------------
174
-- Architecture for System09
175
-------------------------------------------------------------------------------
176
architecture rtl of system09 is
177
 
178
  -----------------------------------------------------------------------------
179
  -- constants
180
  -----------------------------------------------------------------------------
181
 
182
  -- SDRAM
183
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
184
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
185
  constant PIPE_EN              : boolean := false;  -- if true, enable pipelined read operations
186
  constant MAX_NOP              : natural := 10000;  -- number of NOPs before entering self-refresh
187
  constant MULTIPLE_ACTIVE_ROWS : boolean := false;  -- if true, allow an active row in each bank
188
  constant DATA_WIDTH           : natural := 16;     -- host & SDRAM data width
189
  constant NROWS                : natural := 8192;   -- number of rows in SDRAM array
190
  constant NCOLS                : natural := 512;    -- number of columns in SDRAM array
191
  constant HADDR_WIDTH          : natural := 24;     -- host-side address width
192
  constant SADDR_WIDTH          : natural := 13;     -- SDRAM-side address width
193
 
194
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock
195
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
196
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
197
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
198
  constant VGA_CLK_DIV          : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
199
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
200
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
201
 
202
  constant TRESET               : natural := 300;      -- min initialization interval (us)
203
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
204
 
205
  type hold_state_type is ( hold_release_state, hold_request_state );
206
 
207
  -----------------------------------------------------------------------------
208
  -- Signals
209
  -----------------------------------------------------------------------------
210
  -- BOOT ROM
211
  signal rom_cs         : Std_logic;
212
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
213
 
214
  -- Flex Memory & Monitor Stack
215
  signal flex_cs        : Std_logic;
216
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
217
 
218
  -- ACIA/UART Interface signals
219
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
220
  signal acia_cs        : Std_Logic;
221
  signal acia_irq       : Std_Logic;
222
  signal acia_clk       : Std_Logic;
223
  signal rxd            : Std_Logic;
224
  signal txd            : Std_Logic;
225
  signal DCD_n          : Std_Logic;
226
  signal RTS_n          : Std_Logic;
227
  signal CTS_n          : Std_Logic;
228
 
229
  -- keyboard port
230
  signal keyboard_data_out : std_logic_vector(7 downto 0);
231
  signal keyboard_cs       : std_logic;
232
  signal keyboard_irq      : std_logic;
233
 
234
  -- RAM
235
  signal ram_cs         : std_logic; -- memory chip select
236
  signal ram_data_out   : std_logic_vector(7 downto 0);
237
  signal ram_rd_req     : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
238
  signal ram_wr_req     : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge) 
239
  signal ram_hold       : std_logic; -- hold off slow accesses
240
  signal ram_release    : std_logic; -- Release ram hold
241
 
242
  -- CPU Interface signals
243
  signal cpu_reset      : Std_Logic;
244
  signal cpu_clk        : Std_Logic;
245
  signal cpu_rw         : std_logic;
246
  signal cpu_vma        : std_logic;
247
  signal cpu_halt       : std_logic;
248
  signal cpu_hold       : std_logic;
249
  signal cpu_firq       : std_logic;
250
  signal cpu_irq        : std_logic;
251
  signal cpu_nmi        : std_logic;
252
  signal cpu_addr       : std_logic_vector(15 downto 0);
253
  signal cpu_data_in    : std_logic_vector(7 downto 0);
254
  signal cpu_data_out   : std_logic_vector(7 downto 0);
255
 
256
  -- Dynamic Address Translation
257
  signal dat_cs       : std_logic;
258
  signal dat_addr     : std_logic_vector(7 downto 0);
259
 
260
  -- Video Display Unit
261
  signal vdu_cs         : std_logic;
262
  signal vdu_data_out   : std_logic_vector(7 downto 0);
263
  signal vga_red_o      : std_logic;
264
  signal vga_green_o    : std_logic;
265
  signal vga_blue_o     : std_logic;
266
 
267
  -- timer
268
  signal timer_data_out : std_logic_vector(7 downto 0);
269
  signal timer_cs       : std_logic;
270
  signal timer_irq      : std_logic;
271
 
272
  -- trap
273
  signal trap_cs        : std_logic;
274
  signal trap_data_out  : std_logic_vector(7 downto 0);
275
  signal trap_irq       : std_logic;
276
 
277
  -- Peripheral Bus port
278
  signal pb_data_out   : std_logic_vector(7 downto 0);
279 148 davidgb
  signal pb_cs         : std_logic;       -- peripheral bus chip select
280
  signal pb_wru        : std_logic;       -- upper byte write strobe
281
  signal pb_wrl        : std_logic;       -- lower byte write strobe
282
  signal pb_rdu        : std_logic;       -- upper byte read strobe
283
  signal pb_rdl        : std_logic;       -- lower byte read strobe
284
  signal pb_hold       : std_logic;       -- hold peripheral bus access
285
  signal pb_release    : std_logic;       -- release hold of peripheral bus
286 141 davidgb
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
287
  signal pb_hold_state : hold_state_type;
288
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
289
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
290
 
291
  -- Peripheral chip selects on Peripheral Bus
292
  signal ide_cs        : std_logic; -- IDE CF interface
293 148 davidgb
  signal ether_cs      : std_logic;     -- Ethernet interface
294
  signal slot1_cs      : std_logic;     -- Expansion slot 1
295
  signal slot2_cs      : std_logic;     -- Expansion slot 2
296 141 davidgb
 
297
  signal rst_i         : std_logic;     -- internal reset signal
298
  signal clk_i         : std_logic;     -- internal master clock signal
299
  signal lock          : std_logic;     -- SDRAM clock DLL lock indicator
300
 
301
  -- signals that go through the SDRAM host-side interface
302
  signal opBegun       : std_logic;        -- SDRAM operation started indicator
303
  signal earlyBegun    : std_logic;        -- SDRAM operation started indicator
304
  signal ramDone       : std_logic;        -- SDRAM operation complete indicator
305
  signal rdDone        : std_logic;        -- SDRAM read operation complete indicator
306
  signal wrDone        : std_logic;        -- SDRAM write operation complete indicator
307
  signal hAddr         : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
308
  signal hDIn          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
309
  signal hDOut         : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
310
  signal hRd           : std_logic;        -- host-side read control signal
311
  signal hWr           : std_logic;        -- host-side write control signal
312
  signal hUds          : std_logic;        -- host-side upper data strobe
313
  signal hLds          : std_logic;        -- host-side lower data strobe
314
  signal rdPending     : std_logic;        -- read operation pending in SDRAM pipeline
315
  type ram_type is (ram_state_0,
316
                    ram_state_rd1, ram_state_rd2,
317
                    ram_state_wr1,
318 148 davidgb
                                                  ram_state_3 );
319 141 davidgb
  signal ram_state     : ram_type;
320
 
321 148 davidgb
         signal flash_ce_n   :  std_logic;
322
    signal rs232_cts    :   Std_Logic;
323
    signal rs232_rts    :  Std_Logic;
324
         signal ether_cs_n : std_logic;
325
         signal ether_aen : std_logic;
326
         signal ether_bhe_n : std_logic;
327
         signal slot1_cs_n : std_logic;
328
         signal slot2_cs_n : std_logic;
329
 
330
--  signal BaudCount   : std_logic_vector(5 downto 0);
331 141 davidgb
 
332
  signal CountL        : std_logic_vector(23 downto 0);
333
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
334
  signal Clk25         : std_logic;
335
 
336 148 davidgb
  signal vga_clk       : std_logic;
337
 
338 141 davidgb
-----------------------------------------------------------------
339
--
340
-- CPU09 CPU core
341
--
342
-----------------------------------------------------------------
343
 
344
component cpu09
345
  port (
346
    clk:      in  std_logic;
347
    rst:      in  std_logic;
348
    vma:      out std_logic;
349
    addr:     out std_logic_vector(15 downto 0);
350
    rw:       out std_logic;     -- Asynchronous memory interface
351
    data_out: out std_logic_vector(7 downto 0);
352
    data_in:  in  std_logic_vector(7 downto 0);
353
    irq:      in  std_logic;
354
    firq:     in  std_logic;
355
    nmi:      in  std_logic;
356
    halt:     in  std_logic;
357
    hold:     in  std_logic
358
  );
359
end component;
360
 
361
----------------------------------------
362
--
363
-- 4K Block RAM Monitor ROM
364 148 davidgb
-- $F000 - $FFFF
365 141 davidgb
--
366
----------------------------------------
367 148 davidgb
 
368 141 davidgb
component mon_rom
369 148 davidgb
  Port (
370
    clk   : in  std_logic;
371
    rst   : in  std_logic;
372
    cs    : in  std_logic;
373
    rw    : in  std_logic;
374
    addr  : in  std_logic_vector (11 downto 0);
375
    data_out : out std_logic_vector (7 downto 0);
376
    data_in : in  std_logic_vector (7 downto 0)
377
  );
378 141 davidgb
end component;
379
 
380
----------------------------------------
381
--
382
-- 8KBytes Block RAM for FLEX9
383
-- $C000 - $DFFF
384
--
385
----------------------------------------
386 148 davidgb
 
387 141 davidgb
component flex_ram
388
  Port (
389
    clk      : in  std_logic;
390
    rst      : in  std_logic;
391
    cs       : in  std_logic;
392
    rw       : in  std_logic;
393
    addr     : in  std_logic_vector (12 downto 0);
394
    data_out    : out std_logic_vector (7 downto 0);
395
    data_in    : in  std_logic_vector (7 downto 0)
396 148 davidgb
  );
397 141 davidgb
end component;
398
 
399
-----------------------------------------------------------------
400
--
401
-- 6850 Compatible ACIA / UART
402
--
403
-----------------------------------------------------------------
404
 
405
component acia6850
406
  port (
407 148 davidgb
    clk      : in  Std_Logic;  -- System Clock
408
    rst      : in  Std_Logic;  -- Reset input (active high)
409
    cs       : in  Std_Logic;  -- miniUART Chip Select
410
    rw       : in  Std_Logic;  -- Read / Not Write
411
    addr     : in  Std_Logic;  -- Register Select
412
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
413
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
414
    irq      : out Std_Logic;  -- Interrupt
415
    RxC      : in  Std_Logic;  -- Receive Baud Clock
416
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
417
    RxD      : in  Std_Logic;  -- Receive Data
418
    TxD      : out Std_Logic;  -- Transmit Data
419
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
420
    CTS_n    : in  Std_Logic;  -- Clear To Send
421
    RTS_n    : out Std_Logic   -- Request To send
422
  );
423 141 davidgb
end component;
424
 
425
-----------------------------------------------------------------
426
--
427
-- ACIA Clock divider
428
--
429
-----------------------------------------------------------------
430
 
431
component ACIA_Clock
432
  generic (
433 148 davidgb
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
434
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
435 141 davidgb
  );
436
  port (
437 148 davidgb
    clk      : in  Std_Logic;  -- System Clock Input
438
    ACIA_clk : out Std_logic   -- ACIA Clock output
439 141 davidgb
  );
440
end component;
441
 
442
 
443
 
444
 
445
----------------------------------------
446
--
447
-- Timer module
448
--
449
----------------------------------------
450
 
451
component timer
452
  port (
453 148 davidgb
    clk       : in std_logic;
454
    rst       : in std_logic;
455
    cs        : in std_logic;
456
    rw        : in std_logic;
457
    addr      : in std_logic;
458
    data_in   : in std_logic_vector(7 downto 0);
459
    data_out  : out std_logic_vector(7 downto 0);
460
    irq       : out std_logic
461
  );
462 141 davidgb
end component;
463
 
464
------------------------------------------------------------
465
--
466
-- Bus Trap logic
467
--
468
------------------------------------------------------------
469
 
470
component trap
471 148 davidgb
  port (
472 141 davidgb
    clk        : in  std_logic;
473
    rst        : in  std_logic;
474
    cs         : in  std_logic;
475
    rw         : in  std_logic;
476
    vma        : in  std_logic;
477
    addr       : in  std_logic_vector(15 downto 0);
478
    data_in    : in  std_logic_vector(7 downto 0);
479
    data_out   : out std_logic_vector(7 downto 0);
480
    irq        : out std_logic
481
  );
482
end component;
483
 
484
----------------------------------------
485
--
486
-- Dynamic Address Translation Registers
487
--
488
----------------------------------------
489 148 davidgb
 
490 141 davidgb
component dat_ram
491
  port (
492
    clk      : in  std_logic;
493
    rst      : in  std_logic;
494
    cs       : in  std_logic;
495
    rw       : in  std_logic;
496
    addr_lo  : in  std_logic_vector(3 downto 0);
497
    addr_hi  : in  std_logic_vector(3 downto 0);
498
    data_in  : in  std_logic_vector(7 downto 0);
499
    data_out : out std_logic_vector(7 downto 0)
500
  );
501
end component;
502
 
503
 
504
--
505
-- Clock buffer
506
--
507 148 davidgb
 
508 141 davidgb
component BUFG
509
   Port (
510
     i: in std_logic;
511
     o: out std_logic
512
  );
513
end component;
514
 
515
begin
516 148 davidgb
 
517 141 davidgb
  -----------------------------------------------------------------------------
518
  -- Instantiation of internal components
519
  -----------------------------------------------------------------------------
520
 
521 148 davidgb
  my_cpu : cpu09
522
    port map (
523
      clk       => cpu_clk,
524
      rst       => cpu_reset,
525
      vma       => cpu_vma,
526
      addr      => cpu_addr(15 downto 0),
527
      rw        => cpu_rw,
528
      data_out  => cpu_data_out,
529
      data_in   => cpu_data_in,
530
      irq       => cpu_irq,
531
      firq      => cpu_firq,
532
      nmi       => cpu_nmi,
533
      halt      => cpu_halt,
534
      hold      => cpu_hold
535
    );
536 141 davidgb
 
537 148 davidgb
  my_rom : mon_rom
538
    port map (
539
      clk   => cpu_clk,
540
      rst   => cpu_reset,
541
      cs    => rom_cs,
542
      rw    => '1',
543
      addr  => cpu_addr(11 downto 0),
544
      data_in => cpu_data_out,
545
      data_out => rom_data_out
546 141 davidgb
    );
547
 
548 148 davidgb
  my_flex : flex_ram
549
    port map (
550
      clk       => cpu_clk,
551
      rst       => cpu_reset,
552
      cs        => flex_cs,
553
      rw        => cpu_rw,
554
      addr      => cpu_addr(12 downto 0),
555
      data_out     => flex_data_out,
556
      data_in     => cpu_data_out
557 141 davidgb
    );
558
 
559 148 davidgb
  my_acia  : acia6850
560
    port map (
561
      clk       => cpu_clk,
562
      rst       => cpu_reset,
563
      cs        => acia_cs,
564
      rw        => cpu_rw,
565
      addr      => cpu_addr(0),
566
      data_in   => cpu_data_out,
567
      data_out  => acia_data_out,
568
      irq       => acia_irq,
569
      RxC       => acia_clk,
570
      TxC       => acia_clk,
571
      RxD       => rxd,
572
      TxD       => txd,
573
      DCD_n     => dcd_n,
574
      CTS_n     => cts_n,
575
      RTS_n     => rts_n
576 141 davidgb
    );
577
 
578 148 davidgb
  my_ACIA_Clock : ACIA_Clock
579
    generic map(
580
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
581
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
582
    )
583
    port map(
584
      clk        => Clk_i,
585
      acia_clk   => acia_clk
586
    );
587 141 davidgb
 
588 148 davidgb
 
589
  ----------------------------------------
590
  --
591
  -- Timer Module
592
  --
593
  ----------------------------------------
594
  my_timer  : timer
595
    port map (
596
      clk       => cpu_clk,
597
      rst       => cpu_reset,
598
      cs        => timer_cs,
599
      rw        => cpu_rw,
600
      addr      => cpu_addr(0),
601
      data_in   => cpu_data_out,
602
      data_out  => timer_data_out,
603
      irq       => timer_irq
604
    );
605 141 davidgb
 
606 148 davidgb
  ----------------------------------------
607
  --
608
  -- Bus Trap Interrupt logic
609
  --
610
  ----------------------------------------
611
  my_trap : trap
612
    port map (
613
      clk        => cpu_clk,
614
      rst        => cpu_reset,
615
      cs         => trap_cs,
616
      rw         => cpu_rw,
617
      vma        => cpu_vma,
618
      addr       => cpu_addr,
619
      data_in    => cpu_data_out,
620
      data_out   => trap_data_out,
621
      irq        => trap_irq
622 141 davidgb
    );
623
 
624 148 davidgb
  my_dat : dat_ram
625
    port map (
626
      clk       => cpu_clk,
627
      rst       => cpu_reset,
628
      cs        => dat_cs,
629
      rw        => cpu_rw,
630
      addr_hi   => cpu_addr(15 downto 12),
631
      addr_lo   => cpu_addr(3 downto 0),
632
      data_in   => cpu_data_out,
633
      data_out  => dat_addr(7 downto 0)
634 141 davidgb
    );
635
 
636
 
637 148 davidgb
  cpu_clk_buffer : BUFG
638 141 davidgb
    port map(
639 148 davidgb
      i => Clk25,
640
      o => cpu_clk
641 141 davidgb
    );
642
 
643
 
644 148 davidgb
  ----------------------------------------------------------------------
645
  --
646
  -- Process to decode memory map
647
  --
648
  ----------------------------------------------------------------------
649 141 davidgb
 
650 148 davidgb
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
651 141 davidgb
                     dat_addr,
652
                     rom_data_out,
653
                     flex_data_out,
654
                     acia_data_out,
655
                     keyboard_data_out,
656
                     vdu_data_out,
657
                     pb_data_out,
658
                     timer_data_out,
659
                     trap_data_out,
660
                     ram_data_out
661
                     )
662 148 davidgb
  begin
663
    cpu_data_in <= (others=>'0');
664
    dat_cs      <= '0';
665
    rom_cs      <= '0';
666
    flex_cs     <= '0';
667
    acia_cs     <= '0';
668
    keyboard_cs <= '0';
669
    vdu_cs      <= '0';
670
    timer_cs    <= '0';
671
    trap_cs     <= '0';
672
    pb_cs       <= '0';
673
    ide_cs      <= '0';
674
    ether_cs    <= '0';
675
    slot1_cs    <= '0';
676
    slot2_cs    <= '0';
677
    ram_cs      <= '0';
678 141 davidgb
 
679 148 davidgb
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
680
      cpu_data_in <= rom_data_out;
681
      dat_cs      <= cpu_vma;              -- write DAT
682
      rom_cs      <= cpu_vma;              -- read  ROM
683 141 davidgb
 
684 148 davidgb
    --
685
    -- Sys09Bug Monitor ROM $F000 - $FFFF
686
    --
687
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
688
      cpu_data_in <= rom_data_out;
689
      rom_cs      <= cpu_vma;
690 141 davidgb
 
691 148 davidgb
    --
692
    -- IO Devices $E000 - $E7FF
693
    --
694
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
695
      case cpu_addr(11 downto 8) is
696
        --
697
        -- SWTPC peripherals from $E000 to $E0FF
698
        --
699
        when "0000" =>
700
          case cpu_addr(7 downto 4) is
701
          --
702
          -- Console Port ACIA $E000 - $E00F
703
          --
704
            when "0000" => -- $E000
705
              cpu_data_in <= acia_data_out;
706
              acia_cs     <= cpu_vma;
707 141 davidgb
 
708 148 davidgb
            --
709
            -- Reserved
710
            -- Floppy Disk Controller port $E010 - $E01F
711
            --
712 141 davidgb
 
713 148 davidgb
            --
714
            -- Keyboard port $E020 - $E02F
715
            --
716
            when "0010" => -- $E020
717
              cpu_data_in <= keyboard_data_out;
718
              keyboard_cs <= cpu_vma;
719 141 davidgb
 
720 148 davidgb
            --
721
            -- VDU port $E030 - $E03F
722
            --
723
            when "0011" => -- $E030
724
              cpu_data_in <= vdu_data_out;
725
              vdu_cs      <= cpu_vma;
726 141 davidgb
 
727 148 davidgb
            --
728
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
729
            --
730
            when "0100" => -- $E040
731
              cpu_data_in <= (others=> '0');
732 141 davidgb
 
733 148 davidgb
            --
734
            -- Timer $E050 - $E05F
735
            --
736
            when "0101" => -- $E050
737
              cpu_data_in <= timer_data_out;
738
              timer_cs    <= cpu_vma;
739 141 davidgb
 
740 148 davidgb
            --
741
            -- Bus Trap Logic $E060 - $E06F
742
            --
743
            when "0110" => -- $E060
744
              cpu_data_in <= trap_data_out;
745
              trap_cs     <= cpu_vma;
746 141 davidgb
 
747 148 davidgb
            --
748
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
749
            --
750
 
751
            --
752
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
753
            --
754
 
755
            --
756
            -- Remaining 6 slots reserved for non SWTPc Peripherals
757
            --
758
            when others => -- $E0A0 to $E0FF
759
              null;
760
          end case;
761
 
762
        --
763
        -- XST-3.0 Peripheral Bus goes here
764
        -- $E100 to $E1FF
765
        -- Four devices
766
        -- IDE, Ethernet, Slot1, Slot2
767
        --
768
        when "0001" =>
769
          cpu_data_in <= pb_data_out;
770
          pb_cs       <= cpu_vma;
771
          case cpu_addr(7 downto 6) is
772
            --
773
            -- IDE Interface $E100 to $E13F
774
            --
775
            when "00" =>
776
              ide_cs   <= cpu_vma;
777
            --
778
            -- Ethernet Interface $E140 to $E17F
779
            --
780
            when "01" =>
781
              ether_cs <= cpu_vma;
782
            --
783
            -- Slot 1 Interface $E180 to $E1BF
784
            --
785
            when "10" =>
786
              slot1_cs <= cpu_vma;
787
            --
788
            -- Slot 2 Interface $E1C0 to $E1FF
789
            --
790
            when "11" =>
791
              slot2_cs <= cpu_vma;
792
            --
793
            -- Nothing else
794
            --
795
            when others =>
796
              null;
797
          end case;
798
 
799
        --
800
        -- $E200 to $EFFF reserved for future use
801
        --
802
        when others =>
803 141 davidgb
           null;
804 148 davidgb
      end case;
805 141 davidgb
 
806 148 davidgb
    --
807
    -- Flex RAM $0C000 - $0DFFF
808
    --
809
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
810
      cpu_data_in <= flex_data_out;
811
      flex_cs     <= cpu_vma;
812 141 davidgb
 
813 148 davidgb
    --
814
    -- Everything else is RAM
815
    --
816 141 davidgb
    else
817 148 davidgb
      cpu_data_in <= ram_data_out;
818
      ram_cs      <= cpu_vma;
819 141 davidgb
    end if;
820
 
821 148 davidgb
  end process;
822 141 davidgb
 
823
 
824
 
825 148 davidgb
  --
826
  -- Interrupts and other bus control signals
827
  --
828
  interrupts : process( SW3_N,
829 141 davidgb
                      pb_cs, pb_hold, pb_release, ram_hold,
830
--                    ether_irq, 
831
                      acia_irq,
832
                      keyboard_irq,
833
                      trap_irq,
834
                      timer_irq
835
                      )
836 148 davidgb
  begin
837 141 davidgb
    pb_hold    <= pb_cs and (not pb_release);
838
    cpu_irq    <= acia_irq or keyboard_irq;
839
    cpu_nmi    <= trap_irq or not( SW3_N );
840
    cpu_firq   <= timer_irq;
841
    cpu_halt   <= '0';
842
    cpu_hold   <= pb_hold or ram_hold;
843
    FLASH_CE_N <= '1';
844 148 davidgb
  end process;
845 141 davidgb
 
846 148 davidgb
  --
847
  -- Flash 7 segment LEDS
848
  --
849
  my_led_flasher: process( clk_i, rst_i, CountL )
850
  begin
851 141 davidgb
    if rst_i = '1' then
852
         CountL <= "000000000000000000000000";
853
    elsif rising_edge(clk_i) then
854
         CountL <= CountL + 1;
855
    end if;
856 148 davidgb
    --  S(7 downto 0) <= CountL(23 downto 16);
857
  end process;
858 141 davidgb
 
859 148 davidgb
  --
860
  -- Generate CPU & Pixel Clock from Memory Clock
861
  --
862
  my_prescaler : process( clk_i, clk_count )
863
  begin
864
    if rising_edge( clk_i ) then
865
      if clk_count = 0 then
866
        clk_count <= CPU_CLK_DIV-1;
867
      else
868
        clk_count <= clk_count - 1;
869
      end if;
870
      if clk_count = 0 then
871
         clk25 <= '0';
872
      elsif clk_count = (CPU_CLK_DIV/2) then
873
         clk25 <= '1';
874
      end if;
875 141 davidgb
    end if;
876 148 davidgb
  end process;
877 141 davidgb
 
878 148 davidgb
  --
879
  -- Reset button and reset timer
880
  --
881
  my_switch_assignments : process( rst_i, SW2_N, lock )
882
  begin
883
    rst_i <= not SW2_N;
884
    cpu_reset <= rst_i or (not lock);
885
  end process;
886 141 davidgb
 
887 148 davidgb
  --
888
  -- RS232 signals:
889
  --
890
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
891
  begin
892
    rxd       <= RS232_RXD;
893
    cts_n     <= RS232_CTS;
894
    dcd_n     <= '0';
895
    RS232_TXD <= txd;
896
    RS232_RTS <= rts_n;
897
  end process;
898 141 davidgb
 
899 148 davidgb
  --
900
  -- Pin assignments for ethernet controller
901
  --
902
  my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
903
  begin
904 141 davidgb
    ether_cs_n  <= not ether_cs;
905
    ether_aen   <= not ether_cs; -- Ethernet address enable not 
906
    ether_bhe_n <= '1';          -- Ethernet bus high enable - 8 bit access only
907 148 davidgb
  end process;
908 141 davidgb
 
909 148 davidgb
  --
910
  -- I/O expansion slot assignments
911
  --
912
  my_slot_assignments : process( slot1_cs, slot2_cs)
913
  begin
914 141 davidgb
    slot1_cs_n <= not slot1_cs;
915
    slot2_cs_n <= not slot2_cs;
916 148 davidgb
  end process;
917 141 davidgb
 
918
 
919 148 davidgb
  --
920
  -- CPU read data request on rising CPU clock edge
921
  --
922
  ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
923
  begin
924 141 davidgb
    if hRd = '1' then
925
      ram_rd_req   <= '0';
926
    elsif rising_edge(cpu_clk) then
927
      if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
928
        ram_rd_req   <= '1';
929
      end if;
930
    end if;
931 148 davidgb
  end process;
932 141 davidgb
 
933 148 davidgb
  --
934
  -- CPU write data to RAM valid on rising CPU clock edge
935
  --
936
  ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
937
  begin
938 141 davidgb
    if hWr = '1' then
939
       ram_wr_req   <= '0';
940
    elsif rising_edge(cpu_clk) then
941
      if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
942
        ram_wr_req   <= '1';
943
      end if;
944
    end if;
945 148 davidgb
  end process;
946 141 davidgb
 
947 148 davidgb
  status_leds : process( rst_i, cpu_reset, lock )
948
  begin
949 141 davidgb
    S(0) <= rst_i;
950
    S(1) <= cpu_reset;
951
    S(2) <= lock;
952
    S(3) <= countL(23);
953
    S(7 downto 4) <= "0000";
954 148 davidgb
  end process;
955 141 davidgb
 
956 148 davidgb
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
957 141 davidgb
--                      cpu_halt, cpu_hold,
958
--                      cpu_firq, cpu_irq, cpu_nmi,
959
--                      cpu_addr, cpu_data_out, cpu_data_in )
960 148 davidgb
--  begin
961
--    cpu_reset_o    <= cpu_reset;
962
--    cpu_clk_o      <= cpu_clk;
963
--    cpu_rw_o       <= cpu_rw;
964
--    cpu_vma_o      <= cpu_vma;
965
--    cpu_halt_o     <= cpu_halt;
966
--    cpu_hold_o     <= cpu_hold;
967
--    cpu_firq_o     <= cpu_firq;
968
--    cpu_irq_o      <= cpu_irq;
969
--    cpu_nmi_o      <= cpu_nmi;
970
--    cpu_addr_o     <= cpu_addr;
971
--    cpu_data_out_o <= cpu_data_out;
972
--    cpu_data_in_o  <= cpu_data_in;
973
--  end process;
974 141 davidgb
 
975
end rtl; --===================== End of architecture =======================--
976
 

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