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--===========================================================================----
--
--  S Y N T H E Z I A B L E    System09 - SOC.
--
--  www.OpenCores.Org - February 2007
--  This core adheres to the GNU public license  
--
-- File name      : System09_Xess_XSA-3S1000.vhd
--
-- Purpose        : Top level file for 6809 compatible system on a chip
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
--                  Implemented With XESS XSA-3S1000 FPGA board.
--                  *** Note ***
--                  This configuration can run Flex9 however it only has
--                  32k bytes of user memory and the VDU is monochrome
--                  The design needs to be updated to use the SDRAM on 
--                  the XSA-3S1000 board.
--                  This configuration also lacks a DAT so cannot use
--                  the RAM Disk features of SYS09BUG.
--
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_arith
--                  ieee.numeric_std
--                  unisim.vcomponents
--
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
--                  cpu09      (cpu09.vhd)          CPU core
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
--                  timer      (timer.vhd)            Interrupt timer
--                  trap       (trap.vhd)             Bus condition trap logic
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
--                  
-- 
-- Author         : John E. Kent      
--                  dilbert57@opencores.org      
--
-- Memory Map     :
--
-- $0000 - User program RAM (32K Bytes)
-- $C000 - Flex Operating System memory (8K Bytes)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E050 - Timer
-- $E060 - Bus trap
-- $E070 - Reserced for Parallel I/O (B5-X300)
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
-- $F000 - Sys09Bug monitor Program (4K Bytes)
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc" 
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 2.0 - 2 September 2004 - John Kent
-- ported to Digilent Xilinx Spartan3 starter board
-- removed Compact Flash and Trap Logic.
-- Replaced SBUG with KBug9s
--
-- Version 3.0 - 29th August 2006 - John Kent
-- Adapted to XSA-3S1000 board.
-- Removed DAT and miniUART.
-- Used 32KBytes of Block RAM.
--
-- Version 3.1 - 15th January 2007 - John Kent
-- Modified vdu8 interface
-- Added a clock divider
--
-- Version 3.2 - 25th February 2007 - John Kent
-- reinstated ACIA_6850 and ACIA_Clock
-- Updated VDU8 & Keyboard with generic parameters
-- Defined Constants for clock speed calculations
--
-- Version 3.3 - 1st July 2007 - John Kent
-- Made VDU mono to save on one RAMB16
-- Used distributed memory for Key Map ROM to save one RAMB16
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
-- Added timer and trap logic
-- Added IDE Interface for Compact Flash
-- Replaced KBug9s and stack with Sys09Bug.
--
-- Version 4.0 - 1st February 2008 - John kent
-- Replaced Block RAM with SDRAM Interface
-- Modified Hold timing for SDRAM
-- Added CF and Ethernet interface 
-- via the 16 bit peripheral bus at $E100
--
--===========================================================================--
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
library work;
   use work.common.all;
library unisim;
   use unisim.vcomponents.all;
 
entity system09 is
  port(
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    RESET_N      : in  Std_logic;  -- Master Reset input (active low)
    NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
    -- RS232 Port
  --RS232_CTS    : in  std_logic;       
  --RS232_RTS    : out std_logic;  
    RS232_RXD    : in  Std_Logic;  -- RS-232 data in
    RS232_TXD    : out Std_Logic   -- RS-232 data out
 
-- CPU Debug Interface signals
--    cpu_reset_o     : out Std_Logic;
--    cpu_clk_o       : out Std_Logic;
--    cpu_rw_o        : out std_logic;
--    cpu_vma_o       : out std_logic;
--    cpu_halt_o      : out std_logic;
--    cpu_hold_o      : out std_logic;
--    cpu_firq_o      : out std_logic;
--    cpu_irq_o       : out std_logic;
--    cpu_nmi_o       : out std_logic;
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
 
  );
end system09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture rtl of system09 is
 
  -----------------------------------------------------------------------------
  -- constants
  -----------------------------------------------------------------------------
  constant SYS_CLK_FREQ         : natural := 100_000_000; -- FPGA System Clock (in Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
 
  -- BOOT ROM
  signal rom_cs         : Std_logic;
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
  -- Flex Memory & Monitor Stack
  signal flex_cs        : Std_logic;
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
 
  -- ACIA/UART Interface signals
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
  signal acia_cs        : Std_Logic;
  signal acia_irq       : Std_Logic;
  signal acia_clk       : Std_Logic;
  signal rxd            : Std_Logic;
  signal txd            : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
 
  -- RAM
  signal ram1_cs         : std_logic;
  signal ram1_data_out   : std_logic_vector(7 downto 0);
  signal ram2_cs         : std_logic;
  signal ram2_data_out   : std_logic_vector(7 downto 0);
  signal ram3_cs         : std_logic;
 
  -- CPU Interface signals
  signal cpu_reset      : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_rw         : std_logic;
  signal cpu_vma        : std_logic;
  signal cpu_halt       : std_logic;
  signal cpu_hold       : std_logic;
  signal cpu_firq       : std_logic;
  signal cpu_irq        : std_logic;
  signal cpu_nmi        : std_logic;
  signal cpu_addr       : std_logic_vector(15 downto 0);
  signal cpu_data_in    : std_logic_vector(7 downto 0);
  signal cpu_data_out   : std_logic_vector(7 downto 0);
 
  -- Dynamic Address Translation
  signal dat_cs       : std_logic;
  signal dat_addr     : std_logic_vector(7 downto 0);
 
  -- timer
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_cs       : std_logic;
  signal timer_irq      : std_logic;
 
  -- trap
  signal trap_cs        : std_logic;
  signal trap_data_out  : std_logic_vector(7 downto 0);
  signal trap_irq       : std_logic;
 
  signal rst_i         : std_logic;     -- internal reset signal
  signal clk_i         : std_logic;     -- internal master clock signal
 
  signal rs232_cts    :  Std_Logic;
  signal rs232_rts    :  Std_Logic;
 
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
  port (
    clk:      in  std_logic;
    rst:      in  std_logic;
    vma:      out std_logic;
    addr:     out std_logic_vector(15 downto 0);
    rw:       out std_logic;     -- Asynchronous memory interface
    data_out: out std_logic_vector(7 downto 0);
    data_in:  in  std_logic_vector(7 downto 0);
    irq:      in  std_logic;
    firq:     in  std_logic;
    nmi:      in  std_logic;
    halt:     in  std_logic;
    hold:     in  std_logic
  );
end component;
 
----------------------------------------
--
-- 4K Block RAM Monitor ROM
-- $F000 - $FFFF
--
----------------------------------------
 
component mon_rom
  Port (
    clk   : in  std_logic;
    rst   : in  std_logic;
    cs    : in  std_logic;
    rw    : in  std_logic;
    addr  : in  std_logic_vector (11 downto 0);
    data_out : out std_logic_vector (7 downto 0);
    data_in : in  std_logic_vector (7 downto 0)
  );
end component;
 
----------------------------------------
--
-- 8KBytes Block RAM for FLEX9
-- $C000 - $DFFF
--
----------------------------------------
 
component flex_ram
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (12 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
----------------------------------------
--
-- 32KBytes Block RAM 0000
-- $0000 - $7FFF
--
----------------------------------------
 
component ram_32k
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (14 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
 
----------------------------------------
--
-- 16KBytes Block RAM 8000
-- $8000 - $BFFF
--
----------------------------------------
 
component ram_16k
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (13 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
-----------------------------------------------------------------
--
-- 6850 Compatible ACIA / UART
--
-----------------------------------------------------------------
 
component acia6850
  port (
    clk      : in  Std_Logic;  -- System Clock
    rst      : in  Std_Logic;  -- Reset input (active high)
    cs       : in  Std_Logic;  -- miniUART Chip Select
    rw       : in  Std_Logic;  -- Read / Not Write
    addr     : in  Std_Logic;  -- Register Select
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
    irq      : out Std_Logic;  -- Interrupt
    RxC      : in  Std_Logic;  -- Receive Baud Clock
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
    RxD      : in  Std_Logic;  -- Receive Data
    TxD      : out Std_Logic;  -- Transmit Data
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
    CTS_n    : in  Std_Logic;  -- Clear To Send
    RTS_n    : out Std_Logic   -- Request To send
  );
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
  generic (
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
  );
  port (
    clk      : in  Std_Logic;  -- System Clock Input
    ACIA_clk : out Std_logic   -- ACIA Clock output
  );
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
  port (
    clk       : in std_logic;
    rst       : in std_logic;
    cs        : in std_logic;
    rw        : in std_logic;
    addr      : in std_logic;
    data_in   : in std_logic_vector(7 downto 0);
    data_out  : out std_logic_vector(7 downto 0);
    irq       : out std_logic
  );
end component;
 
------------------------------------------------------------
--
-- Bus Trap logic
--
------------------------------------------------------------
 
component trap
  port (
    clk        : in  std_logic;
    rst        : in  std_logic;
    cs         : in  std_logic;
    rw         : in  std_logic;
    vma        : in  std_logic;
    addr       : in  std_logic_vector(15 downto 0);
    data_in    : in  std_logic_vector(7 downto 0);
    data_out   : out std_logic_vector(7 downto 0);
    irq        : out std_logic
  );
end component;
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
 
component dat_ram
  port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr_lo  : in  std_logic_vector(3 downto 0);
    addr_hi  : in  std_logic_vector(3 downto 0);
    data_in  : in  std_logic_vector(7 downto 0);
    data_out : out std_logic_vector(7 downto 0)
  );
end component;
 
----------------------------------------
--
-- Clock buffer
--
----------------------------------------
 
component BUFG
   Port (
     i: in std_logic;
     o: out std_logic
  );
end component;
 
begin
 
  clk_i <= CLKA;
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
  my_cpu : cpu09
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      vma       => cpu_vma,
      addr      => cpu_addr(15 downto 0),
      rw        => cpu_rw,
      data_out  => cpu_data_out,
      data_in   => cpu_data_in,
      irq       => cpu_irq,
      firq      => cpu_firq,
      nmi       => cpu_nmi,
      halt      => cpu_halt,
      hold      => cpu_hold
    );
 
  my_rom : mon_rom
    port map (
      clk   => cpu_clk,
      rst   => cpu_reset,
      cs    => rom_cs,
      rw    => '1',
      addr  => cpu_addr(11 downto 0),
      data_in => cpu_data_out,
      data_out => rom_data_out
    );
 
  my_flex : flex_ram
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => flex_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(12 downto 0),
      data_out     => flex_data_out,
      data_in     => cpu_data_out
    );
 
  my_32k : ram_32k
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => ram1_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(14 downto 0),
      data_out     => ram1_data_out,
      data_in     => cpu_data_out
    );
 
  my_16k : ram_16k
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => ram2_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(13 downto 0),
      data_out     => ram2_data_out,
      data_in     => cpu_data_out
    );
 
  my_acia  : acia6850
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => acia_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(0),
      data_in   => cpu_data_out,
      data_out  => acia_data_out,
      irq       => acia_irq,
      RxC       => acia_clk,
      TxC       => acia_clk,
      RxD       => rxd,
      TxD       => txd,
      DCD_n     => dcd_n,
      CTS_n     => cts_n,
      RTS_n     => rts_n
    );
 
  my_ACIA_Clock : ACIA_Clock
    generic map(
      SYS_CLK_FREQ  => SYS_CLK_FREQ,
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
    )
    port map(
      clk        => Clk_i,
      acia_clk   => acia_clk
    );
 
  ----------------------------------------
  --
  -- Timer Module
  --
  ----------------------------------------
  my_timer  : timer
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => timer_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(0),
      data_in   => cpu_data_out,
      data_out  => timer_data_out,
      irq       => timer_irq
    );
 
  ----------------------------------------
  --
  -- Bus Trap Interrupt logic
  --
  ----------------------------------------
  my_trap : trap
    port map (
      clk        => cpu_clk,
      rst        => cpu_reset,
      cs         => trap_cs,
      rw         => cpu_rw,
      vma        => cpu_vma,
      addr       => cpu_addr,
      data_in    => cpu_data_out,
      data_out   => trap_data_out,
      irq        => trap_irq
    );
 
  my_dat : dat_ram
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => dat_cs,
      rw        => cpu_rw,
      addr_hi   => cpu_addr(15 downto 12),
      addr_lo   => cpu_addr(3 downto 0),
      data_in   => cpu_data_out,
      data_out  => dat_addr(7 downto 0)
    );
 
  cpu_clk_buffer : BUFG
    port map(
      i => Clk25,
      o => cpu_clk
    );
 
  ----------------------------------------------------------------------
  --
  -- Process to decode memory map
  --
  ----------------------------------------------------------------------
 
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
                     dat_addr,
                     rom_data_out,
                     flex_data_out,
                     acia_data_out,
                     timer_data_out,
                     trap_data_out,
                     ram1_data_out, ram2_data_out
                     )
  begin
    cpu_data_in <= (others=>'0');
    dat_cs      <= '0';
    rom_cs      <= '0';
    flex_cs     <= '0';
    acia_cs     <= '0';
    timer_cs    <= '0';
    trap_cs     <= '0';
    ram1_cs      <= '0';
    ram2_cs      <= '0';
 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
      cpu_data_in <= rom_data_out;
      dat_cs      <= cpu_vma;              -- write DAT
      rom_cs      <= cpu_vma;              -- read  ROM
 
    --
    -- Sys09Bug Monitor ROM $F000 - $FFFF
    --
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
      cpu_data_in <= rom_data_out;
      rom_cs      <= cpu_vma;
 
    --
    -- IO Devices $E000 - $E7FF
    --
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
      case cpu_addr(11 downto 8) is
        --
        -- SWTPC peripherals from $E000 to $E0FF
        --
        when "0000" =>
          case cpu_addr(7 downto 4) is
          --
          -- Console Port ACIA $E000 - $E00F
          --
            when "0000" => -- $E000
              cpu_data_in <= acia_data_out;
              acia_cs     <= cpu_vma;
 
            --
            -- Reserved
            -- Floppy Disk Controller port $E010 - $E01F
            --
 
            --
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
            --
            when "0100" => -- $E040
              cpu_data_in <= (others=> '0');
 
            --
            -- Timer $E050 - $E05F
            --
            when "0101" => -- $E050
              cpu_data_in <= timer_data_out;
              timer_cs    <= cpu_vma;
 
            --
            -- Bus Trap Logic $E060 - $E06F
            --
            when "0110" => -- $E060
              cpu_data_in <= trap_data_out;
              trap_cs     <= cpu_vma;
 
            --
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
            --
 
            --
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
            --
 
            --
            -- Remaining 6 slots reserved for non SWTPc Peripherals
            --
            when others => -- $E0A0 to $E0FF
              null;
          end case;
 
        --
        -- $E200 to $EFFF reserved for future use
        --
        when others =>
           null;
      end case;
 
    --
    -- Flex RAM $0C000 - $0DFFF
    --
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
      cpu_data_in <= flex_data_out;
      flex_cs     <= cpu_vma;
 
    --
    -- 32k RAM $00000 - $07FFF
    --
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
      cpu_data_in <= ram1_data_out;
      ram1_cs     <= cpu_vma;
 
    --
    -- 16k RAM $08000 - $0BFFF
    --
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
      cpu_data_in <= ram2_data_out;
      ram2_cs     <= cpu_vma;
 
    --
    -- Everything else is RAM
    --
    else
      cpu_data_in <= (others => '0');
      ram3_cs      <= cpu_vma;
    end if;
 
  end process;
 
  --
  -- Interrupts and other bus control signals
  --
  interrupts : process( NMI_N,
                      acia_irq,
                      trap_irq,
                      timer_irq
                      )
  begin
    cpu_irq    <= acia_irq;
    cpu_nmi    <= trap_irq or not( NMI_N );
    cpu_firq   <= timer_irq;
    cpu_halt   <= '0';
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
  end process;
 
  --
  -- Generate CPU & Pixel Clock from Memory Clock
  --
  my_prescaler : process( clk_i, clk_count )
  begin
    if rising_edge( clk_i ) then
      if clk_count = 0 then
        clk_count <= CPU_CLK_DIV-1;
      else
        clk_count <= clk_count - 1;
      end if;
      if clk_count = 0 then
         clk25 <= '0';
      elsif clk_count = (CPU_CLK_DIV/2) then
         clk25 <= '1';
      end if;
    end if;
  end process;
 
  --
  -- Reset button and reset timer
  --
  my_switch_assignments : process( rst_i, RESET_N)
  begin
    rst_i <= RESET_N;
    cpu_reset <= rst_i;
  end process;
 
  --
  -- RS232 signals:
  --
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
  begin
    rxd       <= RS232_RXD;
    cts_n     <= RS232_CTS;
    dcd_n     <= '0';
    RS232_TXD <= txd;
    RS232_RTS <= rts_n;
  end process;
 
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--                      cpu_halt, cpu_hold,
--                      cpu_firq, cpu_irq, cpu_nmi,
--                      cpu_addr, cpu_data_out, cpu_data_in )
--  begin
--    cpu_reset_o    <= cpu_reset;
--    cpu_clk_o      <= cpu_clk;
--    cpu_rw_o       <= cpu_rw;
--    cpu_vma_o      <= cpu_vma;
--    cpu_halt_o     <= cpu_halt;
--    cpu_hold_o     <= cpu_hold;
--    cpu_firq_o     <= cpu_firq;
--    cpu_irq_o      <= cpu_irq;
--    cpu_nmi_o      <= cpu_nmi;
--    cpu_addr_o     <= cpu_addr;
--    cpu_data_out_o <= cpu_data_out;
--    cpu_data_in_o  <= cpu_data_in;
--  end process;
 
end rtl; --===================== End of architecture =======================--
 

Line No.	Rev	Author	Line
1	141	davidgb	`--===========================================================================----`
2			`--`
3			`-- S Y N T H E Z I A B L E System09 - SOC.`
4			`--`
5			`-- www.OpenCores.Org - February 2007`
6			`-- This core adheres to the GNU public license`
7			`--`
8			`-- File name : System09_Xess_XSA-3S1000.vhd`
9			`--`
10			`-- Purpose : Top level file for 6809 compatible system on a chip`
11			`-- Designed with Xilinx XC3S1000 Spartan 3 FPGA.`
12			`-- Implemented With XESS XSA-3S1000 FPGA board.`
13			`-- * Note *`
14			`-- This configuration can run Flex9 however it only has`
15			`-- 32k bytes of user memory and the VDU is monochrome`
16			`-- The design needs to be updated to use the SDRAM on`
17			`-- the XSA-3S1000 board.`
18			`-- This configuration also lacks a DAT so cannot use`
19			`-- the RAM Disk features of SYS09BUG.`
20			`--`
21			`-- Dependencies : ieee.Std_Logic_1164`
22			`-- ieee.std_logic_unsigned`
23			`-- ieee.std_logic_arith`
24			`-- ieee.numeric_std`
25			`-- unisim.vcomponents`
26			`--`
27			`-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM`
28			`-- cpu09 (cpu09.vhd) CPU core`
29			`-- ACIA_6850 (acia6850.vhd) ACIA / UART`
30			`-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.`
31			`-- timer (timer.vhd) Interrupt timer`
32			`-- trap (trap.vhd) Bus condition trap logic`
33			`-- flex_ram (flex9_ram8k_b16.vhd) Flex operating system`
34			`-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM`
35			`--`
36			`--`
37			`-- Author : John E. Kent`
38			`-- dilbert57@opencores.org`
39			`--`
40			`-- Memory Map :`
41			`--`
42			`-- $0000 - User program RAM (32K Bytes)`
43			`-- $C000 - Flex Operating System memory (8K Bytes)`
44			`-- $E000 - ACIA (SWTPc)`
45			`-- $E010 - Reserved for FD1771 FDC (SWTPc)`
46			`-- $E050 - Timer`
47			`-- $E060 - Bus trap`
48			`-- $E070 - Reserced for Parallel I/O (B5-X300)`
49			`-- $E080 - Reserved for 6821 PIA (?) (SWTPc)`
50			`-- $E090 - Reserved for 6840 PTM (?) (SWTPc)`
51			`-- $F000 - Sys09Bug monitor Program (4K Bytes)`
52			`--`
53			`--===========================================================================----`
54			`--`
55			`-- Revision History:`
56			`--===========================================================================--`
57			`-- Version 0.1 - 20 March 2003`
58			`-- Version 0.2 - 30 March 2003`
59			`-- Version 0.3 - 29 April 2003`
60			`-- Version 0.4 - 29 June 2003`
61			`--`
62			`-- Version 0.5 - 19 July 2003`
63			`-- prints out "Hello World"`
64			`--`
65			`-- Version 0.6 - 5 September 2003`
66			`-- Runs SBUG`
67			`--`
68			`-- Version 1.0- 6 Sep 2003 - John Kent`
69			`-- Inverted SysClk`
70			`-- Initial release to Open Cores`
71			`--`
72			`-- Version 1.1 - 17 Jan 2004 - John Kent`
73			`-- Updated miniUart.`
74			`--`
75			`-- Version 1.2 - 25 Jan 2004 - John Kent`
76			`-- removed signals "test_alu" and "test_cc"`
77			`-- Trap hardware re-instated.`
78			`--`
79			`-- Version 1.3 - 11 Feb 2004 - John Kent`
80			`-- Designed forked off to produce System09_VDU`
81			`-- Added VDU component`
82			`-- VDU runs at 25MHz and divides the clock by 2 for the CPU`
83			`-- UART Runs at 57.6 Kbps`
84			`--`
85			`-- Version 2.0 - 2 September 2004 - John Kent`
86			`-- ported to Digilent Xilinx Spartan3 starter board`
87			`-- removed Compact Flash and Trap Logic.`
88			`-- Replaced SBUG with KBug9s`
89			`--`
90			`-- Version 3.0 - 29th August 2006 - John Kent`
91			`-- Adapted to XSA-3S1000 board.`
92			`-- Removed DAT and miniUART.`
93			`-- Used 32KBytes of Block RAM.`
94			`--`
95			`-- Version 3.1 - 15th January 2007 - John Kent`
96			`-- Modified vdu8 interface`
97			`-- Added a clock divider`
98			`--`
99			`-- Version 3.2 - 25th February 2007 - John Kent`
100			`-- reinstated ACIA_6850 and ACIA_Clock`
101			`-- Updated VDU8 & Keyboard with generic parameters`
102			`-- Defined Constants for clock speed calculations`
103			`--`
104			`-- Version 3.3 - 1st July 2007 - John Kent`
105			`-- Made VDU mono to save on one RAMB16`
106			`-- Used distributed memory for Key Map ROM to save one RAMB16`
107			`-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s`
108			`-- Added timer and trap logic`
109			`-- Added IDE Interface for Compact Flash`
110			`-- Replaced KBug9s and stack with Sys09Bug.`
111			`--`
112			`-- Version 4.0 - 1st February 2008 - John kent`
113			`-- Replaced Block RAM with SDRAM Interface`
114			`-- Modified Hold timing for SDRAM`
115			`-- Added CF and Ethernet interface`
116			`-- via the 16 bit peripheral bus at $E100`
117			`--`
118			`--===========================================================================--`
119			`library ieee;`
120			`use ieee.std_logic_1164.all;`
121			`use IEEE.STD_LOGIC_ARITH.ALL;`
122			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
123			`use ieee.numeric_std.all;`
124			`library work;`
125			`use work.common.all;`
126			`library unisim;`
127	162	davidgb	`use unisim.vcomponents.all;`
128	141	davidgb
129			`entity system09 is`
130			`port(`
131			`CLKA : in Std_Logic; -- 100MHz Clock input`
132	175	davidgb	`RESET_N : in Std_logic; -- Master Reset input (active low)`
133			`NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)`
134	141	davidgb
135	175	davidgb	`-- RS232 Port`
136			`--RS232_CTS : in std_logic;`
137			`--RS232_RTS : out std_logic;`
138			`RS232_RXD : in Std_Logic; -- RS-232 data in`
139			`RS232_TXD : out Std_Logic -- RS-232 data out`
140	141	davidgb
141			`-- CPU Debug Interface signals`
142			`-- cpu_reset_o : out Std_Logic;`
143			`-- cpu_clk_o : out Std_Logic;`
144			`-- cpu_rw_o : out std_logic;`
145			`-- cpu_vma_o : out std_logic;`
146			`-- cpu_halt_o : out std_logic;`
147			`-- cpu_hold_o : out std_logic;`
148			`-- cpu_firq_o : out std_logic;`
149			`-- cpu_irq_o : out std_logic;`
150			`-- cpu_nmi_o : out std_logic;`
151			`-- cpu_addr_o : out std_logic_vector(15 downto 0);`
152			`-- cpu_data_in_o : out std_logic_vector(7 downto 0);`
153			`-- cpu_data_out_o : out std_logic_vector(7 downto 0);`
154
155	148	davidgb	`);`
156	141	davidgb	`end system09;`
157
158			`-------------------------------------------------------------------------------`
159			`-- Architecture for System09`
160			`-------------------------------------------------------------------------------`
161			`architecture rtl of system09 is`
162
163			`-----------------------------------------------------------------------------`
164			`-- constants`
165			`-----------------------------------------------------------------------------`
166	175	davidgb	`constant SYS_CLK_FREQ : natural := 100_000_000; -- FPGA System Clock (in Hz)`
167			`constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)`
168	141	davidgb	`constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);`
169			`constant BAUD_RATE : integer := 57600; -- Baud Rate`
170			`constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;`
171
172			`-----------------------------------------------------------------------------`
173			`-- Signals`
174	174	davidgb	`-----------------------------------------------------------------------------`
175	175	davidgb
176	141	davidgb	`-- BOOT ROM`
177			`signal rom_cs : Std_logic;`
178			`signal rom_data_out : Std_Logic_Vector(7 downto 0);`
179
180			`-- Flex Memory & Monitor Stack`
181			`signal flex_cs : Std_logic;`
182			`signal flex_data_out : Std_Logic_Vector(7 downto 0);`
183
184			`-- ACIA/UART Interface signals`
185			`signal acia_data_out : Std_Logic_Vector(7 downto 0);`
186			`signal acia_cs : Std_Logic;`
187			`signal acia_irq : Std_Logic;`
188			`signal acia_clk : Std_Logic;`
189			`signal rxd : Std_Logic;`
190			`signal txd : Std_Logic;`
191			`signal DCD_n : Std_Logic;`
192			`signal RTS_n : Std_Logic;`
193			`signal CTS_n : Std_Logic;`
194
195			`-- RAM`
196	173	davidgb	`signal ram1_cs : std_logic;`
197			`signal ram1_data_out : std_logic_vector(7 downto 0);`
198			`signal ram2_cs : std_logic;`
199			`signal ram2_data_out : std_logic_vector(7 downto 0);`
200			`signal ram3_cs : std_logic;`
201	141	davidgb
202			`-- CPU Interface signals`
203			`signal cpu_reset : Std_Logic;`
204			`signal cpu_clk : Std_Logic;`
205			`signal cpu_rw : std_logic;`
206			`signal cpu_vma : std_logic;`
207			`signal cpu_halt : std_logic;`
208			`signal cpu_hold : std_logic;`
209			`signal cpu_firq : std_logic;`
210			`signal cpu_irq : std_logic;`
211			`signal cpu_nmi : std_logic;`
212			`signal cpu_addr : std_logic_vector(15 downto 0);`
213			`signal cpu_data_in : std_logic_vector(7 downto 0);`
214			`signal cpu_data_out : std_logic_vector(7 downto 0);`
215
216			`-- Dynamic Address Translation`
217			`signal dat_cs : std_logic;`
218			`signal dat_addr : std_logic_vector(7 downto 0);`
219
220			`-- timer`
221			`signal timer_data_out : std_logic_vector(7 downto 0);`
222			`signal timer_cs : std_logic;`
223			`signal timer_irq : std_logic;`
224
225			`-- trap`
226			`signal trap_cs : std_logic;`
227			`signal trap_data_out : std_logic_vector(7 downto 0);`
228			`signal trap_irq : std_logic;`
229
230			`signal rst_i : std_logic; -- internal reset signal`
231			`signal clk_i : std_logic; -- internal master clock signal`
232	170	davidgb
233	174	davidgb	`signal rs232_cts : Std_Logic;`
234	170	davidgb	`signal rs232_rts : Std_Logic;`
235	148	davidgb
236	141	davidgb	`signal clk_count : natural range 0 to CPU_CLK_DIV;`
237			`signal Clk25 : std_logic;`
238
239			`-----------------------------------------------------------------`
240			`--`
241			`-- CPU09 CPU core`
242			`--`
243			`-----------------------------------------------------------------`
244
245			`component cpu09`
246			`port (`
247			`clk: in std_logic;`
248			`rst: in std_logic;`
249			`vma: out std_logic;`
250			`addr: out std_logic_vector(15 downto 0);`
251			`rw: out std_logic; -- Asynchronous memory interface`
252			`data_out: out std_logic_vector(7 downto 0);`
253			`data_in: in std_logic_vector(7 downto 0);`
254			`irq: in std_logic;`
255			`firq: in std_logic;`
256			`nmi: in std_logic;`
257			`halt: in std_logic;`
258			`hold: in std_logic`
259			`);`
260			`end component;`
261
262			`----------------------------------------`
263			`--`
264			`-- 4K Block RAM Monitor ROM`
265	148	davidgb	`-- $F000 - $FFFF`
266	141	davidgb	`--`
267			`----------------------------------------`
268	148	davidgb
269	141	davidgb	`component mon_rom`
270	148	davidgb	`Port (`
271			`clk : in std_logic;`
272			`rst : in std_logic;`
273			`cs : in std_logic;`
274			`rw : in std_logic;`
275			`addr : in std_logic_vector (11 downto 0);`
276			`data_out : out std_logic_vector (7 downto 0);`
277			`data_in : in std_logic_vector (7 downto 0)`
278			`);`
279	141	davidgb	`end component;`
280
281			`----------------------------------------`
282			`--`
283			`-- 8KBytes Block RAM for FLEX9`
284			`-- $C000 - $DFFF`
285			`--`
286			`----------------------------------------`
287	148	davidgb
288	141	davidgb	`component flex_ram`
289			`Port (`
290			`clk : in std_logic;`
291			`rst : in std_logic;`
292			`cs : in std_logic;`
293			`rw : in std_logic;`
294			`addr : in std_logic_vector (12 downto 0);`
295			`data_out : out std_logic_vector (7 downto 0);`
296			`data_in : in std_logic_vector (7 downto 0)`
297	148	davidgb	`);`
298	141	davidgb	`end component;`
299	170	davidgb
300			`----------------------------------------`
301			`--`
302			`-- 32KBytes Block RAM 0000`
303			`-- $0000 - $7FFF`
304			`--`
305			`----------------------------------------`
306	141	davidgb
307	170	davidgb	`component ram_32k`
308			`Port (`
309			`clk : in std_logic;`
310			`rst : in std_logic;`
311			`cs : in std_logic;`
312			`rw : in std_logic;`
313			`addr : in std_logic_vector (14 downto 0);`
314			`data_out : out std_logic_vector (7 downto 0);`
315			`data_in : in std_logic_vector (7 downto 0)`
316			`);`
317			`end component;`
318
319	173	davidgb
320			`----------------------------------------`
321			`--`
322			`-- 16KBytes Block RAM 8000`
323			`-- $8000 - $BFFF`
324			`--`
325			`----------------------------------------`
326	170	davidgb
327	173	davidgb	`component ram_16k`
328			`Port (`
329			`clk : in std_logic;`
330			`rst : in std_logic;`
331			`cs : in std_logic;`
332			`rw : in std_logic;`
333			`addr : in std_logic_vector (13 downto 0);`
334			`data_out : out std_logic_vector (7 downto 0);`
335			`data_in : in std_logic_vector (7 downto 0)`
336			`);`
337			`end component;`
338
339	141	davidgb	`-----------------------------------------------------------------`
340			`--`
341			`-- 6850 Compatible ACIA / UART`
342			`--`
343			`-----------------------------------------------------------------`
344
345			`component acia6850`
346			`port (`
347	148	davidgb	`clk : in Std_Logic; -- System Clock`
348			`rst : in Std_Logic; -- Reset input (active high)`
349			`cs : in Std_Logic; -- miniUART Chip Select`
350			`rw : in Std_Logic; -- Read / Not Write`
351			`addr : in Std_Logic; -- Register Select`
352			`data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In`
353			`data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out`
354			`irq : out Std_Logic; -- Interrupt`
355			`RxC : in Std_Logic; -- Receive Baud Clock`
356			`TxC : in Std_Logic; -- Transmit Baud Clock`
357			`RxD : in Std_Logic; -- Receive Data`
358			`TxD : out Std_Logic; -- Transmit Data`
359			`DCD_n : in Std_Logic; -- Data Carrier Detect`
360			`CTS_n : in Std_Logic; -- Clear To Send`
361			`RTS_n : out Std_Logic -- Request To send`
362			`);`
363	141	davidgb	`end component;`
364
365			`-----------------------------------------------------------------`
366			`--`
367			`-- ACIA Clock divider`
368			`--`
369			`-----------------------------------------------------------------`
370
371			`component ACIA_Clock`
372			`generic (`
373	148	davidgb	`SYS_CLK_FREQ : integer := SYS_CLK_FREQ;`
374			`ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ`
375	141	davidgb	`);`
376			`port (`
377	148	davidgb	`clk : in Std_Logic; -- System Clock Input`
378			`ACIA_clk : out Std_logic -- ACIA Clock output`
379	141	davidgb	`);`
380			`end component;`
381
382			`----------------------------------------`
383			`--`
384			`-- Timer module`
385			`--`
386			`----------------------------------------`
387
388			`component timer`
389			`port (`
390	148	davidgb	`clk : in std_logic;`
391			`rst : in std_logic;`
392			`cs : in std_logic;`
393			`rw : in std_logic;`
394			`addr : in std_logic;`
395			`data_in : in std_logic_vector(7 downto 0);`
396			`data_out : out std_logic_vector(7 downto 0);`
397			`irq : out std_logic`
398			`);`
399	141	davidgb	`end component;`
400
401			`------------------------------------------------------------`
402			`--`
403			`-- Bus Trap logic`
404			`--`
405			`------------------------------------------------------------`
406
407			`component trap`
408	148	davidgb	`port (`
409	141	davidgb	`clk : in std_logic;`
410			`rst : in std_logic;`
411			`cs : in std_logic;`
412			`rw : in std_logic;`
413			`vma : in std_logic;`
414			`addr : in std_logic_vector(15 downto 0);`
415			`data_in : in std_logic_vector(7 downto 0);`
416			`data_out : out std_logic_vector(7 downto 0);`
417			`irq : out std_logic`
418			`);`
419			`end component;`
420
421			`----------------------------------------`
422			`--`
423			`-- Dynamic Address Translation Registers`
424			`--`
425			`----------------------------------------`
426	148	davidgb
427	141	davidgb	`component dat_ram`
428			`port (`
429			`clk : in std_logic;`
430			`rst : in std_logic;`
431			`cs : in std_logic;`
432			`rw : in std_logic;`
433			`addr_lo : in std_logic_vector(3 downto 0);`
434			`addr_hi : in std_logic_vector(3 downto 0);`
435			`data_in : in std_logic_vector(7 downto 0);`
436			`data_out : out std_logic_vector(7 downto 0)`
437			`);`
438			`end component;`
439	175	davidgb
440			`----------------------------------------`
441	141	davidgb	`--`
442			`-- Clock buffer`
443			`--`
444	175	davidgb	`----------------------------------------`
445	148	davidgb
446	141	davidgb	`component BUFG`
447			`Port (`
448			`i: in std_logic;`
449			`o: out std_logic`
450			`);`
451			`end component;`
452
453	175	davidgb	`begin`
454	169	davidgb
455			`clk_i <= CLKA;`
456	141	davidgb	`-----------------------------------------------------------------------------`
457			`-- Instantiation of internal components`
458			`-----------------------------------------------------------------------------`
459
460	148	davidgb	`my_cpu : cpu09`
461			`port map (`
462			`clk => cpu_clk,`
463			`rst => cpu_reset,`
464			`vma => cpu_vma,`
465			`addr => cpu_addr(15 downto 0),`
466			`rw => cpu_rw,`
467			`data_out => cpu_data_out,`
468			`data_in => cpu_data_in,`
469			`irq => cpu_irq,`
470			`firq => cpu_firq,`
471			`nmi => cpu_nmi,`
472			`halt => cpu_halt,`
473			`hold => cpu_hold`
474			`);`
475	141	davidgb
476	148	davidgb	`my_rom : mon_rom`
477			`port map (`
478			`clk => cpu_clk,`
479			`rst => cpu_reset,`
480			`cs => rom_cs,`
481			`rw => '1',`
482			`addr => cpu_addr(11 downto 0),`
483			`data_in => cpu_data_out,`
484			`data_out => rom_data_out`
485	141	davidgb	`);`
486
487	148	davidgb	`my_flex : flex_ram`
488			`port map (`
489			`clk => cpu_clk,`
490			`rst => cpu_reset,`
491			`cs => flex_cs,`
492			`rw => cpu_rw,`
493			`addr => cpu_addr(12 downto 0),`
494			`data_out => flex_data_out,`
495			`data_in => cpu_data_out`
496	170	davidgb	`);`
497
498			`my_32k : ram_32k`
499			`port map (`
500			`clk => cpu_clk,`

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