OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [btn_debounce.vhd] - Blame information for rev 198

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 187 davidgb 
----------------------------------------------------------------------------
2 
--      btn_debounce.vhd -- Button Debouncer
3 
----------------------------------------------------------------------------
4 
-- Author:  Sam Bobrowicz
5 
--          Copyright 2011 Digilent, Inc.
6 
----------------------------------------------------------------------------
7 
--
8 
----------------------------------------------------------------------------
9 
--      This component is used to debounce signals generated by external push
10 
-- buttons. It is designed to independently debounce 5 Push button signals.
11 
-- Debouncing is done by only registering a change in a button state if
12 
-- it remains constant for 2^16 clock cycles.
13 
--
14 
-- Port Descriptions:
15 
--
16 
--   BTN_I - The input button signals
17 
--    CLK  - Behavior is optimized for a 100 MHz clock
18 
--   BTN_O - The debounced button signals
19 
--
20 
----------------------------------------------------------------------------
21 
--
22 
----------------------------------------------------------------------------
23 
-- Revision History:
24 
--  08/08/2011(SamB): Created using Xilinx Tools 13.2
25 
----------------------------------------------------------------------------
26 
 
27 
library IEEE;
28 
use IEEE.STD_LOGIC_1164.ALL;
29 
use IEEE.std_logic_unsigned.all;
30 
 
31 
entity btn_debounce is
32 
    Port ( BTN_I : in  STD_LOGIC_VECTOR (3 downto 0);
33 
           CLK : in  STD_LOGIC;
34 
           BTN_O : out  STD_LOGIC_VECTOR (3 downto 0));
35 
end btn_debounce;
36 
 
37 
architecture Behavioral of btn_debounce is
38 
 
39 
constant CNTR_MAX : std_logic_vector(15 downto 0) := (others => '1');
40 
 
41 
signal btn0_cntr : std_logic_vector(15 downto 0) := (others => '0');
42 
signal btn1_cntr : std_logic_vector(15 downto 0) := (others => '0');
43 
signal btn2_cntr : std_logic_vector(15 downto 0) := (others => '0');
44 
signal btn3_cntr : std_logic_vector(15 downto 0) := (others => '0');
45 
 
46 
 
47 
signal btn0_reg : std_logic := '0';
48 
signal btn1_reg : std_logic := '0';
49 
signal btn2_reg : std_logic := '0';
50 
signal btn3_reg : std_logic := '0';
51 
 
52 
begin
53 
 
54 
btn0_debounce_process : process (CLK)
55 
begin
56 
        if (rising_edge(CLK)) then
57 
                if (btn0_cntr = CNTR_MAX) then
58 
                        btn0_reg <= not(btn0_reg);
59 
                end if;
60 
        end if;
61 
end process;
62 
 
63 
btn0_counter_process : process (CLK)
64 
begin
65 
        if (rising_edge(CLK)) then
66 
                if ((btn0_reg = '1') xor (BTN_I(0) = '1')) then
67 
                        if (btn0_cntr = CNTR_MAX) then
68 
                                btn0_cntr <= (others => '0');
69 
                        else
70 
                                btn0_cntr <= btn0_cntr + 1;
71 
                        end if;
72 
                else
73 
                        btn0_cntr <= (others => '0');
74 
                end if;
75 
        end if;
76 
end process;
77 
 
78 
btn1_debounce_process : process (CLK)
79 
begin
80 
        if (rising_edge(CLK)) then
81 
                if (btn1_cntr = CNTR_MAX) then
82 
                        btn1_reg <= not(btn1_reg);
83 
                end if;
84 
        end if;
85 
end process;
86 
 
87 
btn1_counter_process : process (CLK)
88 
begin
89 
        if (rising_edge(CLK)) then
90 
                if ((btn1_reg = '1') xor (BTN_I(1) = '1')) then
91 
                        if (btn1_cntr = CNTR_MAX) then
92 
                                btn1_cntr <= (others => '0');
93 
                        else
94 
                                btn1_cntr <= btn1_cntr + 1;
95 
                        end if;
96 
                else
97 
                        btn1_cntr <= (others => '0');
98 
                end if;
99 
        end if;
100 
end process;
101 
 
102 
btn2_debounce_process : process (CLK)
103 
begin
104 
        if (rising_edge(CLK)) then
105 
                if (btn2_cntr = CNTR_MAX) then
106 
                        btn2_reg <= not(btn2_reg);
107 
                end if;
108 
        end if;
109 
end process;
110 
 
111 
btn2_counter_process : process (CLK)
112 
begin
113 
        if (rising_edge(CLK)) then
114 
                if ((btn2_reg = '1') xor (BTN_I(2) = '1')) then
115 
                        if (btn2_cntr = CNTR_MAX) then
116 
                                btn2_cntr <= (others => '0');
117 
                        else
118 
                                btn2_cntr <= btn2_cntr + 1;
119 
                        end if;
120 
                else
121 
                        btn2_cntr <= (others => '0');
122 
                end if;
123 
        end if;
124 
end process;
125 
 
126 
btn3_debounce_process : process (CLK)
127 
begin
128 
        if (rising_edge(CLK)) then
129 
                if (btn3_cntr = CNTR_MAX) then
130 
                        btn3_reg <= not(btn3_reg);
131 
                end if;
132 
        end if;
133 
end process;
134 
 
135 
btn3_counter_process : process (CLK)
136 
begin
137 
        if (rising_edge(CLK)) then
138 
                if ((btn3_reg = '1') xor (BTN_I(3) = '1')) then
139 
                        if (btn3_cntr = CNTR_MAX) then
140 
                                btn3_cntr <= (others => '0');
141 
                        else
142 
                                btn3_cntr <= btn3_cntr + 1;
143 
                        end if;
144 
                else
145 
                        btn3_cntr <= (others => '0');
146 
                end if;
147 
        end if;
148 
end process;
149 
 
150 
 
151 
 
152 
BTN_O <= btn3_reg & btn2_reg & btn1_reg & btn0_reg;
153 
 
154 
end Behavioral;
155 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.