OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.ucf] - Blame information for rev 208

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 178 davidgb 
## This file is a general .xdc for the Zybo Z7 Rev. B
2 
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
3 
## To use it in a project:
4 
## - uncomment the lines corresponding to used pins
5 179 davidgb 
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
6 
 
7 
## System09 usage: This was an XDC file which does not work with ISE 14.7.
8 
## Constraints have been described using UCF syntax.
9 165 davidgb 
 
10 178 davidgb 
##Clock signal
11 179 davidgb 
#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
12 
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
13 187 davidgb 
NET "CLKA" LOC = "K17";
14 
NET "CLKA" IOSTANDARD = LVCMOS33;
15 
NET "CLKA" TNM_NET="CLKA";
16 
TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;
17 165 davidgb 
 
18 178 davidgb 
##Switches
19 
#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
20 
#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
21 
#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
22 
#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
23 187 davidgb 
NET "sw[0]" LOC = "G15";
24 202 davidgb 
 NET "sw[0]" IOSTANDARD = LVCMOS33;
25 187 davidgb 
NET "sw[1]" LOC = "P15";
26 202 davidgb 
 NET "sw[1]" IOSTANDARD = LVCMOS33;
27 187 davidgb 
NET "sw[2]" LOC = "W13";
28 202 davidgb 
 NET "sw[2]" IOSTANDARD = LVCMOS33;
29 187 davidgb 
NET "sw[3]" LOC = "T16";
30 202 davidgb 
 NET "sw[3]" IOSTANDARD = LVCMOS33;
31 178 davidgb 
 
32 
##Buttons
33 187 davidgb 
#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
34 
#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
35 
#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
36 178 davidgb 
#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
37 187 davidgb 
NET "btn[0]" LOC = "K18";
38 202 davidgb 
 NET "btn[0]" IOSTANDARD = LVCMOS33;
39 187 davidgb 
NET "btn[1]" LOC = "P16";
40 202 davidgb 
 NET "btn[1]" IOSTANDARD = LVCMOS33;
41 187 davidgb 
NET "btn[2]" LOC = "K19";
42 202 davidgb 
 NET "btn[2]" IOSTANDARD = LVCMOS33;
43 187 davidgb 
NET "btn[3]" LOC = "Y16";
44 202 davidgb 
 NET "btn[3]" IOSTANDARD = LVCMOS33;
45 178 davidgb 
 
46 
##LEDs
47 
#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
48 
#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
49 
#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
50 
#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
51 187 davidgb 
NET "led[0]" LOC = "M14";
52 202 davidgb 
 NET "led[0]" IOSTANDARD = LVCMOS33;
53 
 NET "led[0]" DRIVE = 12;
54 
 NET "led[0]" SLEW = SLOW;
55 187 davidgb 
NET "led[1]" LOC = "M15";
56 202 davidgb 
 NET "led[1]" IOSTANDARD = LVCMOS33;
57 
 NET "led[1]" DRIVE = 12;
58 
 NET "led[1]" SLEW = SLOW;
59 187 davidgb 
NET "led[2]" LOC = "G14";
60 202 davidgb 
 NET "led[2]" IOSTANDARD = LVCMOS33;
61 
 NET "led[2]" DRIVE = 12;
62 
 NET "led[2]" SLEW = SLOW;
63 187 davidgb 
NET "led[3]" LOC = "D18";
64 202 davidgb 
 NET "led[3]" IOSTANDARD = LVCMOS33;
65 
 NET "led[3]" DRIVE = 12;
66 
 NET "led[3]" SLEW = SLOW;
67 187 davidgb 
 
68 178 davidgb 
 
69 
##RGB LED 5 (Zybo Z7-20 only)
70 
#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
71 
#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
72 
#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
73 
 
74 
##RGB LED 6
75 
#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
76 
#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
77 
#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
78 
 
79 
 
80 
##Audio Codec
81 
#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
82 
#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
83 
#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
84 
#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
85 
#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
86 
#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
87 
#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
88 
#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
89 
#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
90 
 
91 
 
92 
##Additional Ethernet signals
93 
#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
94 
#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
95 
 
96 
 
97 
##USB-OTG over-current detect pin
98 
#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
99 
 
100 
 
101 
##Fan (Zybo Z7-20 only)
102 
#set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS33  PULLUP true    } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
103 
 
104 
 
105 
#HDMI RX
106 
#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
107 
#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
108 
 
109 
#set_property -dict { PACKAGE_PIN U19   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
110 
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
111 
#set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
112 
#set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
113 
#set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
114 
#set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
115 
#set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
116 
#set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
117 
 
118 
#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
119 
 
120 
 
121 
##HDMI RX CEC (Zybo Z7-20 only)
122 
#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
123 
 
124 
 
125 
#HDMI TX
126 
#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_ddc_scl_io }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
127 
#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_ddc_sda_io }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
128 
 
129 
#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
130 
#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
131 
#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[0]  }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
132 
#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[0]  }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
133 
#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[1]  }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
134 
#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[1]  }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
135 
#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[2]  }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
136 
#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[2]  }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
137 
 
138 
#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_hpd   }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
139 200 davidgb 
 
140 
# NET "TMDS_Clk_p" LOC = "H16"; # Clock p
141 
# NET "TMDS_Clk_n" LOC = "H17"; # Clock n
142 
# NET "TMDS_Data_p[2]" LOC = "B19"; #
143 
# NET "TMDS_Data_n[2]" LOC = "A20"; # Red
144 
# NET "TMDS_Data_p[1]" LOC = "C20"; #
145 
# NET "TMDS_Data_n[1]" LOC = "B20"; # Green
146 
# NET "TMDS_Data_p[0]" LOC = "D19"; #
147 
# NET "TMDS_Data_n[0]" LOC = "D20"; # Blue
148 
 
149 
# NET "TMDS_Clk_p" IOSTANDARD = TMDS_33;
150 
# NET "TMDS_Clk_n" IOSTANDARD = TMDS_33;
151 
# NET "TMDS_Data_p[2]" IOSTANDARD = TMDS_33;
152 
# NET "TMDS_Data_n[2]" IOSTANDARD = TMDS_33;
153 
# NET "TMDS_Data_p[1]" IOSTANDARD = TMDS_33;
154 
# NET "TMDS_Data_n[1]" IOSTANDARD = TMDS_33;
155 
# NET "TMDS_Data_p[0]" IOSTANDARD = TMDS_33;
156 
# NET "TMDS_Data_n[0]" IOSTANDARD = TMDS_33;
157 178 davidgb 
 
158 
#HDMI TX CEC
159 
#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
160 
 
161 
 
162 179 davidgb 
##Pmod Header JA (XADC)
163 178 davidgb 
#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
164 
#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
165 179 davidgb 
#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
166 
#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
167 178 davidgb 
#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
168 
#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
169 
#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
170 
#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
171 
 
172 
##Pmod Header JB (Zybo Z7-20 only)
173 
#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33     } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
174 
#set_property -dict { PACKAGE_PIN W8    IOSTANDARD LVCMOS33     } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
175 
#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33     } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
176 
#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVCMOS33     } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
177 
#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVCMOS33     } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
178 
#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVCMOS33     } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
179 
#set_property -dict { PACKAGE_PIN V6    IOSTANDARD LVCMOS33     } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
180 
#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33     } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
181 
 
182 
##Pmod Header JC
183 
#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33     } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
184 
#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33     } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
185 
#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33     } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
186 
#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33     } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
187 
#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33     } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
188 
#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33     } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
189 
#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33     } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
190 202 davidgb 
#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33     } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
191 
# PmodVGA Connector J1 to Zybo JC
192 
NET "VGA_red[0]" LOC = "V15";
193 
 NET "VGA_red[0]" IOSTANDARD = LVCMOS33;
194 
NET "VGA_red[1]" LOC = "W15";
195 
 NET "VGA_red[1]" IOSTANDARD = LVCMOS33;
196 
NET "VGA_red[2]" LOC = "T11";
197 
 NET "VGA_red[2]" IOSTANDARD = LVCMOS33;
198 
NET "VGA_red[3]" LOC = "T10";
199 
 NET "VGA_red[3]" IOSTANDARD = LVCMOS33;
200 
NET "VGA_blue[0]" LOC = "W14";
201 
 NET "VGA_blue[0]" IOSTANDARD = LVCMOS33;
202 
NET "VGA_blue[1]" LOC = "Y14";
203 
 NET "VGA_blue[1]" IOSTANDARD = LVCMOS33;
204 
NET "VGA_blue[2]" LOC = "T12";
205 
 NET "VGA_blue[2]" IOSTANDARD = LVCMOS33;
206 
NET "VGA_blue[3]" LOC = "U12";
207 
 NET "VGA_blue[3]" IOSTANDARD = LVCMOS33;
208 
 
209 178 davidgb 
##Pmod Header JD
210 
#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33     } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
211 
#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33     } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
212 
#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33     } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
213 
#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33     } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
214 
#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33     } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
215 
#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33     } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
216 
#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33     } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
217 202 davidgb 
#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33     } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
218 
# PmodVGA Connector J2 to Zybo JD
219 
NET "VGA_green[0]" LOC = "T14";
220 
 NET "VGA_green[0]" IOSTANDARD = LVCMOS33;
221 
NET "VGA_green[1]" LOC = "T15";
222 
 NET "VGA_green[1]" IOSTANDARD = LVCMOS33;
223 
NET "VGA_green[2]" LOC = "P14";
224 
 NET "VGA_green[2]" IOSTANDARD = LVCMOS33;
225 
NET "VGA_green[3]" LOC = "R14";
226 
 NET "VGA_green[3]" IOSTANDARD = LVCMOS33;
227 
NET "VGA_hsync_n" LOC = "U14";
228 
 NET "VGA_hsync_n" IOSTANDARD = LVCMOS33;
229 
NET "VGA_vsync_n" LOC = "U15";
230 
 NET "VGA_vsync_n" IOSTANDARD = LVCMOS33;
231 
 
232 178 davidgb 
##Pmod Header JE
233 
#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
234 
#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
235 
#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
236 
#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
237 
#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
238 
#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
239 
#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
240 202 davidgb 
#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
241 
##PmodRS232 to Zybo JE
242 198 davidgb 
# Pin   Dir    Function      PMOD    Dir     Function PinLoc
243 
#  1    input   CTS          je<0>   output  CTS      W16
244 
#  2    output  RTS          je<1>   input   RTS      V12
245 
#  3    output  TXD          je<2>   input   RXD      J15
246 
#  4    input   RXD          je<3>   output  TXD      H15
247 
#  5            GND
248 
#  6            VCC
249 196 davidgb 
# NET "RS232_RTS" LOC = "V12";
250 202 davidgb 
#  NET "RS232_RTS" IOSTANDARD = LVCMOS33;
251 196 davidgb 
# NET "RS232_CTS" LOC = "W16";
252 202 davidgb 
#  NET "RS232_CTS" IOSTANDARD = LVCMOS33;
253 
#  NET "RS232_CTS" DRIVE = 12;
254 
#  NET "RS232_CTS" SLEW = SLOW;
255 198 davidgb 
# NET "RS232_RXD" LOC = "J15";
256 202 davidgb 
#  NET "RS232_RXD" IOSTANDARD = LVCMOS33;
257 198 davidgb 
# NET "RS232_TXD" LOC = "H15";
258 202 davidgb 
#  NET "RS232_TXD" IOSTANDARD = LVCMOS33;
259 
#  NET "RS232_TXD" DRIVE = 12;
260 
#  NET "RS232_TXD" SLEW = SLOW;
261 
# PmodUSBUART to Zybo JE
262 198 davidgb 
# Pin   Dir    Function      PMOD    Dir     Function PinLoc
263 199 davidgb 
#  1    output  RTS          je<0>   input   CTS      V12
264 198 davidgb 
#  2    input   RXD          je<1>   output  TXD      W16
265 
#  3    output  TXD          je<2>   input   RXD      J15
266 199 davidgb 
#  4    input   CTS          je<3>   output  RTS      H15
267 198 davidgb 
#  5            GND
268 
#  6            SYS3V3  (make sure Pmod jumper JP1 is LCL-VCC not VCC-SYS to avoid driving 3.3V onto Zybo board)
269 199 davidgb 
NET "RS232_RTS" LOC = "H15";
270 202 davidgb 
 NET "RS232_RTS" IOSTANDARD = LVCMOS33;
271 
 NET "RS232_RTS" DRIVE = 12;
272 
 NET "RS232_RTS" SLEW = SLOW;
273 199 davidgb 
NET "RS232_CTS" LOC = "V12";
274 202 davidgb 
 NET "RS232_CTS" IOSTANDARD = LVCMOS33;
275 179 davidgb 
NET "RS232_RXD" LOC = "J15";
276 202 davidgb 
 NET "RS232_RXD" IOSTANDARD = LVCMOS33;
277 
NET "RS232_TXD" LOC = "W16";
278 
 NET "RS232_TXD" IOSTANDARD = LVCMOS33;
279 
 NET "RS232_TXD" DRIVE = 12;
280 
 NET "RS232_TXD" SLEW = SLOW;
281 178 davidgb 
 
282 
##Pcam MIPI CSI-2 Connector
283 
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
284 
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
285 
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
286 
#set_property -dict { PACKAGE_PIN J19   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
287 
#set_property -dict { PACKAGE_PIN H20   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
288 
#set_property -dict { PACKAGE_PIN M18   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
289 
#set_property -dict { PACKAGE_PIN L19   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
290 
#set_property -dict { PACKAGE_PIN L20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
291 
#set_property -dict { PACKAGE_PIN J20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
292 
#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
293 
#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
294 
#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
295 
#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
296 
#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
297 
#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
298 
#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
299 
#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33     PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
300 
#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
301 
#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
302 
 
303 
 
304 
##Unloaded Crypto Chip SWI (for future use)
305 
#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
306 
 
307 
 
308 
##Unconnected Pins (Zybo Z7-20 only)
309 
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
310 
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
311 
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
312 
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
313 
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
314 
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
315 
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
316 
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
317 
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
318 
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
319 
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
320 
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
321 
 
322 
 

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.