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[/] [System09/] [trunk/] [rtl/] [System09_Memec_XC2V1000/] [System09_Memec_XC2V1000.vhd] - Blame information for rev 95

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1 59 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - September 2003
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S200 Spartan 3 FPGA.
12
--                  Implemented With Digilent Xilinx Starter FPGA board,
13
--
14
-- Dependencies   : ieee.Std_Logic_1164
15
--                  ieee.std_logic_unsigned
16
--                  ieee.std_logic_arith
17
--                  ieee.numeric_std
18
--
19
-- Uses           : mon_rom   (sys09bug_rom4k_b16.vhd) Monitor ROM
20
--                  cpu09     (cpu09.vhd)              CPU core
21
--                  dat_ram   (datram.vhd)             Dynamic Address Translation
22
--                  acia_6850 (acia_6850.vhd)          ACIA (UART)
23
--                            (acia_rx.vhd)
24
--                            (acia_tx.vhd)
25
--                  keyboard  (keyboard.vhd)           PS/2 Keyboard
26
--                            (ps2_keyboard.vhd)
27
--                            (keymap_rom)
28
--                  vdu8      (vdu8.vhd)                          Video Display Unit
29
--                            (char_rom2K_b16.vhd)
30
--                            (ram2k_b16.vhd)
31
--                  seven_segment (SevenSegment.vhd)   Seven Segment Display
32
-- 
33
-- Author         : John E. Kent      
34
--                  dilbert57@opencores.org      
35
--
36
--===========================================================================----
37
--
38
-- Revision History:
39
--===========================================================================--
40
-- Version 0.1 - 20 March 2003
41
-- Version 0.2 - 30 March 2003
42
-- Version 0.3 - 29 April 2003
43
-- Version 0.4 - 29 June 2003
44
--
45
-- Version 0.5 - 19 July 2003
46
-- prints out "Hello World"
47
--
48
-- Version 0.6 - 5 September 2003
49
-- Runs SBUG
50
--
51
-- Version 1.0- 6 Sep 2003 - John Kent
52
-- Inverted sys_clk
53
-- Initial release to Open Cores
54
--
55
-- Version 1.1 - 17 Jan 2004 - John Kent
56
-- Updated miniUart.
57
--
58
-- Version 1.2 - 25 Jan 2004 - John Kent
59
-- removed signals "test_alu" and "test_cc" 
60
-- Trap hardware re-instated.
61
--
62
-- Version 1.3 - 11 Feb 2004 - John Kent
63
-- Designed forked off to produce System09_VDU
64
-- Added VDU component
65
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
66
-- UART Runs at 57.6 Kbps
67
--
68
-- Version 2.0 - 2 September 2004 - John Kent
69
-- ported to Digilent Xilinx Spartan3 starter board
70
--      removed Compaact Flash and Trap Logic.
71
-- Replaced SBUG with KBug9s
72
--
73
-- Version 2.1 - 21 November 2006 - John Kent
74
-- Replaced KBug9s with Sys09bug 1.0
75
-- Inverted bottom nybble of DAT register outputs
76
-- Changed ROM & I/O decoding to be compatible with SWTPc
77
-- Upped the serial baud rate to 115.2 KBd
78
-- added multiple global clock buffers
79
-- (Uart would not operate correctly)
80
--
81
-- Version 2.2 - 22 December 2006 - John Kent
82
-- Increased CPU clock from 12.5MHz to 25 MHz.
83
-- Removed some of the global clock buffers
84
-- Added LED output register
85
-- Changed address decoding to 4K Blocks
86
--
87
-- Version 2.3 - 1 June 2007 - John Kent
88
-- Updated VDU & ACIA
89
-- Changed decoding for Sys09Bug
90
--
91
-- Version 2.4 - 31 January 2008 - John Kent
92
--      ACIA does not appear to work.
93
-- Made RAM OE and WE strobes synchonous to sys_clk
94
--
95
--===========================================================================--
96
library ieee;
97
   use ieee.std_logic_1164.all;
98
   use IEEE.STD_LOGIC_ARITH.ALL;
99
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
100
   use ieee.numeric_std.all;
101
 
102
entity my_system09 is
103
  port(
104
    sys_clk     : in  Std_Logic;  -- System Clock input
105
         rst_sw    : in  Std_logic;  -- Master Reset input (active high)
106
         nmi_sw      : in  Std_logic;
107
 
108
    -- Memory Interface signals
109
    ram_addr    : out Std_Logic_Vector(17 downto 0);
110
    ram_wen     : out Std_Logic;
111
    ram_oen     : out Std_Logic;
112
 
113
    ram1_cen    : out Std_Logic;
114
         ram1_ubn    : out Std_Logic;
115
         ram1_lbn    : out Std_Logic;
116
    ram1_data   : inout Std_Logic_Vector(15 downto 0);
117
 
118
    ram2_cen    : out Std_Logic;
119
         ram2_ubn    : out Std_Logic;
120
         ram2_lbn    : out Std_Logic;
121
    ram2_data   : inout Std_Logic_Vector(15 downto 0);
122
 
123
         -- PS/2 Keyboard
124
         ps2c        : inout Std_logic;
125
         ps2d        : inout Std_Logic;
126
 
127
         -- ACIA Interface
128
    rxd         : in  Std_Logic;
129
         txd         : out Std_Logic;
130
 
131
         -- CRTC output signals
132
         vs          : out Std_Logic;
133
    hs          : out Std_Logic;
134
    blue        : out std_logic;
135
    green       : out std_logic;
136
    red         : out std_logic;
137
 
138
         -- LEDS & Switches
139
         leds        : out std_logic_vector(7 downto 0);
140
         switches    : in  std_logic_vector(7 downto 0);
141
 
142
         -- seven segment display
143
         segments    : out std_logic_vector(7 downto 0);
144
         digits      : out std_logic_vector(3 downto 0)
145
         );
146
end my_system09;
147
 
148
-------------------------------------------------------------------------------
149
-- Architecture for System09
150
-------------------------------------------------------------------------------
151
architecture my_computer of my_system09 is
152
  -----------------------------------------------------------------------------
153
  -- constants
154
  -----------------------------------------------------------------------------
155
  constant SYS_Clock_Frequency  : integer := 100000000;  -- FPGA System Clock
156
  constant VGA_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
157
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
158
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
159
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
160
 
161
  type hold_state_type is ( hold_release_state, hold_request_state );
162
 
163
  -----------------------------------------------------------------------------
164
  -- Signals
165
  -----------------------------------------------------------------------------
166
  -- BOOT ROM
167
  signal rom_cs        : Std_logic;
168
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
169
 
170
  -- FLEX9 RAM
171
  signal flex_cs       : Std_logic;
172
  signal flex_data_out : Std_Logic_Vector(7 downto 0);
173
 
174
  -- ACIA Interface signals
175
  signal acia_clk      : std_logic;
176
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
177
  signal acia_cs       : Std_Logic;
178
  signal acia_irq      : Std_Logic;
179
  signal acia_rxd      : Std_Logic;
180
  signal acia_txd      : Std_Logic;
181
  signal acia_dcd_n    : Std_Logic;
182
--  signal acia_rts_n    : Std_Logic;
183
  signal acia_cts_n    : Std_Logic;
184
 
185
  -- keyboard port
186
  signal keyboard_data_out : std_logic_vector(7 downto 0);
187
  signal keyboard_cs       : std_logic;
188
  signal keyboard_irq      : std_logic;
189
 
190
  -- LEDs
191
  signal leds_data_out : std_logic_vector(7 downto 0);
192
  signal leds_cs       : std_logic;
193
 
194
  -- RAM
195
  signal ram_cs       : std_logic; -- memory chip select
196
  signal ram_data_out : std_logic_vector(7 downto 0);
197
  signal ram1_ce      : std_logic;
198
  signal ram1_ub      : std_logic;
199
  signal ram1_lb      : std_logic;
200
  signal ram2_ce      : std_logic;
201
  signal ram2_ub      : std_logic;
202
  signal ram2_lb      : std_logic;
203
  signal ram_we       : std_logic;
204
  signal ram_oe       : std_logic;
205
 
206
  -- CPU Interface signals
207
  signal cpu_reset    : Std_Logic;
208
  signal cpu_clk      : Std_Logic;
209
  signal cpu_rw       : std_logic;
210
  signal cpu_vma      : std_logic;
211
  signal cpu_halt     : std_logic;
212
  signal cpu_hold     : std_logic;
213
  signal cpu_firq     : std_logic;
214
  signal cpu_irq      : std_logic;
215
  signal cpu_nmi      : std_logic;
216
  signal cpu_addr     : std_logic_vector(15 downto 0);
217
  signal cpu_data_in  : std_logic_vector(7 downto 0);
218
  signal cpu_data_out : std_logic_vector(7 downto 0);
219
 
220
  -- Dynamic Address Translation
221
  signal dat_cs       : std_logic;
222
  signal dat_addr     : std_logic_vector(7 downto 0);
223
 
224
  -- Video Display Unit
225
  signal vdu_cs       : std_logic;
226
  signal vdu_data_out : std_logic_vector(7 downto 0);
227
  signal vga_clk      : std_logic;
228
 
229
  -- 7 Segment Display
230
  signal seg_cs       : std_logic;
231
  signal seg_data_out : std_logic_vector(7 downto 0);
232
 
233
  -- System Clock Prescaler
234
  signal clk_count    : std_logic;
235
  signal Clk50        : std_logic;
236
 
237
-----------------------------------------------------------------
238
--
239
-- CPU09 CPU core
240
--
241
-----------------------------------------------------------------
242
 
243
component cpu09
244
  port (
245
         clk      :     in  std_logic;
246
    rst      : in  std_logic;
247
    rw       :  out std_logic;          -- Asynchronous memory interface
248
    vma      :  out std_logic;
249
    address  : out std_logic_vector(15 downto 0);
250
    data_in  : in        std_logic_vector(7 downto 0);
251
         data_out : out std_logic_vector(7 downto 0);
252
         halt     : in  std_logic;
253
         hold     : in  std_logic;
254
         irq      : in  std_logic;
255
         nmi      : in  std_logic;
256
         firq     : in  std_logic
257
  );
258
end component;
259
 
260
 
261
----------------------------------------
262
--
263
-- 4KByte Block RAM Monitor ROM
264
--
265
----------------------------------------
266
component mon_rom
267
  Port (
268
    clk      : in  std_logic;
269
    rst      : in  std_logic;
270
    cs       : in  std_logic;
271
    rw       : in  std_logic;
272
    addr     : in  std_logic_vector (11 downto 0);
273
    rdata    : out std_logic_vector (7 downto 0);
274
    wdata    : in  std_logic_vector (7 downto 0)
275
    );
276
end component;
277
 
278
----------------------------------------
279
--
280
-- 8KBytes Block RAM for FLEX9
281
-- $C000 - $DFFF
282
--
283
----------------------------------------
284
component flex_ram
285
  Port (
286
    clk      : in  std_logic;
287
    rst      : in  std_logic;
288
    cs       : in  std_logic;
289
    rw       : in  std_logic;
290
    addr     : in  std_logic_vector (12 downto 0);
291
    rdata    : out std_logic_vector (7 downto 0);
292
    wdata    : in  std_logic_vector (7 downto 0)
293
    );
294
end component;
295
 
296
----------------------------------------
297
--
298
-- Dynamic Address Translation Registers
299
--
300
----------------------------------------
301
component dat_ram
302
  port (
303
    clk      : in  std_logic;
304
         rst      : in  std_logic;
305
         cs       : in  std_logic;
306
         rw       : in  std_logic;
307
         addr_lo  : in  std_logic_vector(3 downto 0);
308
         addr_hi  : in  std_logic_vector(3 downto 0);
309
    data_in  : in  std_logic_vector(7 downto 0);
310
         data_out : out std_logic_vector(7 downto 0)
311
  );
312
end component;
313
 
314
-----------------------------------------------------------------
315
--
316
-- 6850 ACIA
317
--
318
-----------------------------------------------------------------
319
 
320
component ACIA_6850
321
  port (
322
    clk      : in  Std_Logic;  -- System Clock
323
    rst      : in  Std_Logic;  -- Reset input (active high)
324
    cs       : in  Std_Logic;  -- ACIA Chip Select
325
    rw       : in  Std_Logic;  -- Read / Not Write
326
    irq      : out Std_Logic;  -- Interrupt
327
    Addr     : in  Std_Logic;  -- Register Select
328
    DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
329
    DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
330
    RxC      : in  Std_Logic;  -- Receive Baud Clock
331
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
332
    RxD      : in  Std_Logic;  -- Receive Data
333
    TxD      : out Std_Logic;  -- Transmit Data
334
         DCD_n    : in  Std_Logic;  -- Data Carrier Detect
335
    CTS_n    : in  Std_Logic;  -- Clear To Send
336
    RTS_n    : out Std_Logic   -- Request To send
337
  );
338
end component;
339
 
340
-----------------------------------------------------------------
341
--
342
-- ACIA Clock divider
343
--
344
-----------------------------------------------------------------
345
 
346
component ACIA_Clock
347
  generic (
348
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
349
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
350
  );
351
  port (
352
     clk      : in  Std_Logic;  -- System Clock Input
353
          ACIA_clk : out Std_logic   -- ACIA Clock output
354
  );
355
end component;
356
 
357
 
358
----------------------------------------
359
--
360
-- PS/2 Keyboard
361
--
362
----------------------------------------
363
 
364
component keyboard
365
  generic(
366
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
367
  );
368
  port(
369
  clk             : in    std_logic;
370
  rst             : in    std_logic;
371
  cs              : in    std_logic;
372
  rw              : in    std_logic;
373
  addr            : in    std_logic;
374
  data_in         : in    std_logic_vector(7 downto 0);
375
  data_out        : out   std_logic_vector(7 downto 0);
376
  irq             : out   std_logic;
377
  kbd_clk         : inout std_logic;
378
  kbd_data        : inout std_logic
379
  );
380
end component;
381
 
382
----------------------------------------
383
--
384
-- Video Display Unit.
385
--
386
----------------------------------------
387
component vdu8
388
      generic(
389
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
390
        VGA_CLOCK_FREQUENCY    : integer := VGA_Clock_Frequency; -- HZ
391
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
392
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
393
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
394
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
395
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
396
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
397
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
398
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
399
             VGA_VER_SYNC           : integer := 1;  -- LINES
400
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
401
      );
402
      port(
403
                -- control register interface
404
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
405
      vdu_rst      : in  std_logic;
406
                vdu_cs       : in  std_logic;
407
                vdu_rw       : in  std_logic;
408
                vdu_addr     : in  std_logic_vector(2 downto 0);
409
      vdu_data_in  : in  std_logic_vector(7 downto 0);
410
      vdu_data_out : out std_logic_vector(7 downto 0);
411
 
412
      -- vga port connections
413
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
414
      vga_red_o    : out std_logic;
415
      vga_green_o  : out std_logic;
416
      vga_blue_o   : out std_logic;
417
      vga_hsync_o  : out std_logic;
418
      vga_vsync_o  : out std_logic
419
   );
420
end component;
421
 
422
----------------------------------------
423
--
424
-- Seven Segment Display driver
425
--
426
----------------------------------------
427
 
428
component seven_segment is
429
        port (
430
          clk         : in  std_logic;
431
     rst         : in  std_logic;
432
     cs          : in  std_logic;
433
     rw          : in  std_logic;
434
     addr        : in  std_logic_vector(1 downto 0);
435
     data_in     : in  std_logic_vector(7 downto 0);
436
          data_out    : out std_logic_vector(7 downto 0);
437
          segments    : out std_logic_vector(7 downto 0);
438
          digits             : out std_logic_vector(3 downto 0)
439
        );
440
end component;
441
 
442
component BUFG
443
  port (
444
    i            : in  std_logic;
445
    o            : out std_logic
446
  );
447
end component;
448
 
449
begin
450
  -----------------------------------------------------------------------------
451
  -- Instantiation of internal components
452
  -----------------------------------------------------------------------------
453
 
454
my_cpu : cpu09  port map (
455
         clk         => cpu_clk,
456
    rst       => cpu_reset,
457
    rw       => cpu_rw,
458
    vma       => cpu_vma,
459
    address   => cpu_addr(15 downto 0),
460
    data_in   => cpu_data_in,
461
         data_out  => cpu_data_out,
462
         halt      => cpu_halt,
463
         hold      => cpu_hold,
464
         irq       => cpu_irq,
465
         nmi       => cpu_nmi,
466
         firq      => cpu_firq
467
    );
468
 
469
my_rom : mon_rom port map (
470
    clk       => cpu_clk,
471
    rst       => cpu_reset,
472
         cs        => rom_cs,
473
         rw        => '1',
474
    addr      => cpu_addr(11 downto 0),
475
    rdata     => rom_data_out,
476
    wdata     => cpu_data_out
477
    );
478
 
479
my_flex : flex_ram port map (
480
    clk       => cpu_clk,
481
    rst       => cpu_reset,
482
         cs        => flex_cs,
483
         rw        => cpu_rw,
484
    addr      => cpu_addr(12 downto 0),
485
    rdata     => flex_data_out,
486
    wdata     => cpu_data_out
487
    );
488
 
489
my_dat : dat_ram port map (
490
    clk       => cpu_clk,
491
         rst       => cpu_reset,
492
         cs        => dat_cs,
493
         rw        => cpu_rw,
494
         addr_hi   => cpu_addr(15 downto 12),
495
         addr_lo   => cpu_addr(3 downto 0),
496
    data_in   => cpu_data_out,
497
         data_out  => dat_addr(7 downto 0)
498
         );
499
 
500
my_acia  : ACIA_6850 port map (
501
         clk         => cpu_clk,
502
         rst       => cpu_reset,
503
    cs        => acia_cs,
504
         rw        => cpu_rw,
505
    irq       => acia_irq,
506
    Addr      => cpu_addr(0),
507
         Datain    => cpu_data_out,
508
         DataOut   => acia_data_out,
509
         RxC       => acia_clk,
510
         TxC       => acia_clk,
511
         RxD       => acia_rxd,
512
         TxD       => acia_txd,
513
         DCD_n     => acia_dcd_n,
514
         CTS_n     => acia_cts_n,
515
         RTS_n     => open
516
         );
517
 
518
 
519
----------------------------------------
520
--
521
-- ACIA Clock
522
--
523
----------------------------------------
524
my_ACIA_Clock : ACIA_Clock
525
  generic map(
526
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
527
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
528
  )
529
  port map(
530
    clk        => sys_clk,
531
    acia_clk   => acia_clk
532
  );
533
 
534
 
535
----------------------------------------
536
--
537
-- PS/2 Keyboard Interface
538
--
539
----------------------------------------
540
my_keyboard : keyboard
541
   generic map (
542
        KBD_Clock_Frequency => CPU_Clock_frequency
543
        )
544
   port map(
545
        clk          => cpu_clk,
546
        rst          => cpu_reset,
547
        cs           => keyboard_cs,
548
        rw           => cpu_rw,
549
        addr         => cpu_addr(0),
550
        data_in      => cpu_data_out(7 downto 0),
551
        data_out     => keyboard_data_out(7 downto 0),
552
        irq          => keyboard_irq,
553
        kbd_clk      => ps2c,
554
        kbd_data     => ps2d
555
        );
556
 
557
----------------------------------------
558
--
559
-- Video Display Unit instantiation
560
--
561
----------------------------------------
562
my_vdu : vdu8
563
  generic map(
564
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
565
      VGA_CLOCK_FREQUENCY    => VGA_Clock_Frequency, -- HZ
566
           VGA_HOR_CHARS          => 80, -- CHARACTERS
567
           VGA_VER_CHARS          => 25, -- CHARACTERS
568
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
569
           VGA_LINES_PER_CHAR     => 16, -- LINES
570
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
571
           VGA_HOR_SYNC           => 96, -- PIXELS
572
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
573
           VGA_VER_BACK_PORCH     => 13, -- LINES
574
           VGA_VER_SYNC           => 1,  -- LINES
575
           VGA_VER_FRONT_PORCH    => 36  -- LINES
576
  )
577
  port map(
578
 
579
                -- Control Registers
580
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
581
      vdu_rst       => cpu_reset,
582
                vdu_cs        => vdu_cs,
583
                vdu_rw        => cpu_rw,
584
                vdu_addr      => cpu_addr(2 downto 0),
585
                vdu_data_in   => cpu_data_out,
586
                vdu_data_out  => vdu_data_out,
587
 
588
      -- vga port connections
589
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
590
      vga_red_o     => red,
591
      vga_green_o   => green,
592
      vga_blue_o    => blue,
593
      vga_hsync_o   => hs,
594
      vga_vsync_o   => vs
595
   );
596
 
597
 
598
----------------------------------------
599
--
600
-- Seven Segment Display instantiation
601
--
602
----------------------------------------
603
 
604
my_seg : seven_segment port map (
605
    clk        => cpu_clk,
606
         rst        => cpu_reset,
607
         cs         => seg_cs,
608
         rw         => cpu_rw,
609
         addr       => cpu_addr(1 downto 0),
610
    data_in    => cpu_data_out,
611
         data_out   => seg_data_out,
612
         segments   => segments,
613
         digits     => digits
614
         );
615
 
616
 
617
vga_clk_buffer : BUFG port map(
618
    i => clk_count,
619
         o => vga_clk
620
    );
621
 
622
cpu_clk_buffer : BUFG port map(
623
    i => clk_count,
624
         o => cpu_clk
625
    );
626
 
627
clk50_clock : process( sys_clk, Clk50 )
628
begin
629
        if sys_clk'event and sys_clk='1' then
630
           Clk50 <= not Clk50;
631
   end if;
632
end process;
633
 
634
--
635
-- Clock divider
636
-- Assumes 50 MHz system clock
637
-- 25MHz pixel clock
638
-- 25MHz CPU clock
639
--
640
sys09_clock : process( Clk50, clk_count )
641
begin
642
        if Clk50'event and CLk50='1' then
643
           clk_count <= not clk_count;
644
   end if;
645
end process;
646
 
647
----------------------------------------------------------------------
648
--
649
-- Process to decode memory map
650
--
651
----------------------------------------------------------------------
652
 
653
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
654
                                              dat_cs, dat_addr,
655
                                              rom_data_out,
656
                                                   acia_data_out,
657
                                                        keyboard_data_out,
658
                                                        vdu_data_out,
659
                                                        seg_data_out,
660
                                                        leds_data_out,
661
                                                        flex_data_out,
662
                                                        ram_data_out
663
                                                        )
664
begin
665
      cpu_data_in <= (others=>'0');
666
      dat_cs      <= '0';
667
      rom_cs      <= '0';
668
      acia_cs     <= '0';
669
      keyboard_cs <= '0';
670
      vdu_cs      <= '0';
671
      seg_cs      <= '0';
672
      leds_cs     <= '0';
673
      flex_cs     <= '0';
674
      ram_cs      <= '0';
675
--           timer_cs    <= '0';
676
--      trap_cs     <= '0';
677
--           pb_cs       <= '0';
678
--      ide_cs      <= '0';
679
--      ether_cs    <= '0';
680
--           slot1_cs    <= '0';
681
--      slot2_cs    <= '0';
682
 
683
      if cpu_addr( 15 downto 8 ) = "11111111" then
684
             cpu_data_in <= rom_data_out;
685
        dat_cs      <= cpu_vma;              -- write DAT
686
        rom_cs      <= cpu_vma;              -- read  ROM
687
           --
688
                -- Sys09Bug Monitor ROM $F000 - $FFFF
689
                --
690
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
691
           --
692
                -- Monitor ROM $F000 - $FFFF
693
                --
694
        cpu_data_in <= rom_data_out;
695
        rom_cs      <= cpu_vma;          -- read  ROM
696
 
697
      --
698
                -- IO Devices $E000 - $EFFF
699
                --
700
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
701
                        case cpu_addr(11 downto 8) is
702
                        --
703
                        -- SWTPC peripherals from $E000 to $E0FF
704
                        --
705
                        when "0000" =>
706
                     case cpu_addr(7 downto 4) is
707
                          --
708
                          -- ACIA ($E000 - $E00F)
709
                          --
710
                          when "0000" =>
711
                       cpu_data_in <= acia_data_out;
712
                            acia_cs     <= cpu_vma;
713
 
714
                --
715
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
716
           --
717
 
718
                          --
719
           -- Keyboard port ($E020 - $E02F)
720
                          --
721
                          when "0010" =>
722
             cpu_data_in <= keyboard_data_out;
723
                            keyboard_cs <= cpu_vma;
724
 
725
           --
726
           -- VDU port ($E030 - $E03F)
727
                          --
728
                          when "0011" =>
729
             cpu_data_in <= vdu_data_out;
730
                            vdu_cs      <= cpu_vma;
731
 
732
           --
733
                          -- Reserved - SWTPc MP-T ($E040 - $E04F)
734
                          --
735
 
736
           --
737
           -- Reserved - Timer ($E050 - $E05F) (B5-X300)
738
                          --
739
 
740
           --
741
           -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300)
742
                          --
743
 
744
           --
745
           -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
746
                          --
747
 
748
                          --
749
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
750
                          --
751
 
752
                          --
753
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
754
                          --
755
 
756
           --
757
                          -- Read Switched port ($E0A0 - $E0AF)
758
                          -- Write LEDS
759
                          --
760
                          when "1010" =>
761
             cpu_data_in <= leds_data_out;
762
                            leds_cs     <= cpu_vma;
763
 
764
           --
765
           -- 7 segment display port ($E0B0 - $E0BF)
766
                          --
767
                          when "1011" =>
768
             cpu_data_in <= seg_data_out;
769
                            seg_cs      <= cpu_vma;
770
 
771
 
772
                          when others => -- $EXC0 to $EXFF
773
                            null;
774
                     end case;
775
                        --
776
                        -- XST-3.0 Peripheral Bus goes here
777
                        --      $E100 to $E1FF
778
                        --      Four devices
779
                        -- IDE, Ethernet, Slot1, Slot2
780
                        --
781
--                      when "0001" =>
782
--                        cpu_data_in <= pb_data_out;
783
--                        pb_cs       <= cpu_vma;
784
--                   case cpu_addr(7 downto 6) is
785
                          --
786
                          -- IDE Interface $E100 to $E13F
787
                          --
788
--                        when "00" =>
789
--                          ide_cs   <= cpu_vma;
790
                          --
791
                          -- Ethernet Interface $E140 to $E17F
792
                          --
793
--                        when "01" =>
794
--                          ether_cs <= cpu_vma;
795
                          --
796
                          -- Slot 1 Interface $E180 to $E1BF
797
                          --
798
--                        when "10" =>
799
--                          slot1_cs <= cpu_vma;
800
                          --
801
                          -- Slot 2 Interface $E1C0 to $E1FF
802
                          --
803
--                        when "11" =>
804
--                          slot2_cs <= cpu_vma;
805
           --
806
                          -- Nothing else
807
                          --
808
--         when others =>
809
--           null;
810
--         end case;
811
         --
812
                        --      $E200 to $EFFF reserved for future use
813
                        --
814
                when others =>
815
                          null;
816
         end case;
817
           --
818
                -- FLEX RAM $0C000 - $0DFFF
819
                --
820
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
821
        cpu_data_in <= flex_data_out;
822
        flex_cs     <= cpu_vma;
823
                --
824
                -- Everything else is RAM
825
                --
826
                else
827
                  cpu_data_in <= ram_data_out;
828
                  ram_cs      <= cpu_vma;
829
    end if;
830
end process;
831
 
832
 
833
--
834
-- 1M byte SRAM Control
835
-- Processes to read and write memory based on bus signals
836
--
837
ram_process: process( cpu_reset, sys_clk,
838
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
839
                                               dat_addr, ram_cs,
840
                      ram1_ce, ram1_ub, ram1_lb, ram1_data,
841
                      ram2_ce, ram2_ub, ram2_lb, ram2_data,
842
                                                         ram_we, ram_oe )
843
begin
844
    --
845
    -- ram_hold signal helps 
846
    --
847
    if( cpu_reset = '1' ) then
848
           ram_we   <= '0';
849
           ram_oe   <= '0';
850
    --
851
         -- Clock Hold on rising edge
852
         --
853
    elsif( sys_clk'event and sys_clk='1' ) then
854
           if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then
855
             ram_we   <= not cpu_rw;
856
             ram_oe   <=     cpu_rw;
857
      else
858
             ram_we   <= '0';
859
             ram_oe   <= '0';
860
      end if;
861
    end if;
862
 
863
         ram_wen  <= not ram_we;
864
         ram_oen  <= not ram_oe;
865
 
866
    ram1_ce   <= ram_cs and (not cpu_addr(1));
867
    ram1_ub   <= not cpu_addr(0);
868
    ram1_lb   <= cpu_addr(0);
869
    ram1_cen  <= not ram1_ce;
870
    ram1_ubn  <= not ram1_ub;
871
    ram1_lbn  <= not ram1_lb;
872
 
873
    ram2_ce   <= ram_cs and cpu_addr(1);
874
    ram2_ub   <= not cpu_addr(0);
875
    ram2_lb   <= cpu_addr(0);
876
    ram2_cen  <= not ram2_ce;
877
    ram2_ubn  <= not ram2_ub;
878
    ram2_lbn  <= not ram2_lb;
879
 
880
         ram_addr(17 downto 10) <= dat_addr(7 downto 0);
881
         ram_addr(9 downto 0) <= cpu_addr(11 downto 2);
882
 
883
    if ram_we = '1' and ram1_ce = '1' and ram1_lb = '1' then
884
                ram1_data(7 downto 0) <= cpu_data_out;
885
         else
886
      ram1_data(7 downto 0)  <= "ZZZZZZZZ";
887
         end if;
888
 
889
    if ram_we = '1' and ram1_ce = '1' and ram1_ub = '1' then
890
                ram1_data(15 downto 8) <= cpu_data_out;
891
         else
892
      ram1_data(15 downto 8)  <= "ZZZZZZZZ";
893
         end if;
894
 
895
    if ram_we = '1' and ram2_ce = '1' and ram2_lb = '1' then
896
                ram2_data(7 downto 0) <= cpu_data_out;
897
         else
898
      ram2_data(7 downto 0)  <= "ZZZZZZZZ";
899
         end if;
900
 
901
    if ram_we = '1' and ram2_ce = '1' and ram2_ub = '1' then
902
                ram2_data(15 downto 8) <= cpu_data_out;
903
         else
904
      ram2_data(15 downto 8)  <= "ZZZZZZZZ";
905
         end if;
906
 
907
         case cpu_addr(1 downto 0) is
908
         when "00" =>
909
      ram_data_out <= ram1_data(15 downto 8);
910
         when "01" =>
911
      ram_data_out <= ram1_data(7 downto 0);
912
         when "10" =>
913
      ram_data_out <= ram2_data(15 downto 8);
914
    when others =>
915
      ram_data_out <= ram2_data(7 downto 0);
916
    end case;
917
end process;
918
 
919
--
920
-- LEDS output register
921
--
922
leds_output : process( cpu_clk, cpu_reset, switches )
923
begin
924
        if cpu_reset = '1' then
925
                leds <= "00000000";
926
        elsif cpu_clk'event and cpu_clk='0' then
927
                if      leds_cs = '1' and cpu_rw = '0' then
928
                        leds <= cpu_data_out;
929
                end if;
930
        end if;
931
        leds_data_out <= switches;
932
end process;
933
 
934
--
935
-- Interrupts and other bus control signals
936
--
937
interrupts : process(   rst_sw,
938
                                                                acia_irq,
939
                                                                keyboard_irq,
940
                                                                nmi_sw
941
                                                         )
942
begin
943
   if sys_clk'event and sys_clk = '1' then
944
          cpu_reset  <= rst_sw; -- CPU reset is active high
945
   end if;
946
        cpu_firq   <= keyboard_irq;
947
        cpu_nmi    <= nmi_sw;
948
        cpu_irq    <= acia_irq;
949
        cpu_halt   <= '0';
950
        cpu_hold   <= '0';
951
end process;
952
 
953
--
954
-- ACIA pin assignments
955
--
956
acia_assignments : process( rxd, acia_txd )
957
begin
958
        acia_dcd_n <= '0';
959
        acia_cts_n <= '0';
960
        acia_rxd   <= rxd;
961
        txd        <= acia_txd;
962
end process;
963
 
964
 
965
end my_computer; --===================== End of architecture =======================--
966
 

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