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[/] [System09/] [trunk/] [rtl/] [System09_Terasic_DE1/] [System09_Terasic_DE1.vhd] - Blame information for rev 215

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1 117 dilbert57
--=============================================================================--
2
--                                                                             --
3
--  System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
4
--                                                                             --
5
--=============================================================================--
6
--
7
--
8
-- File name      : System09_Terasic_DE1.vhd
9
--
10
-- Entity name    : System09
11
--
12
-- Purpose        : Top level file for 6809 compatible system on a chip
13
--                  Designed with Alera EP2C20 Cyclone 2 FPGA.
14
--                  Implemented with Terasic DE1 FPGA board,
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21
-- Uses           : cpu09         (..\VHDL\cpu09.vhd)          CPU core
22
--                  dat_ram       (..\VHDL\datram.vhd)         Dynamic Address Translation
23
--                  mon_rom       (..\Cyclone2\mon_rom.vhd)    Monitor ROM
24
--                  acia6850      (..\VHDL\acia6850.vhd)       ACIA (UART)
25
--                  ACIA_Clock    (..\VHDL\ACIA_Clock.vhd)     ACIA Baud Rate Clock Divider
26
--                  keyboard      (..\VHDL\keyboard.vhd)       PS/2 Keyboard register interface
27
--                  ps2_keyboard  (..\VHDL\ps2_keyboard.vhd)   PS/2 Keyboard interface logic
28
--                  keymap_rom    (..\Cyclone2\keymap_rom.vhd) PS/2 Keyboard key code look up table
29
--                  trap          (..\VHDL\trap.vhd)           Hardware breakpointy trap
30
--                  timer         (..\VHDL\timer.vhd)          Interrupt timer
31
--                  vdu8          (..\VHDL\vdu8.vhd)               Video Display Unit
32
--                                (..\Cyclone2\char_rom.vhd)   Character Generator ROM (B16_RAM)
33
--                                (..\Cyclone2\ram_2k.vhd)     Text & Attribute RAM Buffer
34
--                  sprom         (..\Cyclone2\sprom.vhd)      Single port altsyncrom   
35
--                  spram         (..\Cyclone2\spram.vhd)      Single port altsyncram   
36
--                  bit_funcs     (..\VHDL\bit_funcs.vhd)      Bit manipulation Functions package   
37
-- 
38
-- Author         : John E. Kent      
39
--                  dilbert57@opencores.org      
40
--
41
-- Memory Map     :
42
--
43
-- $0000 - $DFFF System RAM (512K Mapped via DAT)
44
-- $E000 - ACIA (SWTPc)
45
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
46
-- $E020 - Keyboard
47
-- $E030 - VDU
48
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
49
-- $E050 - Timer
50
-- $E060 - Trap (Hardware Breakpoint)
51
-- $E070 - Reserved for Trace Buffer
52
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
53
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
54
-- $E0A0 - Switches in / LEDS out
55
-- $E0B0 - 7 Segment hex display
56
-- $E0C0 - Reserved
57
-- $E0D0 - Reserved
58
-- $E0E0 - Reserved
59
-- $E0F0 - Reserved
60
-- $E100 - $E13F Reserved IDE / Compact Flash Card
61
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
62
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
63
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
64
-- $E200 - $EFFF Reserved for Future I/O
65
-- $F000 - $F7FF RAM for Sys09bug monitor extensions
66
-- $F800 - $FFFF Sys09bug ROM (Read only)
67
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
68
--
69
--
70
--  Copyright (C) 2003 - 2010 John Kent
71
--
72
--  This program is free software: you can redistribute it and/or modify
73
--  it under the terms of the GNU General Public License as published by
74
--  the Free Software Foundation, either version 3 of the License, or
75
--  (at your option) any later version.
76
--
77
--  This program is distributed in the hope that it will be useful,
78
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
79
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
80
--  GNU General Public License for more details.
81
--
82
--  You should have received a copy of the GNU General Public License
83
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
84
--
85
--===========================================================================--
86
--
87
--                              Revision History:
88
--
89
--===========================================================================--
90
--
91
-- Version 0.1 - 20 March 2003
92
-- Version 0.2 - 30 March 2003
93
-- Version 0.3 - 29 April 2003
94
-- Version 0.4 - 29 June 2003
95
--
96
-- Version 0.5 - 19 July 2003
97
-- prints out "Hello World"
98
--
99
-- Version 0.6 - 5 September 2003
100
-- Runs SBUG
101
--
102
-- Version 1.0- 6 Sep 2003 - John Kent
103
-- Inverted sys_clk
104
-- Initial release to Open Cores
105
--
106
-- Version 1.1 - 17 Jan 2004 - John Kent
107
-- Updated miniUart.
108
--
109
-- Version 1.2 - 25 Jan 2004 - John Kent
110
-- removed signals "test_alu" and "test_cc" 
111
-- Trap hardware re-instated.
112
--
113
-- Version 1.3 - 11 Feb 2004 - John Kent
114
-- Designed forked off to produce System09_VDU
115
-- Added VDU component
116
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
117
-- UART Runs at 57.6 Kbps
118
--
119
-- Version 2.0 - 2 September 2004 - John Kent
120
-- ported to Digilent Xilinx Spartan3 starter board
121
--      removed Compaact Flash and Trap Logic.
122
-- Replaced SBUG with KBug9s
123
--
124
-- Version 2.1 - 21 November 2006 - John Kent
125
-- Replaced KBug9s with Sys09bug 1.0
126
-- Inverted bottom nybble of DAT register outputs
127
-- Changed ROM & I/O decoding to be compatible with SWTPc
128
-- Upped the serial baud rate to 115.2 KBd
129
-- added multiple global clock buffers
130
-- (Uart would not operate correctly)
131
--
132
-- Version 2.2 - 22 December 2006 - John Kent
133
-- Increased CPU clock from 12.5MHz to 25 MHz.
134
-- Removed some of the global clock buffers
135
-- Added LED output register
136
-- Changed address decoding to 4K Blocks
137
--
138
-- Version 2.3 - 1 June 2007 - John Kent
139
-- Updated VDU & ACIA
140
-- Changed decoding for Sys09Bug
141
--
142
-- Version 2.4 - 31 January 2008 - John Kent
143
--      ACIA does not appear to work.
144
-- Made RAM OE and WE strobes synchonous to sys_clk
145
--
146
-- Version 2.5 - 23rd Feburary 2009 - John Kent
147
-- Implemented recommendation to remove vga_clk clock buffer
148
--
149
-- Version 2.6 - 5th september 2010 - John Kent
150
-- Renamed ACIA_6850 to acia6850
151
-- Updated generics on VDU8
152
-- Shortened the "keyboard" label
153
-- Fixed up address label on CPU09
154
-- Removed Flex RAM
155
-- Map RAM at $F000 - $F7FF
156
--
157
-- Vesrion 2.7 - 22nd October 2010 - John Kent
158
-- Ported from Digilent XC3S200 Starter to 
159
-- Terasic EP2C20 DE1 board.
160
--   
161
--===========================================================================--
162
library ieee;
163
   use ieee.std_logic_1164.all;
164
   use IEEE.STD_LOGIC_ARITH.ALL;
165
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
166
   use ieee.numeric_std.all;
167
 
168
entity System09_Terasic_DE1 is
169
  port(
170
        -- clocks
171
        clock_24    : in    std_logic_vector(1 downto 0);
172
        clock_27    : in    std_logic;
173
    clock_50    : in    std_logic;  -- System Clock input
174
    ext_clock   : in    std_logic;
175
 
176
    -- push button keys
177
        key         : in    std_logic_vector(3 downto 0);  -- RST, NMI
178
 
179
    -- SRAM interface signals
180
 
181
    sram_ce_n   : out   std_logic;
182
    sram_we_n   : out   std_logic;
183
    sram_oe_n   : out   std_logic;
184
        sram_ub_n   : out   std_logic;
185
        sram_lb_n   : out   std_logic;
186
    sram_addr   : out   std_logic_vector(17 downto 0);
187
    sram_dq     : inout std_logic_vector(15 downto 0);
188
 
189
        -- PS/2 Keyboard
190
        ps2_clk     : inout Std_logic;
191
        ps2_dat     : inout Std_Logic;
192
 
193
        -- ACIA/UART Interface
194
    uart_rxd    : in  Std_Logic;
195
        uart_txd    : out Std_Logic;
196
 
197
        -- CRTC output signals
198
    vga_r       : out std_logic_vector(3 downto 0);
199
    vga_g       : out std_logic_vector(3 downto 0);
200
    vga_b       : out std_logic_vector(3 downto 0);
201
    vga_hs      : out Std_Logic;
202
        vga_vs      : out Std_Logic;
203
 
204
        -- LEDS & Switches
205
        ledg        : out std_logic_vector(7 downto 0);
206
        ledr        : out std_logic_vector(9 downto 0);
207
        sw          : in  std_logic_vector(9 downto 0);
208
 
209
        -- hexadecimal display
210
        hex0        : out std_logic_vector(6 downto 0);
211
        hex1        : out std_logic_vector(6 downto 0);
212
        hex2        : out std_logic_vector(6 downto 0);
213
        hex3        : out std_logic_vector(6 downto 0);
214
 
215
        -- gnereal purpose I/O
216
        gpio_0      : in  std_logic_vector(35 downto 0);
217
        gpio_1      : in  std_logic_vector(35 downto 0);
218
 
219
        -- i2c interface
220
        i2c_sclk    : in std_logic;
221
        i2c_sdat    : in std_logic;
222
 
223
        -- audio codec
224
        aud_adcdat  : in std_logic;
225
        aud_adclrck : in std_logic;
226
        aud_bclk    : in std_logic;
227
        aud_dacdat  : in std_logic;
228
        aud_daclrck : in std_logic;
229
        aud_xck     : in std_logic;
230
 
231
        -- dram
232
        dram_addr  : out std_logic_vector(11 downto 0);
233
        dram_dq    : in  std_logic_vector(15 downto 0);
234
        dram_cs_n  : out std_logic;
235
        dram_ba_0  : in std_logic;
236
        dram_ba_1  : in std_logic;
237
        dram_ldqm  : in std_logic;
238
        dram_udqm  : in std_logic;
239
        dram_ras_n : out std_logic;
240
        dram_cas_n : out std_logic;
241
        dram_we_n  : out std_logic;
242
        dram_cke   : in std_logic;
243
        dram_clk   : in std_logic;
244
 
245
         -- Flash memory
246
        fl_addr    : out std_logic_vector(21 downto 0);
247
        fl_dq      : in  std_logic_vector(7 downto 0);
248
        fl_rst_n   : in  std_logic;
249
        fl_oe_n    : out std_logic;
250
        fl_we_n    : out std_logic;
251
 
252
        -- JTAG
253
        tck        : in std_logic;
254
        tcs        : in std_logic;
255
        tdi        : in std_logic;
256
        tdo        : in std_logic
257
        );
258
end System09_Terasic_DE1;
259
 
260
-------------------------------------------------------------------------------
261
-- Architecture for System09
262
-------------------------------------------------------------------------------
263
architecture my_computer of System09_Terasic_DE1 is
264
  -----------------------------------------------------------------------------
265
  -- constants
266
  -----------------------------------------------------------------------------
267
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
268
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
269
  constant CPU_CLK_FREQ  : integer := 25000000;  -- CPU Clock
270
  constant BAUD_Rate     : integer := 57600;      -- Baud Rate
271
  constant ACIA_CLK_FREQ : integer := BAUD_Rate * 16;
272
 
273
  type hold_state_type is ( hold_release_state, hold_request_state );
274
 
275
  -----------------------------------------------------------------------------
276
  -- Signals
277
  -----------------------------------------------------------------------------
278
 
279
  signal sys_clk       : std_logic;
280
  signal vga_clk       : std_logic;
281
  signal pll_locked    : std_logic;
282
 
283
  -- CPU Interface signals
284
  signal cpu_clk       : std_logic;
285
  signal cpu_rst       : std_logic;
286
  signal cpu_rw        : std_logic;
287
  signal cpu_vma       : std_logic;
288
  signal cpu_halt      : std_logic;
289
  signal cpu_hold      : std_logic;
290
  signal cpu_firq      : std_logic;
291
  signal cpu_irq       : std_logic;
292
  signal cpu_nmi       : std_logic;
293
  signal cpu_addr      : std_logic_vector(15 downto 0);
294
  signal cpu_data_in   : std_logic_vector(7 downto 0);
295
  signal cpu_data_out  : std_logic_vector(7 downto 0);
296
 
297
  -- Dynamic Address Translation
298
  signal dat_cs        : std_logic;
299
  signal dat_addr      : std_logic_vector(7 downto 0);
300
 
301
  -- BOOT ROM
302
  signal rom_cs        : Std_logic;
303
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
304
 
305
  -- ACIA Interface signals
306
  signal acia_clk      : std_logic;
307
  signal acia_cs       : Std_Logic;
308
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
309
  signal acia_irq      : Std_Logic;
310
  signal acia_rxd      : Std_Logic;
311
  signal acia_txd      : Std_Logic;
312
  signal acia_dcd_n    : Std_Logic;
313
--  signal acia_rts_n    : Std_Logic;
314
  signal acia_cts_n    : Std_Logic;
315
 
316
  -- keyboard port
317
  signal kbd_data_out : std_logic_vector(7 downto 0);
318
  signal kbd_cs       : std_logic;
319
  signal kbd_irq      : std_logic;
320
 
321
  -- LEDs
322
  signal leds_data_out : std_logic_vector(7 downto 0);
323
  signal leds_cs       : std_logic;
324
 
325
  -- Video Display Unit
326
  signal vdu_cs       : std_logic;
327
  signal vdu_data_out : std_logic_vector(7 downto 0);
328
  signal vga_red      : std_logic;
329
  signal vga_green    : std_logic;
330
  signal vga_blue     : std_logic;
331
 
332
  -- LEDs
333
  signal led_cs       : std_logic;
334
  signal led_data_out : std_logic_vector(7 downto 0);
335
 
336
  -- 7 Segment Display
337
  signal hex_cs       : std_logic;
338
  signal hex_data_out : std_logic_vector(7 downto 0);
339
  signal hex0_reg     : std_logic_vector(7 downto 0);
340
  signal hex1_reg     : std_logic_vector(7 downto 0);
341
  signal hex2_reg     : std_logic_vector(7 downto 0);
342
  signal hex3_reg     : std_logic_vector(7 downto 0);
343
 
344
  -- interrupt timer
345
  signal tmr_data_out : std_logic_vector(7 downto 0);
346
  signal tmr_cs       : std_logic;
347
  signal tmr_irq      : std_logic;
348
 
349
  -- hardware break point (trap)
350
  signal hbp_data_out : std_logic_vector(7 downto 0);
351
  signal hbp_cs       : std_logic;
352
  signal hbp_irq      : std_logic;
353
 
354
  -- RAM
355
  signal sram_cs       : std_logic; -- memory chip select
356
  signal sram_data_out : std_logic_vector(7 downto 0);
357
  signal sram_ce       : std_logic;
358
  signal sram_ub       : std_logic;
359
  signal sram_lb       : std_logic;
360
  signal sram_we       : std_logic;
361
  signal sram_oe       : std_logic;
362
 
363
  -- System Clock Prescaler
364
  signal clk_count     : std_logic;
365
 
366
-----------------------------------------------------------------
367
--
368
-- CPU09 CPU core
369
--
370
-----------------------------------------------------------------
371
 
372
component cpu09
373
  port (
374
         clk      :     in  std_logic;
375
    rst      : in  std_logic;
376
    vma      :  out std_logic;
377
    addr     : out std_logic_vector(15 downto 0);
378
    rw       :  out std_logic;
379
    data_in  : in        std_logic_vector(7 downto 0);
380
         data_out : out std_logic_vector(7 downto 0);
381
         halt     : in  std_logic;
382
         hold     : in  std_logic;
383
         irq      : in  std_logic;
384
         nmi      : in  std_logic;
385
         firq     : in  std_logic
386
  );
387
end component;
388
 
389
----------------------------------------
390
--
391
-- Dynamic Address Translation Registers
392
--
393
----------------------------------------
394
component dat_ram
395
        port (
396
                clk      : in  std_logic;
397
                rst      : in  std_logic;
398
                cs       : in  std_logic;
399
                rw       : in  std_logic;
400
                addr_lo  : in  std_logic_vector(3 downto 0);
401
                addr_hi  : in  std_logic_vector(3 downto 0);
402
                data_in  : in  std_logic_vector(7 downto 0);
403
                data_out : out std_logic_vector(7 downto 0)
404
        );
405
end component;
406
 
407
----------------------------------------
408
--
409
-- 4KByte Block RAM Monitor ROM
410
--
411
----------------------------------------
412
component mon_rom
413
  Port (
414
    clk      : in  std_logic;
415
    rst      : in  std_logic;
416
    cs       : in  std_logic;
417
    rw       : in  std_logic;
418
    addr     : in  std_logic_vector (10 downto 0);
419
    data_in  : in  std_logic_vector (7 downto 0);
420
    data_out : out std_logic_vector (7 downto 0)
421
    );
422
end component;
423
 
424
-----------------------------------------------------------------
425
--
426
-- 6850 ACIA
427
--
428
-----------------------------------------------------------------
429
 
430
component acia6850
431
  port (
432
    clk      : in  Std_Logic;  -- System Clock
433
    rst      : in  Std_Logic;  -- Reset input (active high)
434
    cs       : in  Std_Logic;  -- ACIA Chip Select
435
    rw       : in  Std_Logic;  -- Read / Not Write
436
    addr     : in  Std_Logic;  -- Register Select
437
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
438
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
439
    irq      : out Std_Logic;  -- Interrupt
440
    RxC      : in  Std_Logic;  -- Receive Baud Clock
441
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
442
    RxD      : in  Std_Logic;  -- Receive Data
443
    TxD      : out Std_Logic;  -- Transmit Data
444
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
445
    CTS_n    : in  Std_Logic;  -- Clear To Send
446
    RTS_n    : out Std_Logic   -- Request To send
447
  );
448
end component;
449
 
450
-----------------------------------------------------------------
451
--
452
-- ACIA Clock divider
453
--
454
-----------------------------------------------------------------
455
 
456
component ACIA_Clock
457
  generic (
458
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
459
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
460
  );
461
  port (
462
     clk      : in  Std_Logic;  -- System Clock Input
463
          acia_clk : out Std_logic   -- ACIA Clock output
464
  );
465
end component;
466
 
467
----------------------------------------
468
--
469
-- PS/2 Keyboard
470
--
471
----------------------------------------
472
 
473
component keyboard
474
  generic(
475
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
476
  );
477
  port(
478
    clk             : in    std_logic;
479
    rst             : in    std_logic;
480
    cs              : in    std_logic;
481
    addr            : in    std_logic;
482
    rw              : in    std_logic;
483
    data_in         : in    std_logic_vector(7 downto 0);
484
    data_out        : out   std_logic_vector(7 downto 0);
485
    irq             : out   std_logic;
486
    kbd_clk         : inout std_logic;
487
    kbd_data        : inout std_logic
488
  );
489
end component;
490
 
491
----------------------------------------
492
--
493
-- Video Display Unit.
494
--
495
----------------------------------------
496
component vdu8
497
  generic(
498
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
499
         VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
500
         VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
501
         VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
502
         VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
503
         VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
504
         VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
505
         VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
506
         VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
507
         VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
508
         VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
509
  );
510
  port(
511
    -- control register interface
512
    vdu_clk      : in  std_logic;        -- CPU Clock - 12.5MHz
513
    vdu_rst      : in  std_logic;
514
    vdu_cs       : in  std_logic;
515
    vdu_rw       : in  std_logic;
516
    vdu_addr     : in  std_logic_vector(2 downto 0);
517
    vdu_data_in  : in  std_logic_vector(7 downto 0);
518
    vdu_data_out : out std_logic_vector(7 downto 0);
519
 
520
    -- vga port connections
521
    vga_clk      : in  std_logic;       -- VGA Pixel Clock - 25 MHz
522
    vga_red_o    : out std_logic;
523
    vga_green_o  : out std_logic;
524
    vga_blue_o   : out std_logic;
525
    vga_hsync_o  : out std_logic;
526
    vga_vsync_o  : out std_logic
527
  );
528
end component;
529
 
530
----------------------------------------
531
--
532
-- Interrupt timer
533
--
534
----------------------------------------
535
 
536
component timer is
537
        port (
538
                clk        : in  std_logic;
539
                rst        : in  std_logic;
540
                cs         : in  std_logic;
541
                addr       : in  std_logic;
542
                rw         : in  std_logic;
543
                data_in    : in  std_logic_vector(7 downto 0);
544
                data_out   : out std_logic_vector(7 downto 0);
545
                irq        : out std_logic
546
        );
547
end component;
548
 
549
----------------------------------------
550
--
551
-- hardware break point (bus trap)
552
--
553
----------------------------------------
554
 
555
component trap is
556
        port (
557
                clk        : in  std_logic;
558
                rst        : in  std_logic;
559
                cs         : in  std_logic;
560
                rw         : in  std_logic;
561
                vma        : in  std_logic;
562
                addr       : in  std_logic_vector(15 downto 0);
563
                data_in    : in  std_logic_vector(7 downto 0);
564
                data_out   : out std_logic_vector(7 downto 0);
565
                irq        : out std_logic
566
        );
567
end component;
568
 
569
 
570
component pll IS
571
        PORT
572
        (
573
                areset          : IN STD_LOGIC  := '0';
574
                inclk0          : IN STD_LOGIC  := '0';
575
                c0                      : OUT STD_LOGIC ;
576
                c1                      : OUT STD_LOGIC ;
577
                c2                      : OUT STD_LOGIC ;
578
                locked          : OUT STD_LOGIC
579
        );
580
END component;
581
 
582
begin
583
  -----------------------------------------------------------------------------
584
  -- Instantiation of internal components
585
  -----------------------------------------------------------------------------
586
 
587
my_cpu : cpu09  port map (
588
         clk         => cpu_clk,
589
    rst       => cpu_rst,
590
    vma       => cpu_vma,
591
    addr      => cpu_addr(15 downto 0),
592
    rw       => cpu_rw,
593
    data_in   => cpu_data_in,
594
         data_out  => cpu_data_out,
595
         halt      => cpu_halt,
596
         hold      => cpu_hold,
597
         irq       => cpu_irq,
598
         nmi       => cpu_nmi,
599
         firq      => cpu_firq
600
    );
601
 
602
my_dat : dat_ram port map (
603
    clk       => cpu_clk,
604
        rst       => cpu_rst,
605
        cs        => dat_cs,
606
        addr_hi   => cpu_addr(15 downto 12),
607
        addr_lo   => cpu_addr(3 downto 0),
608
        rw        => cpu_rw,
609
        data_in   => cpu_data_out,
610
        data_out  => dat_addr(7 downto 0)
611
         );
612
 
613
my_rom : mon_rom port map (
614
    clk       => cpu_clk,
615
    rst       => cpu_rst,
616
        cs        => rom_cs,
617
        rw        => '1',
618
    addr      => cpu_addr(10 downto 0),
619
    data_in   => cpu_data_out,
620
    data_out  => rom_data_out
621
    );
622
 
623
my_acia  : acia6850 port map (
624
        clk           => cpu_clk,
625
        rst       => cpu_rst,
626
    cs        => acia_cs,
627
    addr      => cpu_addr(0),
628
        rw        => cpu_rw,
629
        data_in   => cpu_data_out,
630
        data_out  => acia_data_out,
631
    irq       => acia_irq,
632
        RxC       => acia_clk,
633
        TxC       => acia_clk,
634
        RxD       => acia_rxd,
635
        TxD       => acia_txd,
636
        DCD_n     => acia_dcd_n,
637
        CTS_n     => acia_cts_n,
638
        RTS_n     => open
639
    );
640
 
641
 
642
----------------------------------------
643
--
644
-- ACIA Clock
645
--
646
----------------------------------------
647
my_ACIA_Clock : ACIA_Clock
648
  generic map(
649
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
650
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
651
  )
652
  port map(
653
    clk        => sys_clk,
654
    acia_clk   => acia_clk
655
  );
656
 
657
 
658
----------------------------------------
659
--
660
-- PS/2 Keyboard Interface
661
--
662
----------------------------------------
663
my_keyboard : keyboard
664
   generic map (
665
          KBD_CLK_FREQ => CPU_CLK_FREQ
666
        )
667
   port map(
668
          clk          => cpu_clk,
669
          rst          => cpu_rst,
670
          cs           => kbd_cs,
671
          addr         => cpu_addr(0),
672
          rw           => cpu_rw,
673
          data_in      => cpu_data_out(7 downto 0),
674
          data_out     => kbd_data_out(7 downto 0),
675
          irq          => kbd_irq,
676
          kbd_clk      => ps2_clk,
677
          kbd_data     => ps2_dat
678
        );
679
 
680
----------------------------------------
681
--
682
-- Video Display Unit instantiation
683
--
684
----------------------------------------
685
my_vdu : vdu8
686
  generic map(
687
    VGA_CLK_FREQ           => VGA_CLK_FREQ, -- 25MHZ
688
    VGA_HOR_CHARS          => 80, -- CHARACTERS 25.6us
689
    VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS 0.32us
690
    VGA_HOR_FRONT_PORCH    => 16, -- PIXELS 0.64us
691
    VGA_HOR_SYNC           => 96, -- PIXELS 3.84us
692
    VGA_HOR_BACK_PORCH     => 48, -- PIXELS 1.92us
693
    VGA_VER_CHARS          => 25, -- CHARACTERS 12.8ms
694
    VGA_VER_CHAR_LINES     => 16, -- LINES 0.512ms
695
    VGA_VER_FRONT_PORCH    => 10, -- LINES 0.320ms
696
    VGA_VER_SYNC           => 2,  -- LINES 0.064ms
697
    VGA_VER_BACK_PORCH     => 34  -- LINES 1.088ms
698
  )
699
  port map(
700
 
701
    -- Control Registers
702
    vdu_clk       => cpu_clk,                                    -- 12.5 MHz System Clock in
703
    vdu_rst       => cpu_rst,
704
    vdu_cs        => vdu_cs,
705
    vdu_addr      => cpu_addr(2 downto 0),
706
    vdu_rw        => cpu_rw,
707
    vdu_data_in   => cpu_data_out,
708
    vdu_data_out  => vdu_data_out,
709
 
710
    -- vga port connections
711
    vga_clk       => vga_clk,                                    -- 25 MHz pixel clock
712
    vga_red_o     => vga_red,
713
    vga_green_o   => vga_green,
714
    vga_blue_o    => vga_blue,
715
    vga_hsync_o   => vga_hs,
716
    vga_vsync_o   => vga_vs
717
  );
718
 
719
----------------------------------------
720
--
721
-- Interrupt timer
722
--
723
----------------------------------------
724
 
725
my_timer : timer
726
        port map (
727
                clk        => cpu_clk,
728
                rst        => cpu_rst,
729
                cs         => tmr_cs,
730
                addr       => cpu_addr(0),
731
                rw         => cpu_rw,
732
                data_in    => cpu_data_out,
733
                data_out   => tmr_data_out,
734
                irq        => tmr_irq
735
        );
736
 
737
----------------------------------------
738
--
739
-- hardware break point (bus trap)
740
--
741
----------------------------------------
742
 
743
my_hw_bp : trap
744
        port map (
745
                clk        => cpu_clk,
746
                rst        => cpu_rst,
747
                cs         => hbp_cs,
748
                rw         => cpu_rw,
749
                vma        => cpu_vma,
750
                addr       => cpu_addr,
751
                data_in    => cpu_data_out,
752
                data_out   => hbp_data_out,
753
                irq        => hbp_irq
754
        );
755
 
756
----------------------------------------
757
--
758
-- Phase Locked Loop Clock divider
759
--
760
 
761
my_pll : pll
762
        PORT MAP
763
        (
764
                areset          => '0',
765
                inclk0          => clock_50,
766
                c0                      => sys_clk,
767
                c1                      => cpu_clk,
768
                c2                      => vga_clk,
769
                locked          => pll_locked
770
        );
771
 
772
----------------------------------------------------------------------
773
--
774
-- Process to decode memory map
775
--
776
----------------------------------------------------------------------
777
 
778
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
779
                                        dat_cs, dat_addr,
780
                                        rom_data_out,
781
                                        acia_data_out,
782
                                        kbd_data_out,
783
                                        vdu_data_out,
784
                                        hex_data_out,
785
                                        led_data_out,
786
                                        tmr_data_out,
787
                                        hbp_data_out,
788
                                        sram_data_out
789
                                        )
790
begin
791
      cpu_data_in <= (others=>'0');
792
      dat_cs      <= '0';
793
      rom_cs      <= '0';
794
      acia_cs     <= '0';
795
      kbd_cs      <= '0';
796
      vdu_cs      <= '0';
797
      hex_cs      <= '0';
798
      led_cs      <= '0';
799
      sram_cs     <= '0';
800
          tmr_cs      <= '0';
801
      hbp_cs      <= '0';
802
--          pb_cs       <= '0';
803
--      ide_cs      <= '0';
804
--      ether_cs    <= '0';
805
--          slot1_cs    <= '0';
806
--      slot2_cs    <= '0';
807
 
808
      if cpu_addr( 15 downto 8 ) = "11111111" then
809
            cpu_data_in <= rom_data_out;
810
        dat_cs      <= cpu_vma;              -- write DAT
811
        rom_cs      <= cpu_vma;              -- read  ROM
812
            --
813
                -- Sys09Bug Monitor ROM $F000 - $FFFF
814
                --
815
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
816
          if cpu_addr(11) = '1' then
817
            --
818
                    -- Monitor ROM $F800 - $FFFF
819
                    --
820
            cpu_data_in <= rom_data_out;
821
            rom_cs      <= cpu_vma;          -- read  ROM
822
          else
823
            --
824
                    -- SRAM $F000 - $F7FF
825
                    --
826
            cpu_data_in <= sram_data_out;
827
            sram_cs      <= cpu_vma;
828
          end if;
829
        --
830
                -- IO Devices $E000 - $EFFF
831
                --
832
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
833
                        case cpu_addr(11 downto 8) is
834
                        --
835
                        -- SWTPC peripherals from $E000 to $E0FF
836
                        --
837
                        when "0000" =>
838
                      case cpu_addr(7 downto 4) is
839
                          --
840
                          -- ACIA ($E000 - $E00F)
841
                          --
842
                          when "0000" =>
843
                        cpu_data_in <= acia_data_out;
844
                            acia_cs      <= cpu_vma;
845
 
846
                  --
847
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
848
              --
849
 
850
                          --
851
              -- Keyboard port ($E020 - $E02F)
852
                          --
853
                          when "0010" =>
854
                cpu_data_in <= kbd_data_out;
855
                            kbd_cs      <= cpu_vma;
856
 
857
              --
858
              -- VDU port ($E030 - $E03F)
859
                          --
860
                          when "0011" =>
861
                cpu_data_in <= vdu_data_out;
862
                            vdu_cs      <= cpu_vma;
863
 
864
              --
865
                          -- Reserved - SWTPc MP-T ($E040 - $E04F)
866
                          --
867
 
868
              --
869
              -- Reserved - Timer ($E050 - $E05F) (B5-X300)
870
                          --
871
                          when "0101" =>
872
                            cpu_data_in <= tmr_data_out;
873
                            tmr_cs      <= cpu_vma;
874
 
875
              --
876
              -- Reserved - hardware break point (Bus Trap) ($E060 - $E06F)
877
                          --
878
                          when "0110" =>
879
                            cpu_data_in <= hbp_data_out;
880
                            hbp_cs      <= cpu_vma;
881
 
882
              --
883
              -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
884
                          --
885
 
886
                          --
887
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
888
                          --
889
 
890
                          --
891
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
892
                          --
893
 
894
              --
895
                          -- Read Switched port ($E0A0 - $E0AF)
896
                          -- Write LEDS
897
                          --
898
                          when "1010" =>
899
                cpu_data_in <= led_data_out;
900
                            led_cs     <= cpu_vma;
901
 
902
              --
903
              -- 7 segment display port ($E0B0 - $E0BF)
904
                          --
905
                          when "1011" =>
906
                cpu_data_in <= hex_data_out;
907
                            hex_cs      <= cpu_vma;
908
 
909
 
910
                          when others => -- $EXC0 to $EXFF
911
                            null;
912
                      end case;
913
            --
914
                        --      $E100 to $EFFF reserved for future use
915
                        --
916
                when others =>
917
                          null;
918
         end case;
919
                --
920
                -- Everything else is RAM
921
                --
922
                else
923
                  cpu_data_in <= sram_data_out;
924
                  sram_cs      <= cpu_vma;
925
    end if;
926
end process;
927
 
928
 
929
--
930
-- 1M byte SRAM Control
931
-- Processes to read and write memory based on bus signals
932
--
933
sram_process: process( sys_clk, cpu_rst,
934
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
935
                                          dat_addr, sram_cs,
936
                      sram_ce,  sram_ub, sram_lb, sram_dq,
937
                                          sram_we,  sram_oe )
938
begin
939
    --
940
        -- Clock Hold on rising edge
941
        --
942
    if( sys_clk'event and sys_clk='1' ) then
943
                --
944
                -- sram_hold signal helps 
945
                --
946
                if( cpu_rst = '1' ) then
947
                        sram_we   <= '0';
948
                        sram_oe   <= '0';
949
                else
950
                        if (sram_cs = '1') and (sram_we = '0') and (sram_oe = '0') then
951
                                sram_we   <= not cpu_rw;
952
                                sram_oe   <=     cpu_rw;
953
                        else
954
                                sram_we   <= '0';
955
                                sram_oe   <= '0';
956
                        end if;
957
                end if;
958
    end if;
959
 
960
        sram_we_n  <= not sram_we;
961
        sram_oe_n  <= not sram_oe;
962
 
963
    sram_ce   <= sram_cs;
964
    sram_ub   <= not cpu_addr(0);
965
    sram_lb   <= cpu_addr(0);
966
    sram_ce_n <= not sram_ce;
967
    sram_ub_n <= not sram_ub;
968
    sram_lb_n <= not sram_lb;
969
 
970
        sram_addr(17 downto 11) <= dat_addr(6 downto 0);
971
        sram_addr(10 downto 0) <= cpu_addr(11 downto 1);
972
 
973
    if sram_we = '1' and sram_ce = '1' and sram_lb = '1' then
974
                sram_dq(7 downto 0) <= cpu_data_out;
975
        else
976
        sram_dq(7 downto 0)  <= "ZZZZZZZZ";
977
        end if;
978
 
979
    if sram_we = '1' and sram_ce = '1' and sram_ub = '1' then
980
                sram_dq(15 downto 8) <= cpu_data_out;
981
        else
982
        sram_dq(15 downto 8)  <= "ZZZZZZZZ";
983
        end if;
984
 
985
        if cpu_addr(0) = '0' then
986
        sram_data_out <= sram_dq(15 downto 8);
987
        else
988
        sram_data_out <= sram_dq(7 downto 0);
989
    end if;
990
 
991
end process;
992
 
993
--
994
-- LEDS output register
995
--
996
led_output : process( cpu_clk, cpu_rst, led_cs, cpu_rw, cpu_addr, cpu_data_out, sw )
997
begin
998
        if cpu_clk'event and cpu_clk='0' then
999
                if cpu_rst = '1' then
1000
                        ledr <= (others=>'0');
1001
                        ledg <= (others=>'0');
1002
                else
1003
                        if led_cs = '1' and cpu_rw = '0' then
1004
                                if cpu_addr(0) = '0' then
1005
                                        ledr(7 downto 0) <= cpu_data_out;
1006
                                else
1007
                                        ledg(7 downto 0) <= cpu_data_out;
1008
                                end if;
1009
                        end if;
1010
                end if;
1011
        end if;
1012
        led_data_out <= sw(7 downto 0);
1013
end process;
1014
 
1015
--
1016
-- 7 segment HEX display output register
1017
--
1018
hex_output : process( cpu_clk, cpu_rst, hex_cs, cpu_rw, cpu_addr, cpu_data_out,
1019
                                                hex0_reg, hex1_reg, hex2_reg, hex3_reg )
1020
begin
1021
        if cpu_clk'event and cpu_clk='0' then
1022
                if cpu_rst = '1' then
1023
                        hex0_reg <= (others=>'0');
1024
                        hex1_reg <= (others=>'0');
1025
                        hex2_reg <= (others=>'0');
1026
                        hex3_reg <= (others=>'0');
1027
                else
1028
                        if      hex_cs = '1' and cpu_rw = '0' then
1029
                                case cpu_addr(1 downto 0) is
1030
                                when "00" =>
1031
                                        hex0_reg <= cpu_data_out;
1032
                                when "01" =>
1033
                                        hex1_reg <= cpu_data_out;
1034
                                when "10" =>
1035
                                        hex2_reg <= cpu_data_out;
1036
                                when "11" =>
1037
                                        hex3_reg <= cpu_data_out;
1038
                                end case;
1039
                        end if;
1040
                end if;
1041
        end if;
1042
 
1043
        case cpu_addr(1 downto 0) is
1044
        when "00" =>
1045
                hex_data_out <= hex0_reg;
1046
        when "01" =>
1047
                hex_data_out <= hex1_reg;
1048
        when "10" =>
1049
                hex_data_out <= hex2_reg;
1050
        when "11" =>
1051
                hex_data_out <= hex3_reg;
1052
        end case;
1053
 
1054
    hex0 <= not hex0_reg(6 downto 0);
1055
    hex1 <= not hex1_reg(6 downto 0);
1056
    hex2 <= not hex2_reg(6 downto 0);
1057
    hex3 <= not hex3_reg(6 downto 0);
1058
 
1059
end process;
1060
 
1061
--
1062
-- Interrupts and other bus control signals
1063
--
1064
interrupts : process(   key, pll_locked,
1065
                                                acia_irq, kbd_irq, hbp_irq, tmr_irq )
1066
begin
1067
        cpu_rst    <= not key(0); -- CPU reset is active high
1068
        cpu_firq   <= kbd_irq;
1069
        cpu_nmi    <= (not key(1)) or hbp_irq;
1070
        cpu_irq    <= acia_irq or tmr_irq;
1071
        cpu_halt   <= '0';
1072
        cpu_hold   <= '0';
1073
end process;
1074
 
1075
--
1076
-- ACIA pin assignments
1077
--
1078
acia_assignments : process( uart_rxd, acia_txd )
1079
begin
1080
        acia_dcd_n <= '0';
1081
        acia_cts_n <= '0';
1082
        acia_rxd   <= uart_rxd;
1083
        uart_txd   <= acia_txd;
1084
end process;
1085
 
1086
--
1087
-- assign vga colour bits to single bit RGB output of VDU
1088
--
1089
vga_assignments : process( vga_red, vga_green, vga_blue )
1090
begin
1091
        vga_r <= (others=>vga_red);
1092
        vga_g <= (others=>vga_green);
1093
        vga_b <= (others=>vga_blue);
1094
end process;
1095
 
1096
--
1097
-- assign dram signals
1098
--
1099
dram_assign : process( all )
1100
begin
1101
        dram_addr  <= (others=>'0');
1102
        dram_cs_n  <= '1';
1103
        dram_ras_n <= '1';
1104
        dram_cas_n <= '1';
1105
        dram_we_n  <= '1';
1106
end process;
1107
 
1108
--
1109
-- assign flash memory signals
1110
--
1111
flash_assign : process( all )
1112
begin
1113
        fl_addr    <= (others=>'0');
1114
        fl_oe_n    <= '1';
1115
        fl_we_n    <= '1';
1116
 
1117
end process;
1118
 
1119
end my_computer; --===================== End of architecture =======================--
1120
 

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