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[/] [System09/] [trunk/] [rtl/] [System09_Terasic_DE1/] [System09_Terasic_DE1.vhd.bak] - Blame information for rev 120

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1 117 dilbert57
--=============================================================================--
2
--                                                                             --
3
--  System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
4
--                                                                             --
5
--=============================================================================--
6
--
7
--
8
-- File name      : System09_Terasic_DE1.vhd
9
--
10
-- Entity name    : System09
11
--
12
-- Purpose        : Top level file for 6809 compatible system on a chip
13
--                  Designed with Alera EP2C20 Cyclone 2 FPGA.
14
--                  Implemented with Terasic DE1 FPGA board,
15
--
16
-- Dependencies   : ieee.Std_Logic_1164
17
--                  ieee.std_logic_unsigned
18
--                  ieee.std_logic_arith
19
--                  ieee.numeric_std
20
--
21
-- Uses           : cpu09         (..\VHDL\cpu09.vhd)              CPU core
22
--                  dat_ram       (..\VHDL\datram.vhd)             Dynamic Address Translation
23
--                  mon_rom       (..\Cyclone2\mon_rom.vhd)        Monitor ROM
24
--                  acia6850      (..\VHDL\acia6850.vhd)           ACIA (UART)
25
--                  ACIA_Clock    (..\VHDL\ACIA_Clock.vhd)         ACIA Baud Rate Clock Divider
26
--                  keyboard      (..\VHDL\keyboard.vhd)           PS/2 Keyboard register interface
27
--                  ps2_keyboard  (..\VHDL\ps2_keyboard.vhd)       PS/2 Keyboard interface logic
28
--                  keymap_rom    (..\Cyclone2\keymap_rom.vhd)     PS/2 Keyboard key code look up table
29
--                  vdu8          (..\VHDL\vdu8.vhd)                   Video Display Unit
30
--                                (..\Cyclone2\char_rom.vhd)       Character Generator ROM (B16_RAM)
31
--                                (..\Cyclone2\ram_2k.vhd)         Text & Attribute RAM Buffer
32
--                  seven_segment (..\VHDL\SevenSegment.vhd)       Seven Segment Display
33
--
34
-- Author         : John E. Kent
35
--                  dilbert57@opencores.org
36
--
37
-- Memory Map     :
38
--
39
-- $0000 - $DFFF System RAM (512K Mapped via DAT)
40
-- $E000 - ACIA (SWTPc)
41
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
42
-- $E020 - Keyboard
43
-- $E030 - VDU
44
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
45
-- $E050 - Timer
46
-- $E060 - Reserved for Bus Trap (Hardware Breakpoint Logic)
47
-- $E070 - Reserved for Trace Buffer
48
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
49
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
50
-- $E0A0 - Switches in / LEDS out
51
-- $E0B0 - 7 Segment hex display
52
-- $E0C0 - Reserved
53
-- $E0D0 - Reserved
54
-- $E0E0 - Reserved
55
-- $E0F0 - Reserved
56
-- $E100 - $E13F Reserved IDE / Compact Flash Card
57
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
58
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
59
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
60
-- $E200 - $EFFF Reserved for Future I/O
61
-- $F000 - $F7FF RAM for Sys09bug monitor extensions
62
-- $F800 - $FFFF Sys09bug ROM (Read only)
63
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
64
--
65
--
66
--  Copyright (C) 2003 - 2010 John Kent
67
--
68
--  This program is free software: you can redistribute it and/or modify
69
--  it under the terms of the GNU General Public License as published by
70
--  the Free Software Foundation, either version 3 of the License, or
71
--  (at your option) any later version.
72
--
73
--  This program is distributed in the hope that it will be useful,
74
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
75
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
76
--  GNU General Public License for more details.
77
--
78
--  You should have received a copy of the GNU General Public License
79
--  along with this program.  If not, see .
80
--
81
--===========================================================================--
82
--
83
--                              Revision History:
84
--
85
--===========================================================================--
86
--
87
-- Version 0.1 - 20 March 2003
88
-- Version 0.2 - 30 March 2003
89
-- Version 0.3 - 29 April 2003
90
-- Version 0.4 - 29 June 2003
91
--
92
-- Version 0.5 - 19 July 2003
93
-- prints out "Hello World"
94
--
95
-- Version 0.6 - 5 September 2003
96
-- Runs SBUG
97
--
98
-- Version 1.0- 6 Sep 2003 - John Kent
99
-- Inverted sys_clk
100
-- Initial release to Open Cores
101
--
102
-- Version 1.1 - 17 Jan 2004 - John Kent
103
-- Updated miniUart.
104
--
105
-- Version 1.2 - 25 Jan 2004 - John Kent
106
-- removed signals "test_alu" and "test_cc"
107
-- Trap hardware re-instated.
108
--
109
-- Version 1.3 - 11 Feb 2004 - John Kent
110
-- Designed forked off to produce System09_VDU
111
-- Added VDU component
112
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
113
-- UART Runs at 57.6 Kbps
114
--
115
-- Version 2.0 - 2 September 2004 - John Kent
116
-- ported to Digilent Xilinx Spartan3 starter board
117
--      removed Compaact Flash and Trap Logic.
118
-- Replaced SBUG with KBug9s
119
--
120
-- Version 2.1 - 21 November 2006 - John Kent
121
-- Replaced KBug9s with Sys09bug 1.0
122
-- Inverted bottom nybble of DAT register outputs
123
-- Changed ROM & I/O decoding to be compatible with SWTPc
124
-- Upped the serial baud rate to 115.2 KBd
125
-- added multiple global clock buffers
126
-- (Uart would not operate correctly)
127
--
128
-- Version 2.2 - 22 December 2006 - John Kent
129
-- Increased CPU clock from 12.5MHz to 25 MHz.
130
-- Removed some of the global clock buffers
131
-- Added LED output register
132
-- Changed address decoding to 4K Blocks
133
--
134
-- Version 2.3 - 1 June 2007 - John Kent
135
-- Updated VDU & ACIA
136
-- Changed decoding for Sys09Bug
137
--
138
-- Version 2.4 - 31 January 2008 - John Kent
139
--      ACIA does not appear to work.
140
-- Made RAM OE and WE strobes synchonous to sys_clk
141
--
142
-- Version 2.5 - 23rd Feburary 2009 - John Kent
143
-- Implemented recommendation to remove vga_clk clock buffer
144
--
145
-- Version 2.6 - 5th september 2010 - John Kent
146
-- Renamed ACIA_6850 to acia6850
147
-- Updated generics on VDU8
148
-- Shortened the "keyboard" label
149
-- Fixed up address label on CPU09
150
-- Removed Flex RAM
151
-- Map RAM at $F000 - $F7FF
152
--
153
-- Vesrion 2.7 - 22nd October 2010 - John Kent
154
-- Ported from Digilent XC3S200 Starter to
155
-- Terasic EP2C20 DE1 board.
156
--
157
--===========================================================================--
158
library ieee;
159
   use ieee.std_logic_1164.all;
160
   use IEEE.STD_LOGIC_ARITH.ALL;
161
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
162
   use ieee.numeric_std.all;
163
 
164
entity System09_Terasic_DE1 is
165
  port(
166
        -- clocks
167
        clock_24    : in    std_logic_vector(1 downto 0);
168
        clock_27    : in    std_logic;
169
    clock_50    : in    std_logic;  -- System Clock input
170
    ext_clock   : in    std_logic;
171
 
172
    -- push button keys
173
        key         : in    std_logic_vector(3 downto 0);  -- RST, NMI
174
 
175
    -- SRAM interface signals
176
 
177
    sram_ce_n   : out   std_logic;
178
    sram_we_n   : out   std_logic;
179
    sram_oe_n   : out   std_logic;
180
        sram_ub_n   : out   std_logic;
181
        sram_lb_n   : out   std_logic;
182
    sram_addr   : out   std_logic_vector(17 downto 0);
183
    sram_dq     : inout std_logic_vector(15 downto 0);
184
 
185
        -- PS/2 Keyboard
186
        ps2_clk     : inout Std_logic;
187
        ps2_dat     : inout Std_Logic;
188
 
189
        -- ACIA/UART Interface
190
    uart_rxd    : in  Std_Logic;
191
        uart_txd    : out Std_Logic;
192
 
193
        -- CRTC output signals
194
    vga_r       : out std_logic_vector(3 downto 0);
195
    vga_g       : out std_logic_vector(3 downto 0);
196
    vga_b       : out std_logic_vector(3 downto 0);
197
    vga_hs      : out Std_Logic;
198
        vga_vs      : out Std_Logic;
199
 
200
        -- LEDS & Switches
201
        ledg        : out std_logic_vector(7 downto 0);
202
        ledr        : out std_logic_vector(9 downto 0);
203
        sw          : in  std_logic_vector(9 downto 0);
204
 
205
        -- hexadecimal display
206
        hex0        : out std_logic_vector(6 downto 0);
207
        hex1        : out std_logic_vector(6 downto 0);
208
        hex2        : out std_logic_vector(6 downto 0);
209
        hex3        : out std_logic_vector(6 downto 0);
210
 
211
        -- gnereal purpose I/O
212
        gpio_0      : in  std_logic_vector(35 downto 0);
213
        gpio_1      : in  std_logic_vector(35 downto 0);
214
 
215
        -- i2c interface
216
        i2c_sclk    : in std_logic;
217
        i2c_sdat    : in std_logic;
218
 
219
        -- audio codec
220
        aud_adcdat  : in std_logic;
221
        aud_adclrck : in std_logic;
222
        aud_bclk    : in std_logic;
223
        aud_dacdat  : in std_logic;
224
        aud_daclrck : in std_logic;
225
        aud_xck     : in std_logic;
226
 
227
        -- dram
228
        dram_addr  : out std_logic_vector(11 downto 0);
229
        dram_dq    : in  std_logic_vector(15 downto 0);
230
        dram_cs_n  : out std_logic;
231
        dram_ba_0  : in std_logic;
232
        dram_ba_1  : in std_logic;
233
        dram_ldqm  : in std_logic;
234
        dram_udqm  : in std_logic;
235
        dram_ras_n : out std_logic;
236
        dram_cas_n : out std_logic;
237
        dram_we_n  : out std_logic;
238
        dram_cke   : in std_logic;
239
        dram_clk   : in std_logic;
240
 
241
         -- Flash memory
242
        fl_addr    : out std_logic_vector(21 downto 0);
243
        fl_dq      : in  std_logic_vector(7 downto 0);
244
        fl_rst_n   : in  std_logic;
245
        fl_oe_n    : out std_logic;
246
        fl_we_n    : out std_logic;
247
 
248
        -- JTAG
249
        tck        : in std_logic;
250
        tcs        : in std_logic;
251
        tdi        : in std_logic;
252
        tdo        : in std_logic
253
        );
254
end System09_Terasic_DE1;
255
 
256
-------------------------------------------------------------------------------
257
-- Architecture for System09
258
-------------------------------------------------------------------------------
259
architecture my_computer of System09_Terasic_DE1 is
260
  -----------------------------------------------------------------------------
261
  -- constants
262
  -----------------------------------------------------------------------------
263
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
264
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
265
  constant CPU_CLK_FREQ  : integer := 25000000;  -- CPU Clock
266
  constant BAUD_Rate     : integer := 57600;      -- Baud Rate
267
  constant ACIA_CLK_FREQ : integer := BAUD_Rate * 16;
268
 
269
  type hold_state_type is ( hold_release_state, hold_request_state );
270
 
271
  -----------------------------------------------------------------------------
272
  -- Signals
273
  -----------------------------------------------------------------------------
274
 
275
  signal sys_clk       : std_logic;
276
  signal vga_clk       : std_logic;
277
  signal pll_locked    : std_logic;
278
 
279
  -- CPU Interface signals
280
  signal cpu_clk       : std_logic;
281
  signal cpu_rst       : std_logic;
282
  signal cpu_rw        : std_logic;
283
  signal cpu_vma       : std_logic;
284
  signal cpu_halt      : std_logic;
285
  signal cpu_hold      : std_logic;
286
  signal cpu_firq      : std_logic;
287
  signal cpu_irq       : std_logic;
288
  signal cpu_nmi       : std_logic;
289
  signal cpu_addr      : std_logic_vector(15 downto 0);
290
  signal cpu_data_in   : std_logic_vector(7 downto 0);
291
  signal cpu_data_out  : std_logic_vector(7 downto 0);
292
 
293
  -- Dynamic Address Translation
294
  signal dat_cs        : std_logic;
295
  signal dat_addr      : std_logic_vector(7 downto 0);
296
 
297
  -- BOOT ROM
298
  signal rom_cs        : Std_logic;
299
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
300
 
301
  -- ACIA Interface signals
302
  signal acia_clk      : std_logic;
303
  signal acia_cs       : Std_Logic;
304
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
305
  signal acia_irq      : Std_Logic;
306
  signal acia_rxd      : Std_Logic;
307
  signal acia_txd      : Std_Logic;
308
  signal acia_dcd_n    : Std_Logic;
309
--  signal acia_rts_n    : Std_Logic;
310
  signal acia_cts_n    : Std_Logic;
311
 
312
  -- keyboard port
313
  signal kbd_data_out : std_logic_vector(7 downto 0);
314
  signal kbd_cs       : std_logic;
315
  signal kbd_irq      : std_logic;
316
 
317
  -- LEDs
318
  signal leds_data_out : std_logic_vector(7 downto 0);
319
  signal leds_cs       : std_logic;
320
 
321
  -- Video Display Unit
322
  signal vdu_cs       : std_logic;
323
  signal vdu_data_out : std_logic_vector(7 downto 0);
324
  signal vga_red      : std_logic;
325
  signal vga_green    : std_logic;
326
  signal vga_blue     : std_logic;
327
 
328
  -- LEDs
329
  signal led_cs       : std_logic;
330
  signal led_data_out : std_logic_vector(7 downto 0);
331
 
332
  -- 7 Segment Display
333
  signal hex_cs       : std_logic;
334
  signal hex_data_out : std_logic_vector(7 downto 0);
335
  signal hex0_reg     : std_logic_vector(7 downto 0);
336
  signal hex1_reg     : std_logic_vector(7 downto 0);
337
  signal hex2_reg     : std_logic_vector(7 downto 0);
338
  signal hex3_reg     : std_logic_vector(7 downto 0);
339
 
340
  -- interrupt timer
341
  signal tmr_data_out : std_logic_vector(7 downto 0);
342
  signal tmr_cs       : std_logic;
343
  signal tmr_irq      : std_logic;
344
 
345
  -- hardware break point (trap)
346
  signal hbp_data_out : std_logic_vector(7 downto 0);
347
  signal hbp_cs       : std_logic;
348
  signal hbp_irq      : std_logic;
349
 
350
  -- RAM
351
  signal sram_cs       : std_logic; -- memory chip select
352
  signal sram_data_out : std_logic_vector(7 downto 0);
353
  signal sram_ce       : std_logic;
354
  signal sram_ub       : std_logic;
355
  signal sram_lb       : std_logic;
356
  signal sram_we       : std_logic;
357
  signal sram_oe       : std_logic;
358
 
359
  -- System Clock Prescaler
360
  signal clk_count     : std_logic;
361
 
362
-----------------------------------------------------------------
363
--
364
-- CPU09 CPU core
365
--
366
-----------------------------------------------------------------
367
 
368
component cpu09
369
  port (
370
         clk      :     in  std_logic;
371
    rst      : in  std_logic;
372
    vma      :  out std_logic;
373
    addr     : out std_logic_vector(15 downto 0);
374
    rw       :  out std_logic;
375
    data_in  : in        std_logic_vector(7 downto 0);
376
         data_out : out std_logic_vector(7 downto 0);
377
         halt     : in  std_logic;
378
         hold     : in  std_logic;
379
         irq      : in  std_logic;
380
         nmi      : in  std_logic;
381
         firq     : in  std_logic
382
  );
383
end component;
384
 
385
----------------------------------------
386
--
387
-- Dynamic Address Translation Registers
388
--
389
----------------------------------------
390
component dat_ram
391
        port (
392
                clk      : in  std_logic;
393
                rst      : in  std_logic;
394
                cs       : in  std_logic;
395
                rw       : in  std_logic;
396
                addr_lo  : in  std_logic_vector(3 downto 0);
397
                addr_hi  : in  std_logic_vector(3 downto 0);
398
                data_in  : in  std_logic_vector(7 downto 0);
399
                data_out : out std_logic_vector(7 downto 0)
400
        );
401
end component;
402
 
403
----------------------------------------
404
--
405
-- 4KByte Block RAM Monitor ROM
406
--
407
----------------------------------------
408
component mon_rom
409
  Port (
410
    clk      : in  std_logic;
411
    rst      : in  std_logic;
412
    cs       : in  std_logic;
413
    rw       : in  std_logic;
414
    addr     : in  std_logic_vector (10 downto 0);
415
    data_in  : in  std_logic_vector (7 downto 0);
416
    data_out : out std_logic_vector (7 downto 0)
417
    );
418
end component;
419
 
420
-----------------------------------------------------------------
421
--
422
-- 6850 ACIA
423
--
424
-----------------------------------------------------------------
425
 
426
component acia6850
427
  port (
428
    clk      : in  Std_Logic;  -- System Clock
429
    rst      : in  Std_Logic;  -- Reset input (active high)
430
    cs       : in  Std_Logic;  -- ACIA Chip Select
431
    rw       : in  Std_Logic;  -- Read / Not Write
432
    addr     : in  Std_Logic;  -- Register Select
433
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In
434
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
435
    irq      : out Std_Logic;  -- Interrupt
436
    RxC      : in  Std_Logic;  -- Receive Baud Clock
437
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
438
    RxD      : in  Std_Logic;  -- Receive Data
439
    TxD      : out Std_Logic;  -- Transmit Data
440
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
441
    CTS_n    : in  Std_Logic;  -- Clear To Send
442
    RTS_n    : out Std_Logic   -- Request To send
443
  );
444
end component;
445
 
446
-----------------------------------------------------------------
447
--
448
-- ACIA Clock divider
449
--
450
-----------------------------------------------------------------
451
 
452
component ACIA_Clock
453
  generic (
454
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
455
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
456
  );
457
  port (
458
     clk      : in  Std_Logic;  -- System Clock Input
459
          acia_clk : out Std_logic   -- ACIA Clock output
460
  );
461
end component;
462
 
463
----------------------------------------
464
--
465
-- PS/2 Keyboard
466
--
467
----------------------------------------
468
 
469
component keyboard
470
  generic(
471
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
472
  );
473
  port(
474
    clk             : in    std_logic;
475
    rst             : in    std_logic;
476
    cs              : in    std_logic;
477
    addr            : in    std_logic;
478
    rw              : in    std_logic;
479
    data_in         : in    std_logic_vector(7 downto 0);
480
    data_out        : out   std_logic_vector(7 downto 0);
481
    irq             : out   std_logic;
482
    kbd_clk         : inout std_logic;
483
    kbd_data        : inout std_logic
484
  );
485
end component;
486
 
487
----------------------------------------
488
--
489
-- Video Display Unit.
490
--
491
----------------------------------------
492
component vdu8
493
  generic(
494
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
495
         VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
496
         VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
497
         VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
498
         VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
499
         VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
500
         VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
501
         VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
502
         VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
503
         VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
504
         VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
505
  );
506
  port(
507
    -- control register interface
508
    vdu_clk      : in  std_logic;        -- CPU Clock - 12.5MHz
509
    vdu_rst      : in  std_logic;
510
    vdu_cs       : in  std_logic;
511
    vdu_rw       : in  std_logic;
512
    vdu_addr     : in  std_logic_vector(2 downto 0);
513
    vdu_data_in  : in  std_logic_vector(7 downto 0);
514
    vdu_data_out : out std_logic_vector(7 downto 0);
515
 
516
    -- vga port connections
517
    vga_clk      : in  std_logic;       -- VGA Pixel Clock - 25 MHz
518
    vga_red_o    : out std_logic;
519
    vga_green_o  : out std_logic;
520
    vga_blue_o   : out std_logic;
521
    vga_hsync_o  : out std_logic;
522
    vga_vsync_o  : out std_logic
523
  );
524
end component;
525
 
526
----------------------------------------
527
--
528
-- Interrupt timer
529
--
530
----------------------------------------
531
 
532
component timer is
533
        port (
534
                clk        : in  std_logic;
535
                rst        : in  std_logic;
536
                cs         : in  std_logic;
537
                addr       : in  std_logic;
538
                rw         : in  std_logic;
539
                data_in    : in  std_logic_vector(7 downto 0);
540
                data_out   : out std_logic_vector(7 downto 0);
541
                irq        : out std_logic
542
        );
543
end component;
544
 
545
----------------------------------------
546
--
547
-- hardware break point (bus trap)
548
--
549
----------------------------------------
550
 
551
component trap is
552
        port (
553
                clk        : in  std_logic;
554
                rst        : in  std_logic;
555
                cs         : in  std_logic;
556
                rw         : in  std_logic;
557
                vma        : in  std_logic;
558
                addr       : in  std_logic_vector(15 downto 0);
559
                data_in    : in  std_logic_vector(7 downto 0);
560
                data_out   : out std_logic_vector(7 downto 0);
561
                irq        : out std_logic
562
        );
563
end component;
564
 
565
 
566
component pll IS
567
        PORT
568
        (
569
                areset          : IN STD_LOGIC  := '0';
570
                inclk0          : IN STD_LOGIC  := '0';
571
                c0                      : OUT STD_LOGIC ;
572
                c1                      : OUT STD_LOGIC ;
573
                c2                      : OUT STD_LOGIC ;
574
                locked          : OUT STD_LOGIC
575
        );
576
END component;
577
 
578
begin
579
  -----------------------------------------------------------------------------
580
  -- Instantiation of internal components
581
  -----------------------------------------------------------------------------
582
 
583
my_cpu : cpu09  port map (
584
         clk         => cpu_clk,
585
    rst       => cpu_rst,
586
    vma       => cpu_vma,
587
    addr      => cpu_addr(15 downto 0),
588
    rw       => cpu_rw,
589
    data_in   => cpu_data_in,
590
         data_out  => cpu_data_out,
591
         halt      => cpu_halt,
592
         hold      => cpu_hold,
593
         irq       => cpu_irq,
594
         nmi       => cpu_nmi,
595
         firq      => cpu_firq
596
    );
597
 
598
my_dat : dat_ram port map (
599
    clk       => cpu_clk,
600
        rst       => cpu_rst,
601
        cs        => dat_cs,
602
        addr_hi   => cpu_addr(15 downto 12),
603
        addr_lo   => cpu_addr(3 downto 0),
604
        rw        => cpu_rw,
605
        data_in   => cpu_data_out,
606
        data_out  => dat_addr(7 downto 0)
607
         );
608
 
609
my_rom : mon_rom port map (
610
    clk       => cpu_clk,
611
    rst       => cpu_rst,
612
        cs        => rom_cs,
613
        rw        => '1',
614
    addr      => cpu_addr(10 downto 0),
615
    data_in   => cpu_data_out,
616
    data_out  => rom_data_out
617
    );
618
 
619
my_acia  : acia6850 port map (
620
        clk           => cpu_clk,
621
        rst       => cpu_rst,
622
    cs        => acia_cs,
623
    addr      => cpu_addr(0),
624
        rw        => cpu_rw,
625
        data_in   => cpu_data_out,
626
        data_out  => acia_data_out,
627
    irq       => acia_irq,
628
        RxC       => acia_clk,
629
        TxC       => acia_clk,
630
        RxD       => acia_rxd,
631
        TxD       => acia_txd,
632
        DCD_n     => acia_dcd_n,
633
        CTS_n     => acia_cts_n,
634
        RTS_n     => open
635
    );
636
 
637
 
638
----------------------------------------
639
--
640
-- ACIA Clock
641
--
642
----------------------------------------
643
my_ACIA_Clock : ACIA_Clock
644
  generic map(
645
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
646
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
647
  )
648
  port map(
649
    clk        => sys_clk,
650
    acia_clk   => acia_clk
651
  );
652
 
653
 
654
----------------------------------------
655
--
656
-- PS/2 Keyboard Interface
657
--
658
----------------------------------------
659
my_keyboard : keyboard
660
   generic map (
661
          KBD_CLK_FREQ => CPU_CLK_FREQ
662
        )
663
   port map(
664
          clk          => cpu_clk,
665
          rst          => cpu_rst,
666
          cs           => kbd_cs,
667
          addr         => cpu_addr(0),
668
          rw           => cpu_rw,
669
          data_in      => cpu_data_out(7 downto 0),
670
          data_out     => kbd_data_out(7 downto 0),
671
          irq          => kbd_irq,
672
          kbd_clk      => ps2_clk,
673
          kbd_data     => ps2_dat
674
        );
675
 
676
----------------------------------------
677
--
678
-- Video Display Unit instantiation
679
--
680
----------------------------------------
681
my_vdu : vdu8
682
  generic map(
683
    VGA_CLK_FREQ           => VGA_CLK_FREQ, -- 25MHZ
684
    VGA_HOR_CHARS          => 80, -- CHARACTERS 25.6us
685
    VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS 0.32us
686
    VGA_HOR_FRONT_PORCH    => 16, -- PIXELS 0.64us
687
    VGA_HOR_SYNC           => 96, -- PIXELS 3.84us
688
    VGA_HOR_BACK_PORCH     => 48, -- PIXELS 1.92us
689
    VGA_VER_CHARS          => 25, -- CHARACTERS 12.8ms
690
    VGA_VER_CHAR_LINES     => 16, -- LINES 0.512ms
691
    VGA_VER_FRONT_PORCH    => 10, -- LINES 0.320ms
692
    VGA_VER_SYNC           => 2,  -- LINES 0.064ms
693
    VGA_VER_BACK_PORCH     => 34  -- LINES 1.088ms
694
  )
695
  port map(
696
 
697
    -- Control Registers
698
    vdu_clk       => cpu_clk,                                    -- 12.5 MHz System Clock in
699
    vdu_rst       => cpu_rst,
700
    vdu_cs        => vdu_cs,
701
    vdu_addr      => cpu_addr(2 downto 0),
702
    vdu_rw        => cpu_rw,
703
    vdu_data_in   => cpu_data_out,
704
    vdu_data_out  => vdu_data_out,
705
 
706
    -- vga port connections
707
    vga_clk       => vga_clk,                                    -- 25 MHz pixel clock
708
    vga_red_o     => vga_red,
709
    vga_green_o   => vga_green,
710
    vga_blue_o    => vga_blue,
711
    vga_hsync_o   => vga_hs,
712
    vga_vsync_o   => vga_vs
713
  );
714
 
715
----------------------------------------
716
--
717
-- Interrupt timer
718
--
719
----------------------------------------
720
 
721
my_timer : timer
722
        port map (
723
                clk        => cpu_clk,
724
                rst        => cpu_rst,
725
                cs         => tmr_cs,
726
                addr       => cpu_addr(0),
727
                rw         => cpu_rw,
728
                data_in    => cpu_data_out,
729
                data_out   => tmr_data_out,
730
                irq        => tmr_irq
731
        );
732
 
733
----------------------------------------
734
--
735
-- hardware break point (bus trap)
736
--
737
----------------------------------------
738
 
739
my_hw_bp : trap
740
        port map (
741
                clk        => cpu_clk,
742
                rst        => cpu_rst,
743
                cs         => hbp_cs,
744
                rw         => cpu_rw,
745
                vma        => cpu_vma,
746
                addr       => cpu_addr,
747
                data_in    => cpu_data_out,
748
                data_out   => hbp_data_out,
749
                irq        => hbp_irq
750
        );
751
 
752
----------------------------------------
753
--
754
-- Phase Locked Loop Clock divider
755
--
756
 
757
my_pll : pll
758
        PORT MAP
759
        (
760
                areset          => '0',
761
                inclk0          => clock_50,
762
                c0                      => sys_clk,
763
                c1                      => cpu_clk,
764
                c2                      => vga_clk,
765
                locked          => pll_locked
766
        );
767
 
768
----------------------------------------------------------------------
769
--
770
-- Process to decode memory map
771
--
772
----------------------------------------------------------------------
773
 
774
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
775
                                        dat_cs, dat_addr,
776
                                        rom_data_out,
777
                                        acia_data_out,
778
                                        kbd_data_out,
779
                                        vdu_data_out,
780
                                        hex_data_out,
781
                                        led_data_out,
782
                                        tmr_data_out,
783
                                        hbp_data_out,
784
                                        sram_data_out
785
                                        )
786
begin
787
      cpu_data_in <= (others=>'0');
788
      dat_cs      <= '0';
789
      rom_cs      <= '0';
790
      acia_cs     <= '0';
791
      kbd_cs      <= '0';
792
      vdu_cs      <= '0';
793
      hex_cs      <= '0';
794
      led_cs      <= '0';
795
      sram_cs     <= '0';
796
          tmr_cs      <= '0';
797
      hbp_cs      <= '0';
798
--          pb_cs       <= '0';
799
--      ide_cs      <= '0';
800
--      ether_cs    <= '0';
801
--          slot1_cs    <= '0';
802
--      slot2_cs    <= '0';
803
 
804
      if cpu_addr( 15 downto 8 ) = "11111111" then
805
            cpu_data_in <= rom_data_out;
806
        dat_cs      <= cpu_vma;              -- write DAT
807
        rom_cs      <= cpu_vma;              -- read  ROM
808
            --
809
                -- Sys09Bug Monitor ROM $F000 - $FFFF
810
                --
811
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
812
          if cpu_addr(11) = '1' then
813
            --
814
                    -- Monitor ROM $F800 - $FFFF
815
                    --
816
            cpu_data_in <= rom_data_out;
817
            rom_cs      <= cpu_vma;          -- read  ROM
818
          else
819
            --
820
                    -- SRAM $F000 - $F7FF
821
                    --
822
            cpu_data_in <= sram_data_out;
823
            sram_cs      <= cpu_vma;
824
          end if;
825
        --
826
                -- IO Devices $E000 - $EFFF
827
                --
828
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
829
                        case cpu_addr(11 downto 8) is
830
                        --
831
                        -- SWTPC peripherals from $E000 to $E0FF
832
                        --
833
                        when "0000" =>
834
                      case cpu_addr(7 downto 4) is
835
                          --
836
                          -- ACIA ($E000 - $E00F)
837
                          --
838
                          when "0000" =>
839
                        cpu_data_in <= acia_data_out;
840
                            acia_cs      <= cpu_vma;
841
 
842
                  --
843
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
844
              --
845
 
846
                          --
847
              -- Keyboard port ($E020 - $E02F)
848
                          --
849
                          when "0010" =>
850
                cpu_data_in <= kbd_data_out;
851
                            kbd_cs      <= cpu_vma;
852
 
853
              --
854
              -- VDU port ($E030 - $E03F)
855
                          --
856
                          when "0011" =>
857
                cpu_data_in <= vdu_data_out;
858
                            vdu_cs      <= cpu_vma;
859
 
860
              --
861
                          -- Reserved - SWTPc MP-T ($E040 - $E04F)
862
                          --
863
 
864
              --
865
              -- Reserved - Timer ($E050 - $E05F) (B5-X300)
866
                          --
867
                          when "0101" =>
868
                            cpu_data_in <= tmr_data_out;
869
                            tmr_cs      <= cpu_vma;
870
 
871
              --
872
              -- Reserved - hardware break point (Bus Trap) ($E060 - $E06F)
873
                          --
874
                          when "0110" =>
875
                            cpu_data_in <= hbp_data_out;
876
                            hbp_cs      <= cpu_vma;
877
 
878
              --
879
              -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
880
                          --
881
 
882
                          --
883
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
884
                          --
885
 
886
                          --
887
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
888
                          --
889
 
890
              --
891
                          -- Read Switched port ($E0A0 - $E0AF)
892
                          -- Write LEDS
893
                          --
894
                          when "1010" =>
895
                cpu_data_in <= led_data_out;
896
                            led_cs     <= cpu_vma;
897
 
898
              --
899
              -- 7 segment display port ($E0B0 - $E0BF)
900
                          --
901
                          when "1011" =>
902
                cpu_data_in <= hex_data_out;
903
                            hex_cs      <= cpu_vma;
904
 
905
 
906
                          when others => -- $EXC0 to $EXFF
907
                            null;
908
                      end case;
909
            --
910
                        --      $E100 to $EFFF reserved for future use
911
                        --
912
                when others =>
913
                          null;
914
         end case;
915
                --
916
                -- Everything else is RAM
917
                --
918
                else
919
                  cpu_data_in <= sram_data_out;
920
                  sram_cs      <= cpu_vma;
921
    end if;
922
end process;
923
 
924
 
925
--
926
-- 1M byte SRAM Control
927
-- Processes to read and write memory based on bus signals
928
--
929
sram_process: process( sys_clk, cpu_rst,
930
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
931
                                          dat_addr, sram_cs,
932
                      sram_ce,  sram_ub, sram_lb, sram_dq,
933
                                          sram_we,  sram_oe )
934
begin
935
    --
936
        -- Clock Hold on rising edge
937
        --
938
    if( sys_clk'event and sys_clk='1' ) then
939
                --
940
                -- sram_hold signal helps
941
                --
942
                if( cpu_rst = '1' ) then
943
                        sram_we   <= '0';
944
                        sram_oe   <= '0';
945
                else
946
                        if (sram_cs = '1') and (sram_we = '0') and (sram_oe = '0') then
947
                                sram_we   <= not cpu_rw;
948
                                sram_oe   <=     cpu_rw;
949
                        else
950
                                sram_we   <= '0';
951
                                sram_oe   <= '0';
952
                        end if;
953
                end if;
954
    end if;
955
 
956
        sram_we_n  <= not sram_we;
957
        sram_oe_n  <= not sram_oe;
958
 
959
    sram_ce   <= sram_cs;
960
    sram_ub   <= not cpu_addr(0);
961
    sram_lb   <= cpu_addr(0);
962
    sram_ce_n <= not sram_ce;
963
    sram_ub_n <= not sram_ub;
964
    sram_lb_n <= not sram_lb;
965
 
966
        sram_addr(17 downto 11) <= dat_addr(6 downto 0);
967
        sram_addr(10 downto 0) <= cpu_addr(11 downto 1);
968
 
969
    if sram_we = '1' and sram_ce = '1' and sram_lb = '1' then
970
                sram_dq(7 downto 0) <= cpu_data_out;
971
        else
972
        sram_dq(7 downto 0)  <= "ZZZZZZZZ";
973
        end if;
974
 
975
    if sram_we = '1' and sram_ce = '1' and sram_ub = '1' then
976
                sram_dq(15 downto 8) <= cpu_data_out;
977
        else
978
        sram_dq(15 downto 8)  <= "ZZZZZZZZ";
979
        end if;
980
 
981
        if cpu_addr(0) = '0' then
982
        sram_data_out <= sram_dq(15 downto 8);
983
        else
984
        sram_data_out <= sram_dq(7 downto 0);
985
    end if;
986
 
987
end process;
988
 
989
--
990
-- LEDS output register
991
--
992
led_output : process( cpu_clk, cpu_rst, led_cs, cpu_rw, cpu_addr, cpu_data_out, sw )
993
begin
994
        if cpu_clk'event and cpu_clk='0' then
995
                if cpu_rst = '1' then
996
                        ledr <= (others=>'0');
997
                        ledg <= (others=>'0');
998
                else
999
                        if led_cs = '1' and cpu_rw = '0' then
1000
                                if cpu_addr(0) = '0' then
1001
                                        ledr(7 downto 0) <= cpu_data_out;
1002
                                else
1003
                                        ledg(7 downto 0) <= cpu_data_out;
1004
                                end if;
1005
                        end if;
1006
                end if;
1007
        end if;
1008
        led_data_out <= sw(7 downto 0);
1009
end process;
1010
 
1011
--
1012
-- 7 segment HEX display output register
1013
--
1014
hex_output : process( cpu_clk, cpu_rst, hex_cs, cpu_rw, cpu_addr, cpu_data_out,
1015
                                                hex0_reg, hex1_reg, hex2_reg, hex3_reg )
1016
begin
1017
        if cpu_clk'event and cpu_clk='0' then
1018
                if cpu_rst = '1' then
1019
                        hex0_reg <= (others=>'0');
1020
                        hex1_reg <= (others=>'0');
1021
                        hex2_reg <= (others=>'0');
1022
                        hex3_reg <= (others=>'0');
1023
                else
1024
                        if      hex_cs = '1' and cpu_rw = '0' then
1025
                                case cpu_addr(1 downto 0) is
1026
                                when "00" =>
1027
                                        hex0_reg <= cpu_data_out;
1028
                                when "01" =>
1029
                                        hex1_reg <= cpu_data_out;
1030
                                when "10" =>
1031
                                        hex2_reg <= cpu_data_out;
1032
                                when "11" =>
1033
                                        hex3_reg <= cpu_data_out;
1034
                                end case;
1035
                        end if;
1036
                end if;
1037
        end if;
1038
 
1039
        case cpu_addr(1 downto 0) is
1040
        when "00" =>
1041
                hex_data_out <= hex0_reg;
1042
        when "01" =>
1043
                hex_data_out <= hex1_reg;
1044
        when "10" =>
1045
                hex_data_out <= hex2_reg;
1046
        when "11" =>
1047
                hex_data_out <= hex3_reg;
1048
        end case;
1049
 
1050
    hex0 <= not hex0_reg(6 downto 0);
1051
    hex1 <= not hex1_reg(6 downto 0);
1052
    hex2 <= not hex2_reg(6 downto 0);
1053
    hex3 <= not hex3_reg(6 downto 0);
1054
 
1055
end process;
1056
 
1057
--
1058
-- Interrupts and other bus control signals
1059
--
1060
interrupts : process(   key, pll_locked,
1061
                                                acia_irq, kbd_irq, hbp_irq, tmr_irq )
1062
begin
1063
        cpu_rst    <= not key(0); -- CPU reset is active high
1064
        cpu_firq   <= kbd_irq;
1065
        cpu_nmi    <= (not key(1)) or hbp_irq;
1066
        cpu_irq    <= acia_irq or tmr_irq;
1067
        cpu_halt   <= '0';
1068
        cpu_hold   <= '0';
1069
end process;
1070
 
1071
--
1072
-- ACIA pin assignments
1073
--
1074
acia_assignments : process( uart_rxd, acia_txd )
1075
begin
1076
        acia_dcd_n <= '0';
1077
        acia_cts_n <= '0';
1078
        acia_rxd   <= uart_rxd;
1079
        uart_txd   <= acia_txd;
1080
end process;
1081
 
1082
--
1083
-- assign vga colour bits to single bit RGB output of VDU
1084
--
1085
vga_assignments : process( vga_red, vga_green, vga_blue )
1086
begin
1087
        vga_r <= (others=>vga_red);
1088
        vga_g <= (others=>vga_green);
1089
        vga_b <= (others=>vga_blue);
1090
end process;
1091
 
1092
--
1093
-- assign dram signals
1094
--
1095
dram_assign : process( all )
1096
begin
1097
        dram_addr  <= (others=>'0');
1098
        dram_cs_n  <= '1';
1099
        dram_ras_n <= '1';
1100
        dram_cas_n <= '1';
1101
        dram_we_n  <= '1';
1102
end process;
1103
 
1104
--
1105
-- assign flash memory signals
1106
--
1107
flash_assign : process( all )
1108
begin
1109
        fl_addr    <= (others=>'0');
1110
        fl_oe_n    <= '1';
1111
        fl_we_n    <= '1';
1112
 
1113
end process;
1114
 
1115
end my_computer; --===================== End of architecture =======================--
1116
 

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