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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [System09_Trenz_TE0141.vhd] - Blame information for rev 114

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1 105 davidgb
-- SECD Front End Processor derived from System09 written by John E. Kent
2
-- This core adheres to the GNU public license  
3
 
4
library ieee;
5
use ieee.std_logic_1164.all;
6
use IEEE.STD_LOGIC_ARITH.ALL;
7
use IEEE.STD_LOGIC_UNSIGNED.ALL;
8
use ieee.numeric_std.all;
9
--use config.all;
10
 
11
entity System09_trenz is
12
  port(
13
         -- the following output assignments are required so that
14
    -- the GT3200 USB phy generates a 30 MHz clock
15
    utmi_databus16_8 : out std_logic;
16
    utmi_reset       : out std_logic;
17
    utmi_xcvrselect  : out std_logic;
18
    utmi_termselect  : out std_logic;
19
    utmi_opmode1     : out std_logic;
20
    utmi_txvalid     : out std_logic;
21
 
22
                -- this is the 30 MHz clock input (clkout is the utmi name)
23
    utmi_clkout      : in std_logic;
24
 
25
    reset_sw    : in    Std_logic;  -- Master Reset input (active low)
26
 
27
    -- PS/2 Keyboard
28
    ps2_clk1    : inout Std_logic;
29
    ps2_data1   : inout Std_Logic;
30
 
31
    -- acia Interface
32
    fpga_rxd    : in    Std_Logic;
33
    fpga_txd    : out   Std_Logic;
34
    fpga_cts    : in    Std_Logic;
35
    fpga_rts    : out   Std_Logic;
36
 
37
    -- CRTC output signals
38
    vsync_b     : out   Std_Logic;
39
    hsync_b     : out   Std_Logic;
40
    fpga_b      : out   Std_Logic_Vector(2 downto 0);
41
    fpga_g      : out   Std_Logic_Vector(2 downto 0);
42
    fpga_r      : out   Std_Logic_Vector(2 downto 0);
43
 
44
    -- LEDS & Switches
45
    mm_led      : out   Std_Logic;
46
    led         : out   Std_Logic_Vector(3 downto 0);
47
 
48
    joy_down    : in    Std_Logic;
49
    joy_fire    : in    Std_Logic;
50
    joy_left    : in    Std_Logic;
51
    joy_right   : in    Std_Logic;
52
    joy_up      : in    Std_Logic;
53
 
54
    -- LCD Display
55
    lcd_e       : out   Std_Logic;
56
    lcd_rw      : out   Std_Logic;
57
    lcd_rs      : out   Std_Logic;
58
    lcd_d       : inout Std_Logic_Vector(3 downto 0);
59
 
60
    -- Audio
61
    aud_out     : out   std_logic_vector(4 downto 1);
62
 
63
    --ir remote control
64
    ir_data     : in    std_logic;
65
 
66
    -- Memory interface
67
    ram_a       : out   std_logic_vector(20 downto 0);
68
    ram_io      : inout std_logic_vector(15 downto 0);
69
    ram_bhen    : out   std_logic;
70
    ram_blen    : out   std_logic;
71
    ram_cen     : out   std_logic;
72
    ram_oen     : out   std_logic;
73
    ram_wen     : out   std_logic;
74
 
75
         -- Flash interface
76
         fl_resetn   : out   std_logic;
77
         fl_cen      : out   std_logic;
78
         fl_oen      : out   std_logic;
79
         fl_byten    : out   std_logic;
80
         fl_busyn    : in    std_logic;
81
 
82
    -- Compact flash
83
         cf_we       : out   std_logic;           -- all these signals are active low
84
         cf_reg      : out   std_logic;           -- for more details see the specification
85
         cf_cs0      : out   std_logic;           -- of compact flash
86
         cf_cs1      : out   std_logic;
87
         cf_reset    : out   std_logic;
88
         cf_iord     : out   std_logic;
89
         cf_iowr     : out   std_logic;
90
         cf_irq      : in    std_logic;
91
         cf_wait     : in    std_logic;
92
         cf_cd1      : in    std_logic;
93
         cf_cd2      : in    std_logic;
94
         iois16      : in    std_logic;
95
         cf_oe       : out   std_logic;
96
         cf_dasp     : inout std_logic;
97
         cf_pdiag    : inout std_logic;
98
 
99
                --cf power enable (active low)
100
         cf_pwr_en   : out   std_logic
101
    );
102
end System09_trenz;
103
 
104
-------------------------------------------------------------------------------
105
-- Architecture for System09
106
-------------------------------------------------------------------------------
107
architecture rtl of System09_trenz is
108
  -----------------------------------------------------------------------------
109
  -- constants
110
  -----------------------------------------------------------------------------
111
  constant SYS_Clock_Frequency  : integer := 50_000_000;  -- FPGA System Clock
112
  constant VGA_Clock_Frequency  : integer := 25_000_000;  -- VGA Pixel Clock
113
  constant CPU_Clock_Frequency  : integer := 25_000_000;  -- CPU Clock
114
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
115
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
116
 
117
  type hold_state_type is ( hold_release_state, hold_request_state );
118
 
119
  -----------------------------------------------------------------------------
120
  -- ChipScope Pro components and signals
121
  -----------------------------------------------------------------------------
122
 
123
--  component icon
124
--    port(control0    :   out std_logic_vector(35 downto 0));
125
--  end component;
126
 
127
--  component ila
128
--    port(control     : in    std_logic_vector(35 downto 0);
129
--         clk         : in    std_logic;
130
--         trig0       : in    std_logic_vector(39 downto 0));
131
--  end component;
132
 
133
--  signal chipscope_control : std_logic_vector(35 downto 0);
134
--  signal ila_clock : std_logic;
135
 
136
  -----------------------------------------------------------------------------
137
  -- Signals
138
  -----------------------------------------------------------------------------
139
 
140
  -- Clocks
141
  attribute buffer_type            : string;
142
  attribute period                 : string;
143
 
144
  signal    sys_clk                : std_logic;      -- 50 Mhz
145
  attribute period of sys_clk      : signal is "20 ns";
146
  attribute buffer_type of sys_clk : signal is "BUFG";
147
 
148
  signal    cpu_clk                : std_logic;      -- 25 Mhz
149
  attribute period of cpu_clk      : signal is "40 ns";
150
  attribute buffer_type of cpu_clk : signal is "BUFG";
151
 
152
  signal    vga_clk                : std_logic;      -- 25 Mhz
153
  attribute period of vga_clk      : signal is "40 ns";
154
  attribute buffer_type of vga_clk : signal is "BUFG";
155
 
156
  -- System Reset (generated by key press)
157
  signal cpu_reset     : std_logic;
158
 
159
  -- Dynamic Address Translation
160
  signal dat_cs        : std_logic;
161
  signal dat_addr      : std_logic_vector(7 downto 0);
162
 
163
  -- BOOT ROM
164
  signal rom_cs        : Std_logic;
165
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
166
 
167
  -- FLEX9 RAM
168
  signal flex_cs       : Std_logic;
169
  signal flex_data_out : Std_Logic_Vector(7 downto 0);
170
 
171
  -- acia Interface signals
172
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
173
  signal acia_cs       : Std_Logic;
174
  signal acia_irq      : Std_Logic;
175
  signal baudclk       : Std_Logic;
176
  signal DCD_n         : Std_Logic;
177
  signal RTS_n         : Std_Logic;
178
  signal CTS_n         : Std_Logic;
179
 
180
  -- keyboard port
181
  signal keyboard_data_out : std_logic_vector(7 downto 0);
182
  signal keyboard_cs       : std_logic;
183
  signal keyboard_irq      : std_logic;
184
 
185
  -- CPU Interface signals
186
  signal cpu_rw       : std_logic;
187
  signal cpu_vma      : std_logic;
188
  signal cpu_halt     : std_logic;
189
  signal cpu_hold     : std_logic;
190
  signal cpu_firq     : std_logic;
191
  signal cpu_irq      : std_logic;
192
  signal cpu_nmi      : std_logic;
193
  signal cpu_addr     : std_logic_vector(15 downto 0);
194
  signal cpu_data_in  : std_logic_vector(7 downto 0);
195
  signal cpu_data_out : std_logic_vector(7 downto 0);
196
 
197
  -- Compact Flash port
198
  -- CF data bus shared with RAM
199
--  signal cf_data_out : std_logic_vector(7 downto 0);
200
  signal cf_cs0x     : std_logic;
201
  signal cf_cs1x     : std_logic;
202
  signal cf_rd       : std_logic;
203
  signal cf_wr       : std_logic;
204
  signal cf_hold     : std_logic;
205
  signal cf_release  : std_logic;
206
  signal cf_count    : std_logic_vector(3 downto 0);
207
  signal cf_hold_state : hold_state_type;
208
 
209
  -- Video Display Unit
210
  signal vdu_cs       : std_logic;
211
  signal vdu_data_out : std_logic_vector(7 downto 0);
212
 
213
  -- VGA output signals (distributed to VGA DAC)
214
  signal red          : std_logic;
215
  signal green        : std_logic;
216
  signal blue         : std_logic;
217
 
218
  -- LCD register select
219
  signal lcd_cs       : std_logic;
220
  signal lcd_data_in  : std_logic_vector(7 downto 0);
221
  signal lcd_data_out : std_logic_vector(7 downto 0);
222
 
223
  -- LED register select
224
  signal leds_cs       : std_logic;
225
  signal leds_data_in  : std_logic_vector(7 downto 0) := (others => '0');
226
  signal leds_data_out : std_logic_vector(7 downto 0) := (others => '0');
227
 
228
  -- Joystick buffer
229
  signal joy_cs       : std_logic;
230
  signal joy_data_out : std_logic_vector(7 downto 0);
231
 
232
  -- External RAM interface
233
  signal ram_cs       : std_logic := '0';
234
  signal ram_data_out : std_logic_vector(7 downto 0);
235
  signal ram_oe       : std_logic;
236
  signal ram_we       : std_logic;
237
 
238
  -- Locked signal of clock synthesizer
239
  signal clock_locked : std_logic;
240
  signal ila_clock    : std_logic;
241
 
242
  -- LED Flasher
243
  signal blink_count  : std_logic_vector(25 downto 0) := (others => '0');
244
 
245
  -- System Clock Prescaler
246
  signal clk_count    : std_logic;
247
 
248
 
249
-----------------------------------------------------------------
250
--
251
-- CPU09 CPU core
252
--
253
-----------------------------------------------------------------
254
 
255
  component cpu09
256
    port (
257
      clk      : in  std_logic;
258
      rst      : in  std_logic;
259
      rw       : out std_logic;         -- Asynchronous memory interface
260
      vma      : out std_logic;
261
      address  : out std_logic_vector(15 downto 0);
262
      data_in  : in      std_logic_vector(7 downto 0);
263
      data_out : out std_logic_vector(7 downto 0);
264
      halt     : in  std_logic;
265
      hold     : in  std_logic;
266
      irq      : in  std_logic;
267
      nmi      : in  std_logic;
268
      firq     : in  std_logic
269
      );
270
  end component;
271
 
272
 
273
----------------------------------------
274
--
275
-- 4KByte Block RAM Monitor ROM
276
--
277
----------------------------------------
278
component mon_rom
279
  Port (
280
    clk      : in  std_logic;
281
    rst      : in  std_logic;
282
    cs       : in  std_logic;
283
    rw       : in  std_logic;
284
    addr     : in  std_logic_vector (11 downto 0);
285
    rdata    : out std_logic_vector (7 downto 0);
286
    wdata    : in  std_logic_vector (7 downto 0)
287
    );
288
end component;
289
 
290
----------------------------------------
291
--
292
-- 8KBytes Block RAM for FLEX9
293
-- $C000 - $DFFF
294
--
295
----------------------------------------
296
component flex_ram
297
  Port (
298
    clk      : in  std_logic;
299
    rst      : in  std_logic;
300
    cs       : in  std_logic;
301
    rw       : in  std_logic;
302
    addr     : in  std_logic_vector (12 downto 0);
303
    rdata    : out std_logic_vector (7 downto 0);
304
    wdata    : in  std_logic_vector (7 downto 0)
305
    );
306
end component;
307
 
308
----------------------------------------
309
--
310
-- Dynamic Address Translation Registers
311
--
312
----------------------------------------
313
component dat_ram
314
  port (
315
    clk      : in  std_logic;
316
         rst      : in  std_logic;
317
         cs       : in  std_logic;
318
         rw       : in  std_logic;
319
         addr_lo  : in  std_logic_vector(3 downto 0);
320
         addr_hi  : in  std_logic_vector(3 downto 0);
321
    data_in  : in  std_logic_vector(7 downto 0);
322
         data_out : out std_logic_vector(7 downto 0)
323
  );
324
end component;
325
 
326
 
327
-----------------------------------------------------------------
328
--
329
-- 6850 ACIA / UART
330
--
331
-----------------------------------------------------------------
332
 
333
  component ACIA_6850
334
    port (
335
      clk      : in  Std_Logic;  -- System Clock
336
      rst      : in  Std_Logic;  -- Reset input (active high)
337
      cs       : in  Std_Logic;  -- ACIA Chip Select
338
      rw       : in  Std_Logic;  -- Read / Not Write
339
      irq      : out Std_Logic;  -- Interrupt
340
      Addr     : in  Std_Logic;  -- Register Select
341
      DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
342
      DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
343
      RxC      : in  Std_Logic;  -- Receive Baud Clock
344
      TxC      : in  Std_Logic;  -- Transmit Baud Clock
345
      RxD      : in  Std_Logic;  -- Receive Data
346
      TxD      : out Std_Logic;  -- Transmit Data
347
      DCD_n    : in  Std_Logic;  -- Data Carrier Detect
348
      CTS_n    : in  Std_Logic;  -- Clear To Send
349
      RTS_n    : out Std_Logic   -- Request To send
350
      );
351
  end component;
352
 
353
-----------------------------------------------------------------
354
--
355
-- ACIA Clock divider
356
--
357
-----------------------------------------------------------------
358
 
359
  component ACIA_Clock
360
    generic (
361
      SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
362
      ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
363
      );
364
    port (
365
      clk      : in  Std_Logic;  -- System Clock Input
366
      ACIA_clk : out Std_logic   -- ACIA Clock output
367
      );
368
  end component;
369
 
370
 
371
----------------------------------------
372
--
373
-- PS/2 Keyboard
374
--
375
----------------------------------------
376
 
377
  component keyboard
378
    generic(
379
      KBD_Clock_Frequency : integer := CPU_Clock_Frequency
380
      );
381
    port(
382
      clk             : in    std_logic;
383
      rst             : in    std_logic;
384
      cs              : in    std_logic;
385
      rw              : in    std_logic;
386
      addr            : in    std_logic;
387
      data_in         : in    std_logic_vector(7 downto 0);
388
      data_out        : out   std_logic_vector(7 downto 0);
389
      irq             : out   std_logic;
390
      kbd_clk         : inout std_logic;
391
      kbd_data        : inout std_logic
392
      );
393
  end component;
394
 
395
----------------------------------------
396
--
397
-- Video Display Unit.
398
--
399
----------------------------------------
400
  component vdu8
401
    generic(
402
      VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
403
      VGA_CLOCK_FREQUENCY    : integer := VGA_Clock_Frequency; -- HZ
404
      VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
405
      VGA_VER_CHARS          : integer := 25; -- CHARACTERS
406
      VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
407
      VGA_LINES_PER_CHAR     : integer := 16; -- LINES
408
      VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
409
      VGA_HOR_SYNC           : integer := 96; -- PIXELS
410
      VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
411
      VGA_VER_BACK_PORCH     : integer := 13; -- LINES
412
      VGA_VER_SYNC           : integer := 1;  -- LINES
413
      VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
414
      );
415
    port(
416
      -- control register interface
417
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
418
      vdu_rst      : in  std_logic;
419
      vdu_cs       : in  std_logic;
420
      vdu_rw       : in  std_logic;
421
      vdu_addr     : in  std_logic_vector(2 downto 0);
422
      vdu_data_in  : in  std_logic_vector(7 downto 0);
423
      vdu_data_out : out std_logic_vector(7 downto 0);
424
 
425
      -- vga port connections
426
      vga_clk      : in  std_logic;     -- VGA Pixel Clock - 25 MHz
427
      vga_red_o    : out std_logic;
428
      vga_green_o  : out std_logic;
429
      vga_blue_o   : out std_logic;
430
      vga_hsync_o  : out std_logic;
431
      vga_vsync_o  : out std_logic
432
      );
433
  end component;
434
 
435
--  component ram_controller
436
--  port(
437
--    reset      : in  std_logic;
438
--    clk        : in  std_logic;
439
--    cs_ram     : in  std_logic;
440
--    rw         : in  std_logic;
441
--    din        : in  std_logic_vector(7 downto 0);
442
--    dout       : out std_logic_vector(7 downto 0);
443
--    addr       : in  std_logic_vector(19 downto 0);
444
 
445
    -- External interface
446
--    ram_oen    : out   std_logic;
447
--    ram_cen    : out   std_logic;
448
--    ram_wen    : out   std_logic;
449
--    ram_io     : inout std_logic_vector(15 downto 0);
450
--    ram_a      : out   std_logic_vector(20 downto 1);
451
--    ram_bhen   : out   std_logic;
452
--    ram_blen   : out   std_logic
453
--  );
454
--  end component;
455
 
456
component BUFG
457
  port (
458
    i            : in  std_logic;
459
    o            : out std_logic
460
  );
461
end component;
462
 
463
begin
464
 
465
  -----------------------------------------------------------------
466
  --
467
  -- ChipsScope Pro cores
468
  --
469
  -----------------------------------------------------------------
470
 
471
--  i_icon : icon
472
--    port map(control0  => chipscope_control);
473
--
474
--  i_ila : ila
475
--    port map(control => chipscope_control,
476
--             clk => ila_clock,
477
--             trig0(15 downto 8) => cpu_data_in,
478
--             trig0(23 downto 16) => cpu_data_out,
479
--             trig0(39 downto 24) => cpu_addr,
480
--             trig0(0) => cpu_clk,
481
--             trig0(1) => cpu_vma,
482
--             trig0(2) => ram_bhenx,
483
--             trig0(3) => ram_blenx,
484
--             trig0(4) => ram_cenx,
485
--             trig0(5) => ram_oenx,
486
--             trig0(6) => ram_wenx,
487
--             trig0(7) => vga_clk);
488
 
489
 
490
 
491
  -----------------------------------------------------------------
492
  --
493
  -- CPU09 CPU core
494
  --
495
  -----------------------------------------------------------------
496
 
497
  my_cpu : entity cpu09 port map (
498
    clk      => cpu_clk,
499
    rst       => cpu_reset,
500
    rw       => cpu_rw,
501
    vma       => cpu_vma,
502
    address   => cpu_addr,
503
    data_in   => cpu_data_in,
504
    data_out  => cpu_data_out,
505
    halt      => cpu_halt,
506
    hold      => cpu_hold,
507
    irq       => cpu_irq,
508
    nmi       => cpu_nmi,
509
    firq      => cpu_firq
510
    );
511
 
512
  ----------------------------------------
513
  --
514
  -- Sys09Bug ROM (Xilinx Block RAM, 4k)
515
  --
516
  ----------------------------------------
517
 
518
my_rom : mon_rom port map (
519
    clk       => cpu_clk,
520
    rst       => cpu_reset,
521
         cs        => rom_cs,
522
         rw        => '1',
523
    addr      => cpu_addr(11 downto 0),
524
    rdata     => rom_data_out,
525
    wdata     => cpu_data_out
526
    );
527
 
528
  ----------------------------------------
529
  --
530
  -- Flex Operating System (Xilinx Block RAM, 8k)
531
  --
532
  ----------------------------------------
533
 
534
my_flex : flex_ram port map (
535
    clk       => cpu_clk,
536
    rst       => cpu_reset,
537
         cs        => flex_cs,
538
         rw        => cpu_rw,
539
    addr      => cpu_addr(12 downto 0),
540
    rdata     => flex_data_out,
541
    wdata     => cpu_data_out
542
    );
543
 
544
  ----------------------------------------
545
  --
546
  -- Dynamic Address Translation
547
  --
548
  ----------------------------------------
549
 
550
my_dat : dat_ram port map (
551
    clk       => cpu_clk,
552
         rst       => cpu_reset,
553
         cs        => dat_cs,
554
         rw        => cpu_rw,
555
         addr_hi   => cpu_addr(15 downto 12),
556
         addr_lo   => cpu_addr(3 downto 0),
557
    data_in   => cpu_data_out,
558
         data_out  => dat_addr(7 downto 0)
559
         );
560
 
561
 
562
  -----------------------------------------------------------------
563
  --
564
  -- 6850 ACIA
565
  --
566
  -----------------------------------------------------------------
567
 
568
  my_acia  : entity acia_6850 port map (
569
    clk      => cpu_clk,
570
    rst       => cpu_reset,
571
    cs        => acia_cs,
572
    rw        => cpu_rw,
573
    irq       => acia_irq,
574
    Addr      => cpu_addr(0),
575
    Datain    => cpu_data_out,
576
    DataOut   => acia_data_out,
577
    RxC       => baudclk,
578
    TxC       => baudclk,
579
    RxD       => fpga_rxd,
580
    TxD       => fpga_txd,
581
    DCD_n     => dcd_n,
582
    CTS_n     => fpga_cts,
583
    RTS_n     => fpga_rts
584
    );
585
 
586
 
587
----------------------------------------
588
--
589
-- PS/2 Keyboard Interface
590
--
591
----------------------------------------
592
  my_keyboard : keyboard
593
    generic map (
594
      KBD_Clock_Frequency => CPU_Clock_frequency
595
      )
596
    port map(
597
      clk          => cpu_clk,
598
      rst          => cpu_reset,
599
      cs           => keyboard_cs,
600
      rw           => cpu_rw,
601
      addr         => cpu_addr(0),
602
      data_in      => cpu_data_out(7 downto 0),
603
      data_out     => keyboard_data_out(7 downto 0),
604
      irq          => keyboard_irq,
605
      kbd_clk      => ps2_clk1,
606
      kbd_data     => ps2_data1
607
      );
608
 
609
----------------------------------------
610
--
611
-- Video Display Unit instantiation
612
--
613
----------------------------------------
614
  my_vdu : vdu8
615
    generic map(
616
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
617
      VGA_CLOCK_FREQUENCY    => VGA_Clock_Frequency, -- HZ
618
      VGA_HOR_CHARS          => 80, -- CHARACTERS
619
      VGA_VER_CHARS          => 25, -- CHARACTERS
620
      VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
621
      VGA_LINES_PER_CHAR     => 16, -- LINES
622
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
623
      VGA_HOR_SYNC           => 96, -- PIXELS
624
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
625
      VGA_VER_BACK_PORCH     => 13, -- LINES
626
      VGA_VER_SYNC           => 1,  -- LINES
627
      VGA_VER_FRONT_PORCH    => 36  -- LINES
628
      )
629
    port map(
630
 
631
      -- Control Registers
632
      vdu_clk       => cpu_clk,                                  -- 12.5 MHz System Clock in
633
      vdu_rst       => cpu_reset,
634
      vdu_cs        => vdu_cs,
635
      vdu_rw        => cpu_rw,
636
      vdu_addr      => cpu_addr(2 downto 0),
637
      vdu_data_in   => cpu_data_out,
638
      vdu_data_out  => vdu_data_out,
639
 
640
      -- vga port connections
641
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
642
      vga_red_o     => red,
643
      vga_green_o   => green,
644
      vga_blue_o    => blue,
645
      vga_hsync_o   => hsync_b,
646
      vga_vsync_o   => vsync_b
647
      );
648
 
649
  ----------------------------------------
650
  --
651
  -- Clock Synthesis instantiation
652
  --
653
  ----------------------------------------
654
 
655
  my_clock_synthesis : entity clock_synthesis port map (
656
    clk_30mhz       => utmi_clkout,
657
    sys_clk_out     => sys_clk,
658
    locked          => clock_locked );
659
 
660
 
661
vga_clk_buffer : BUFG port map(
662
    i => clk_count,
663
         o => vga_clk
664
    );
665
 
666
cpu_clk_buffer : BUFG port map(
667
    i => clk_count,
668
         o => cpu_clk
669
    );
670
 
671
  ----------------------------------------
672
  --
673
  -- RAM Controller instantiation
674
  --
675
  ----------------------------------------
676
 
677
--  my_external_ram : entity ram_controller port map (
678
--    reset              => cpu_reset,
679
--    clk                => cpu_clk,
680
--    cs_ram             => ram_cs,
681
--    rw                 => cpu_rw,
682
--    din                => cpu_data_out,
683
--    dout               => ram_data_out,
684
--    addr(19 downto 12) => dat_addr( 7 downto 0),
685
--    addr(11 downto 0)  => cpu_addr(11 downto 0),
686
 
687
    -- external interface
688
--    ram_oen           => ram_oenx,
689
--    ram_cen           => ram_cenx,
690
--    ram_wen           => ram_wenx,
691
--    ram_io        => ram_io,
692
--    ram_a         => ram_a,
693
--    ram_bhen          => ram_bhenx,
694
--    ram_blen          => ram_blenx
695
--    );
696
 
697
 
698
----------------------------------------
699
--
700
-- ACIA Clock
701
--
702
----------------------------------------
703
  my_ACIA_Clock : ACIA_Clock
704
    generic map(
705
      SYS_Clock_Frequency  => SYS_Clock_Frequency,
706
      ACIA_Clock_Frequency => ACIA_Clock_Frequency
707
      )
708
    port map(
709
      clk        => sys_clk,
710
      acia_clk   => baudclk
711
      );
712
 
713
 
714
--
715
-- Generate a 25 MHz Clock from 50 MHz
716
--
717
my_sys09_clk : process( sys_clk, clk_count )
718
begin
719
  if sys_clk'event and sys_clk = '1' then
720
    clk_count <= not clk_count;
721
  end if;
722
end process;
723
 
724
----------------------------------------------------------------------
725
--
726
-- Process to decode memory map
727
--
728
----------------------------------------------------------------------
729
 
730
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
731
                                              dat_cs, dat_addr,
732
                                              rom_data_out,
733
                                                   acia_data_out,
734
                                                        keyboard_data_out,
735
                                                        vdu_data_out,
736
                                                        joy_data_out,
737
                                                        lcd_data_out,
738
                                                        leds_data_out,
739
                                                        flex_data_out,
740
                                                        ram_data_out
741
                                                        )
742
begin
743
         cpu_data_in <= (others => '0');
744
    dat_cs      <= '0';
745
    rom_cs      <= '0';
746
    acia_cs     <= '0';
747
    keyboard_cs <= '0';
748
    vdu_cs      <= '0';
749
         cf_cs0x     <= '0';
750
         cf_cs1x     <= '0';
751
         joy_cs      <= '0';
752
    lcd_cs      <= '0';
753
    leds_cs     <= '0';
754
    flex_cs     <= '0';
755
    ram_cs      <= '0';
756
 
757
    if cpu_addr( 15 downto 8 ) = "11111111" then
758
             cpu_data_in <= rom_data_out;
759
        dat_cs      <= cpu_vma;              -- write DAT
760
        rom_cs      <= cpu_vma;              -- read  ROM
761
         --
762
    -- Sys09Bug Monitor ROM $F000 - $FFFF
763
         --
764
         elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
765
           --
766
                -- Monitor ROM $F000 - $FFFF
767
                --
768
      cpu_data_in <= rom_data_out;
769
      rom_cs      <= cpu_vma;          -- read  ROM
770
 
771
    --
772
         -- IO Devices $E000 - $EFFF
773
         --
774
         elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
775
                   dat_cs      <= '0';
776
                        rom_cs      <= '0';
777
                        case cpu_addr(11 downto 8) is
778
                        when "0000" =>
779
                     case cpu_addr(7 downto 4) is
780
                          --
781
                          -- UART / ACIA ($E000 - $E00F)
782
                          --
783
                          when "0000" =>
784
                       cpu_data_in <= acia_data_out;
785
                            acia_cs     <= cpu_vma;
786
 
787
                          --
788
                          -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
789
           --
790
 
791
                          --
792
           -- Keyboard port ($E020 - $E02F)
793
                          --
794
                          when "0010" =>
795
             cpu_data_in <= keyboard_data_out;
796
                            keyboard_cs <= cpu_vma;
797
 
798
           --
799
           -- VDU port ($E030 - $E03F)
800
                          --
801
                          when "0011" =>
802
             cpu_data_in <= vdu_data_out;
803
                            vdu_cs      <= cpu_vma;
804
 
805
           --
806
                          -- Reserved SWTPc MP-T ($E040 - $E04F)
807
                          --
808
 
809
           --
810
           -- Reserved - Timer ($E050 - $E05F) (B5-X300)
811
                          --
812
 
813
           --
814
           -- Reserved - Bus Trap Logic ($E060 - $E06F) (B5-X300)
815
                          --
816
 
817
           --
818
           -- Reserved - I/O port ($E070 - $E07F) (B5-X300)
819
                          --
820
 
821
                          --
822
                          -- Reserved - PTM 6840 ($E080 - $E08F) (SWTPC)
823
                          --
824
 
825
                          --
826
                          -- Reserved - PIA Timer ($E090 - $E09F) (SWTPC)
827
                          --
828
 
829
           --
830
                          -- Read LED port ($E0A0 - $E0AF)
831
                          -- Write LEDS
832
                          --
833
                          when "1010" =>
834
             cpu_data_in <= leds_data_out;
835
                            leds_cs     <= cpu_vma;
836
 
837
           --
838
           -- LCD display port ($E0B0 - $E0BF)
839
                          --
840
                          when "1011" =>
841
             cpu_data_in <= lcd_data_out;
842
                            lcd_cs      <= cpu_vma;
843
 
844
           --
845
                          -- Read Joy Stick port ($E0D0 - $E0DF)
846
                          -- Write LEDS
847
                          --
848
                          when "1101" =>
849
             cpu_data_in <= joy_data_out;
850
                            joy_cs     <= cpu_vma;
851
 
852
           --
853
                          -- Read LED port ($E0E0 - $E0EF)
854
                          -- Write LEDS
855
                          --
856
                          when "1110" =>
857
             cpu_data_in <= leds_data_out;
858
                            leds_cs     <= cpu_vma;
859
 
860
           --
861
           -- LCD display port ($E0F0 - $E0BF)
862
                          --
863
                          when "1111" =>
864
             cpu_data_in <= lcd_data_out;
865
                            lcd_cs      <= cpu_vma;
866
 
867
                          when others => -- $EXC0 to $EXFF
868
                             null;
869
 
870
                     end case;
871
                        --
872
                        -- XST-3.0 Peripheral Bus goes here
873
                        --      $E100 to $E1FF
874
                        --      Four devices
875
                        -- IDE, Ethernet, Slot1, Slot2
876
                        --
877
                        when "0001" =>
878
           cpu_data_in <= ram_data_out;
879
 
880
                     case cpu_addr(7 downto 4) is
881
                          --
882
                          -- CF Interface $E100 to $E1FF
883
                          --
884
                          when "0000" =>
885
                            cf_cs0x     <= cpu_vma;
886
 
887
                          when "0001" =>
888
                            cf_cs1x     <= cpu_vma;
889
           --
890
                          -- Nothing else
891
                          --
892
           when others =>
893
                            null;
894
           end case;
895
         --
896
                        --      $E200 to $EFFF reserved for future use
897
                        --
898
                when others =>
899
                          cpu_data_in <= (others => '0');
900
         end case;
901
           --
902
                -- FLEX RAM $0C000 - $0DFFF
903
                --
904
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
905
        cpu_data_in <= flex_data_out;
906
        flex_cs     <= cpu_vma;
907
                --
908
                -- Everything else is RAM
909
                --
910
                else
911
                  cpu_data_in <= ram_data_out;
912
                  ram_cs      <= cpu_vma;
913
      end if;
914
end process;
915
 
916
--
917
-- 1M byte SRAM Control
918
-- Processes to read and write memory based on bus signals
919
-- using bhe/ble controlled read and write.
920
-- Can't gate the write pulse with the clock
921
-- because the bus is shared with the CF 
922
-- which uses clock stretching.
923
--
924
ram_process: process( cpu_reset, sys_clk, cpu_addr, cpu_rw, cpu_data_out, dat_addr,
925
                      ram_cs, ram_io, ram_we, ram_oe )
926
begin
927
    --
928
    -- ram_hold signal helps 
929
    --
930
    if( cpu_reset = '1' ) then
931
           ram_we   <= '0';
932
           ram_oe   <= '0';
933
    --
934
         -- Clock Hold on rising edge
935
         --
936
    elsif( sys_clk'event and sys_clk='1' ) then
937
           if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then
938
             ram_we   <= not cpu_rw;
939
             ram_oe   <=     cpu_rw;
940
      else
941
             ram_we   <= '0';
942
             ram_oe   <= '0';
943
      end if;
944
    end if;
945
 
946
    ram_cen  <= not ram_cs;
947
    ram_bhen <=     cpu_addr(0);
948
    ram_blen <= not cpu_addr(0);
949
         ram_wen  <= not ram_we;
950
         ram_oen  <= not ram_oe;
951
 
952
         ram_a(20) <= '0';
953
         ram_a(19 downto 0) <= dat_addr(7 downto 0) & cpu_addr(11 downto 0);
954
 
955
    if (cpu_rw = '0') and (cpu_addr(0) = '0') then
956
                ram_io(15 downto 8) <= cpu_data_out;
957
         else
958
      ram_io(15 downto 8)  <= "ZZZZZZZZ";
959
         end if;
960
 
961
    if (cpu_rw = '0') and (cpu_addr(0) = '1') then
962
                ram_io(7 downto 0) <= cpu_data_out;
963
         else
964
      ram_io(7 downto 0)  <= "ZZZZZZZZ";
965
         end if;
966
 
967
         if cpu_addr(0) = '0' then
968
      ram_data_out <= ram_io(15 downto 8);
969
    else
970
      ram_data_out <= ram_io(7 downto 0);
971
    end if;
972
end process;
973
 
974
--
975
-- Compact Flash Control
976
-- Configure compact flash for TRUE IDE mode
977
--
978
  compact_flash: process( reset_sw,
979
                          cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
980
                          cf_cs0x, cf_cs1x, cf_rd, cf_wr, cf_cd1, cf_cd2 )
981
  begin
982
    cf_reset  <= reset_sw;
983
    cf_pwr_en <= (cf_cd1) or (cf_cd2);    -- power enable when card detect
984
    cf_oe     <= '0';                                      -- TRUE IDE mode
985
    cf_we     <= '1';
986
    cf_reg    <= '1';
987
    cf_cs0    <= not cf_cs0x;
988
    cf_cs1    <= not cf_cs1x;
989
    cf_wr     <= (cf_cs0x or cf_cs1x) and (not cpu_rw);
990
    cf_rd     <= (cf_cs0x or cf_cs1x) and      cpu_rw;
991
    cf_iowr   <= not cf_wr;
992
    cf_iord   <= not cf_rd;
993
  end process;
994
 
995
 
996
--
997
-- Hold CF access       for a few cycles
998
--
999
cf_hold_proc: process( cpu_clk, cpu_reset )
1000
begin
1001
    if cpu_reset = '1' then
1002
                 cf_release    <= '0';
1003
                 cf_count      <= "0000";
1004
            cf_hold_state <= hold_release_state;
1005
         elsif falling_edge( cpu_clk ) then
1006
            case cf_hold_state is
1007
                 when hold_release_state =>
1008
          cf_release <= '0';
1009
                    if (cf_cs0x = '1') or (cf_cs1x = '1') then
1010
                            cf_count      <= "0011";
1011
                                 cf_hold_state <= hold_request_state;
1012
                         end if;
1013
 
1014
                 when hold_request_state =>
1015
                    cf_count <= cf_count - "0001";
1016
                         if cf_count = "0000" then
1017
             cf_release    <= '1';
1018
                                 cf_hold_state <= hold_release_state;
1019
                         end if;
1020
       when others =>
1021
                    null;
1022
       end case;
1023
         end if;
1024
 
1025
end process;
1026
 
1027
 
1028
--
1029
-- Interrupts and other bus control signals
1030
--
1031
  interrupts : process( acia_irq, keyboard_irq, joy_up, cf_cs0x, cf_cs1x, cf_hold, cf_release )
1032
  begin
1033
    cf_hold   <= (cf_cs0x or cf_cs1x) and (not cf_release);
1034
    cpu_irq   <= keyboard_irq;
1035
    cpu_nmi   <= not joy_up;
1036
    cpu_firq  <= acia_irq;
1037
    cpu_halt  <= '0';
1038
    cpu_hold  <= cf_hold;
1039
  end process;
1040
 
1041
  --
1042
  -- LCD write register
1043
  -- LCD_data_in and LCD_data_out 
1044
  -- are relative to the CPU
1045
  -- Not the LCD display
1046
  --
1047
  lcd_control : process(cpu_reset, cpu_clk, lcd_data_in, lcd_d )
1048
  begin
1049
    if cpu_reset = '1' then
1050
           lcd_data_in <= (others => '0');
1051
    elsif falling_edge(cpu_clk) then
1052
      if lcd_cs = '1' and cpu_rw = '0' then
1053
         lcd_data_in <= cpu_data_out;
1054
      end if;
1055
    end if;
1056
         if lcd_data_in(4) = '1' and lcd_data_in(5) = '0' then
1057
       lcd_d  <= lcd_data_in(3 downto 0);
1058
    else
1059
            lcd_d  <= (others => 'Z');
1060
    end if;
1061
    lcd_e     <= lcd_data_in(4);
1062
    lcd_rw    <= lcd_data_in(5);
1063
    lcd_rs    <= lcd_data_in(6);
1064
         -- read back control signals
1065
         lcd_data_out(7 downto 4) <= lcd_data_in(7 downto 4);
1066
         -- read back 4 bit data bus
1067
         lcd_data_out(3 downto 0) <= lcd_d(3 downto 0);
1068
  end process;
1069
 
1070
  --
1071
  -- LED write register
1072
  --
1073
  led_control : process(cpu_reset, cpu_clk, leds_data_in)
1074
  begin
1075
    if cpu_reset = '1' then
1076
      leds_data_in <= (others => '1');
1077
    elsif falling_edge(cpu_clk) then
1078
      if leds_cs = '1' and cpu_rw = '0' then
1079
        leds_data_in <= cpu_data_out;
1080
      end if;
1081
    end if;
1082
    led <= leds_data_in(3 downto 0);
1083
         -- read back output state
1084
         leds_data_out <= leds_data_in;
1085
  end process;
1086
 
1087
 
1088
  --
1089
  -- Joystick register
1090
  --
1091
  read_joystick : process(cpu_clk, joy_up, joy_right, joy_down, joy_left, joy_fire)
1092
  begin
1093
    if rising_edge(cpu_clk) then
1094
      joy_data_out(0) <= joy_up;
1095
      joy_data_out(1) <= joy_right;
1096
      joy_data_out(2) <= joy_down;
1097
      joy_data_out(3) <= joy_left;
1098
      joy_data_out(4) <= joy_fire;
1099
      joy_data_out(7 downto 5) <= (others => '0');
1100
    end if;
1101
  end process;
1102
 
1103
--
1104
-- LED Flasher
1105
--
1106
  my_led_flasher: process(vga_clk, cpu_reset, blink_count)
1107
  begin
1108
    if cpu_reset = '1' then
1109
      blink_count <= (others => '0');
1110
    elsif rising_edge(vga_clk) then
1111
      blink_count <= blink_count + 1;
1112
    end if;
1113
 
1114
    mm_led <= blink_count(25);
1115
 
1116
  end process;
1117
 
1118
 
1119
-- Set acia DCD to always true
1120
  DCD_n <= '0';
1121
 
1122
--
1123
-- configure utmi for 30MHz clock
1124
--
1125
  utmi_databus16_8 <= '1';
1126
  utmi_reset             <= '0';
1127
  utmi_xcvrselect        <= '1';
1128
  utmi_termselect        <= '1';
1129
  utmi_opmode1           <= '0';
1130
  utmi_txvalid           <= '0';
1131
 
1132
--
1133
-- Feed RGB DAC
1134
--
1135
  fpga_r(0) <= red;
1136
  fpga_r(1) <= red;
1137
  fpga_r(2) <= red;
1138
  fpga_g(0) <= green;
1139
  fpga_g(1) <= green;
1140
  fpga_g(2) <= green;
1141
  fpga_b(0) <= blue;
1142
  fpga_b(1) <= blue;
1143
  fpga_b(2) <= blue;
1144
 
1145
  -- Hold system in reset until the clock is locked or when the reset
1146
  -- key is pressed.
1147
  cpu_reset <= (not reset_sw ) or (not clock_locked);
1148
 
1149
  --
1150
  -- Terminate Audio Output signals
1151
  --
1152
  aud_out <= (others => '0');
1153
 
1154
  --
1155
  -- Terminate Flash memory controls
1156
  --
1157
  fl_resetn <= '1';
1158
  fl_cen    <= '1';
1159
  fl_oen    <= '1';
1160
  fl_byten  <= '1';
1161
 
1162
-- debug output
1163
--      input detected from an IR remote control is forwarded to the LED on the micromodule.
1164
-- there it is easily accessible by a scope and you can also see some flicker when pressing a button.
1165
--  mm_led <= ir_data;
1166
 
1167
 
1168
end;
1169
 

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