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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [clock_synthesis_50.vhd] - Blame information for rev 120

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Line No. Rev Author Line
1 105 davidgb
--
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-- Clock synthesis
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--
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-- This module generates the 50 Mhz System Clock
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-- from the Trenz 30MHz clock using a DCM.  
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-- The outputs are fed into BUFGs.
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--
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-- synopsys translate_off
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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-- synopsys translate_on
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entity clock_synthesis is
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  port ( clk_30mhz   : in  std_logic;
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         sys_clk_out : out std_logic;
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         locked      : out std_logic);
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end clock_synthesis;
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architecture BEHAVIORAL of clock_synthesis is
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  signal clk_30mhz_ibufg : std_logic;
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  signal sys_clkfb_in    : std_logic;
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  signal sys_clkfb_out   : std_logic;
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  signal sys_clk_in      : std_logic;
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  signal gnd1            : std_logic;
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  component BUFG
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    port ( I : in    std_logic;
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           O : out   std_logic);
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  end component;
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  component IBUFG
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    port ( I : in    std_logic;
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           O : out   std_logic);
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  end component;
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  -- Period Jitter with noise (unit interval) for block DCM_INST = 0.04 UI
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  -- Period Jitter with noise (Peak-to-Peak) for block DCM_INST = 0.86 ns
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  component DCM
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    generic( CLK_FEEDBACK          : string     :=  "1X";
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             CLKDV_DIVIDE          : real       :=  2.000000;
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             CLKFX_DIVIDE          : integer    :=  1;
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             CLKFX_MULTIPLY        : integer    :=  4;
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             CLKIN_DIVIDE_BY_2     : boolean    :=  FALSE;
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             CLKIN_PERIOD          : real       :=  10.000000;
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             CLKOUT_PHASE_SHIFT    : string     :=  "NONE";
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             DESKEW_ADJUST         : string     :=  "SYSTEM_SYNCHRONOUS";
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             DFS_FREQUENCY_MODE    : string     :=  "LOW";
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             DLL_FREQUENCY_MODE    : string     :=  "LOW";
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             DUTY_CYCLE_CORRECTION : boolean    :=  TRUE;
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             FACTORY_JF            : bit_vector :=  x"C080";
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             PHASE_SHIFT           : integer    :=  0;
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             STARTUP_WAIT          : boolean    :=  TRUE;
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             DSS_MODE              : string     :=  "NONE");
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    port ( CLKIN    : in    std_logic;
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           CLKFB    : in    std_logic;
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           RST      : in    std_logic;
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           PSEN     : in    std_logic;
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           PSINCDEC : in    std_logic;
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           PSCLK    : in    std_logic;
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           DSSEN    : in    std_logic;
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           CLK0     : out   std_logic;
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           CLK90    : out   std_logic;
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           CLK180   : out   std_logic;
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           CLK270   : out   std_logic;
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           CLKDV    : out   std_logic;
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           CLK2X    : out   std_logic;
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           CLK2X180 : out   std_logic;
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           CLKFX    : out   std_logic;
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           CLKFX180 : out   std_logic;
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           STATUS   : out   std_logic_vector (7 downto 0);
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           LOCKED   : out   std_logic;
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           PSDONE   : out   std_logic);
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  end component;
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begin
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  GND1 <= '0';
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  sys_clkin_ibufg_inst : ibufg
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    port map (i => clk_30mhz,
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              o => clk_30mhz_ibufg);
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  sys_clk_bufg_inst : bufg
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    port map (i => sys_clk_in,
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              o => sys_clk_out);
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  sys_fb_bufg_inst : bufg
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    port map (i => sys_clkfb_in,
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              o => sys_clkfb_out);
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  sys_clk_dcm : dcm
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    generic map( clk_feedback          =>  "1X",
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                 clkfx_divide          =>  6,
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                 clkfx_multiply        =>  10,
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                 clkin_divide_by_2     =>  FALSE,
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                 clkin_period          =>  33.333300,
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                 clkout_phase_shift    =>  "NONE",
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                 deskew_adjust         =>  "SYSTEM_SYNCHRONOUS",
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                 dfs_frequency_mode    =>  "LOW",
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                 dll_frequency_mode    =>  "LOW",
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                 duty_cycle_correction =>  TRUE,
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                 factory_jf            =>  x"C080",
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                 phase_shift           =>  0,
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                 startup_wait          =>  FALSE)
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    port map (clkfb    => sys_clkfb_out,
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              clkin    => clk_30mhz_ibufg,
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              dssen    => gnd1,
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              psclk    => gnd1,
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              psen     => gnd1,
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              psincdec => gnd1,
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              rst      => gnd1,
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              clkdv    => open,
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              clkfx    => sys_clk_in,
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              clkfx180 => open,
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              clk2x    => open,
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              clk2x180 => open,
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              clk0     => sys_clkfb_in,
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              clk90    => open,
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              clk180   => open,
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              clk270   => open,
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              locked   => locked,
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              psdone   => open,
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              status   => open);
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end;

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