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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [fep_toplevel_hans.vhd] - Blame information for rev 130

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1 105 davidgb
-- SECD Front End Processor derived from System09 written by John E. Kent
2
-- This core adheres to the GNU public license  
3
 
4
library ieee;
5
use ieee.std_logic_1164.all;
6
use IEEE.STD_LOGIC_ARITH.ALL;
7
use IEEE.STD_LOGIC_UNSIGNED.ALL;
8
use ieee.numeric_std.all;
9
--use config.all;
10
 
11
entity secd_fep_trenz is
12
  port(
13
    utmi_clkout      : in  Std_Logic;  -- UTMI Clock input
14
    utmi_databus16_8 : out Std_Logic;  -- UTMI configuration input
15
 
16
    reset_sw    : in  Std_logic;  -- Master Reset input (active low)
17
 
18
    -- PS/2 Keyboard
19
    ps2_clk1    : inout Std_logic;
20
    ps2_data1   : inout Std_Logic;
21
 
22
    -- Uart Interface
23
    fpga_rxd    : in  Std_Logic;
24
    fpga_txd    : out Std_Logic;
25
    fpga_cts    : in  Std_Logic;
26
    fpga_rts    : out Std_Logic;
27
 
28
    -- CRTC output signals
29
    vsync_b     : out Std_Logic;
30
    hsync_b     : out Std_Logic;
31
    fpga_b      : out Std_Logic_Vector(2 downto 0);
32
    fpga_g      : out Std_Logic_Vector(2 downto 0);
33
    fpga_r      : out Std_Logic_Vector(2 downto 0);
34
 
35
    -- LEDS & Switches
36
    mm_led      : out Std_Logic;
37
    led         : out Std_Logic_Vector(3 downto 0);
38
 
39
    joy_down    : in Std_Logic;
40
    joy_fire    : in Std_Logic;
41
    joy_left    : in Std_Logic;
42
    joy_right   : in Std_Logic;
43
    joy_up      : in Std_Logic;
44
 
45
    -- LCD Display
46
    lcd_e       : out Std_Logic;
47
    lcd_rw      : out Std_Logic;
48
    lcd_rs      : out Std_Logic;
49
    lcd_d       : out Std_Logic_Vector(3 downto 0);
50
 
51
    -- Audio
52
    aud_out     : out std_logic_vector(4 downto 1);
53
 
54
    -- Memory interface
55
    ram_a       : out std_logic_vector(20 downto 1);
56
    ram_io      : inout std_logic_vector(15 downto 0);
57
    ram_bhen    : out std_logic;
58
    ram_blen    : out std_logic;
59
    ram_cen     : out std_logic;
60
    ram_oen     : out std_logic;
61
    ram_wen     : out std_logic;
62
 
63
    -- Compact flash
64
    cf_reset    : out std_logic;
65
--    cf_irq      : in std_logic;
66
    cf_iord     : out std_logic;
67
    cf_iowr     : out std_logic;
68
--    cf_wait     : in std_logic;
69
--    cf_dasp     : in std_logic;
70
--    cf_pdiag    : in std_logic;
71
--    cf_cd1      : in std_logic;
72
--    cf_cd2      : in std_logic;
73
--    iois16      : in std_logic;
74
--    cf_oe       : out std_logic;
75
    cf_pwr_en   : out std_logic;
76
    cf_cs0      : out std_logic;
77
    cf_cs1      : out std_logic
78
--    cf_we       : out std_logic;
79
--    cf_rew      : out std_logic
80
    );
81
end secd_fep_trenz;
82
 
83
-------------------------------------------------------------------------------
84
-- Architecture for System09
85
-------------------------------------------------------------------------------
86
architecture rtl of secd_fep_trenz is
87
  -----------------------------------------------------------------------------
88
  -- constants
89
  -----------------------------------------------------------------------------
90
  constant fep_only             : integer := 1;
91
 
92
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
93
  constant VGA_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
94
  constant CPU_Clock_Frequency  : integer := 12500000;  -- CPU Clock
95
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
96
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
97
 
98
  -----------------------------------------------------------------------------
99
  -- ChipScope Pro components and signals
100
  -----------------------------------------------------------------------------
101
 
102
--  component icon
103
--    port(control0    :   out std_logic_vector(35 downto 0));
104
--  end component;
105
 
106
--  component ila
107
--    port(control     : in    std_logic_vector(35 downto 0);
108
--         clk         : in    std_logic;
109
--         trig0       : in    std_logic_vector(39 downto 0));
110
--  end component;
111
 
112
--  signal chipscope_control : std_logic_vector(35 downto 0);
113
--  signal ila_clock : std_logic;
114
 
115
  -----------------------------------------------------------------------------
116
  -- Signals
117
  -----------------------------------------------------------------------------
118
 
119
  -- Clocks
120
  attribute buffer_type                 : string;
121
  attribute period                      : string;
122
 
123
  signal vdu_clk                        : std_logic;      -- 25 Mhz
124
  attribute period of vdu_clk           : signal is "40 ns";
125
  attribute buffer_type of vdu_clk      : signal is "BUFG";
126
 
127
  signal cpu_clk                        : std_logic;      -- 12.5 Mhz
128
  attribute buffer_type of cpu_clk      : signal is "BUFG";
129
 
130
  -- BOOT ROM
131
  signal rom_cs        : Std_logic;
132
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
133
 
134
  -- RAM
135
  signal user_ram0_cs   : std_logic;
136
  signal user_ram0_dout : std_logic_vector(7 downto 0);
137
  signal user_ram1_cs   : std_logic;
138
  signal user_ram1_dout : std_logic_vector(7 downto 0);
139
 
140
  -- UART Interface signals
141
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
142
  signal uart_cs       : Std_Logic;
143
  signal uart_irq      : Std_Logic;
144
  signal baudclk       : Std_Logic;
145
  signal DCD_n         : Std_Logic;
146
  signal RTS_n         : Std_Logic;
147
  signal CTS_n         : Std_Logic;
148
 
149
  -- keyboard port
150
  signal keyboard_data_out : std_logic_vector(7 downto 0);
151
  signal keyboard_cs       : std_logic;
152
  signal keyboard_irq      : std_logic;
153
 
154
  -- CPU Interface signals
155
  signal cpu_rw       : std_logic;
156
  signal cpu_vma      : std_logic;
157
  signal cpu_halt     : std_logic;
158
  signal cpu_hold     : std_logic;
159
  signal cpu_firq     : std_logic;
160
  signal cpu_irq      : std_logic;
161
  signal cpu_nmi      : std_logic;
162
  signal cpu_addr     : std_logic_vector(15 downto 0);
163
  signal cpu_data_in  : std_logic_vector(7 downto 0);
164
  signal cpu_data_out : std_logic_vector(7 downto 0);
165
 
166
  -- Compact Flash port
167
  signal cf_data_out : std_logic_vector(7 downto 0);
168
  signal cf_cs       : std_logic;
169
  signal cf_rd       : std_logic;
170
  signal cf_wr       : std_logic;
171
 
172
  -- Video Display Unit
173
  signal vdu_cs       : std_logic;
174
  signal vdu_data_out : std_logic_vector(7 downto 0);
175
 
176
  -- VGA output signals (distributed to VGA DAC)
177
  signal red          : std_logic;
178
  signal green        : std_logic;
179
  signal blue         : std_logic;
180
 
181
  -- System Reset (generated by key press)
182
  signal reset        : std_logic;
183
 
184
  -- LCD register select
185
  signal lcd_cs       : std_logic;
186
 
187
  -- LED register select
188
  signal led_cs       : std_logic;
189
  signal led_reg      : std_logic_vector(7 downto 0) := (others => '0');
190
 
191
  -- Joystick buffer
192
  signal joystick     : std_logic_vector(7 downto 0);
193
 
194
  -- LED Flasher
195
  signal blink_count  : std_logic_vector(25 downto 0) := (others => '0');
196
 
197
  -- SECD interface
198
  signal secd_button           : std_logic := '0';
199
  signal secd_stop             : std_logic := '1';
200
  signal secd_stopped          : std_logic := '1';
201
  signal secd_state            : std_logic_vector(1 downto 0);
202
  signal secd_ram_addr_hi      : std_logic_vector(7 downto 0) := (others => '0');
203
  signal secd_ram_addr_high_cs : std_logic := '0';
204
  signal secd_ram_cs           : std_logic := '0';
205
  signal secd_control_cs       : std_logic := '0';
206
 
207
  -- SECD RAM Controller interface
208
  signal secd_ram_busy          : std_logic;
209
 
210
  -- RAM signal taps
211
  signal ram_bhenx : std_logic;
212
  signal ram_blenx : std_logic;
213
  signal ram_cenx : std_logic;
214
  signal ram_oenx : std_logic;
215
  signal ram_wenx : std_logic;
216
 
217
  -- Interface signals for SECD
218
  signal secd_ram_din32         : std_logic_vector(31 downto 0);
219
  signal secd_ram_dout32        : std_logic_vector(31 downto 0);
220
  signal secd_ram_addr32        : std_logic_vector(13 downto 0);
221
  signal secd_ram_read32        : std_logic;
222
  signal secd_ram_write32       : std_logic;
223
 
224
  -- Interface signals for 6809
225
  signal secd_ram_dout8         : std_logic_vector(7 downto 0);
226
  signal secd_ram_hold          : std_logic;
227
 
228
  -- Locked signal of clock synthesizer
229
  signal clock_locked           : std_logic;
230
  signal ila_clock              :std_logic;
231
-----------------------------------------------------------------
232
--
233
-- CPU09 CPU core
234
--
235
-----------------------------------------------------------------
236
 
237
  component cpu09
238
    port (
239
      clk      :        in  std_logic;
240
      rst      : in  std_logic;
241
      rw       :        out std_logic;          -- Asynchronous memory interface
242
      vma      :        out std_logic;
243
      address  : out std_logic_vector(15 downto 0);
244
      data_in  : in      std_logic_vector(7 downto 0);
245
      data_out : out std_logic_vector(7 downto 0);
246
      halt     : in  std_logic;
247
      hold     : in  std_logic;
248
      irq      : in  std_logic;
249
      nmi      : in  std_logic;
250
      firq     : in  std_logic
251
      );
252
  end component;
253
 
254
 
255
----------------------------------------
256
--
257
-- 16KByte Block RAM Mais Forth ROM
258
--
259
----------------------------------------
260
  component maisforth_rom_16k
261
    Port (
262
      clk      : in  std_logic;
263
      rst      : in  std_logic;
264
      cs       : in  std_logic;
265
      rw       : in  std_logic;
266
      addr     : in  std_logic_vector (13 downto 0);
267
      rdata    : out std_logic_vector (7 downto 0);
268
      wdata    : in  std_logic_vector (7 downto 0)
269
      );
270
  end component;
271
 
272
----------------------------------------
273
--
274
-- 8KBytes Block RAM for FLEX9
275
-- $C000 - $DFFF
276
--
277
----------------------------------------
278
  component ram_2k
279
    Port (
280
      clk      : in  std_logic;
281
      rst      : in  std_logic;
282
      cs       : in  std_logic;
283
      rw       : in  std_logic;
284
      addr     : in  std_logic_vector (12 downto 0);
285
      rdata    : out std_logic_vector (7 downto 0);
286
      wdata    : in  std_logic_vector (7 downto 0)
287
      );
288
  end component;
289
 
290
-----------------------------------------------------------------
291
--
292
-- Open Cores Mini UART
293
--
294
-----------------------------------------------------------------
295
 
296
  component ACIA_6850
297
    port (
298
      clk      : in  Std_Logic;  -- System Clock
299
      rst      : in  Std_Logic;  -- Reset input (active high)
300
      cs       : in  Std_Logic;  -- miniUART Chip Select
301
      rw       : in  Std_Logic;  -- Read / Not Write
302
      irq      : out Std_Logic;  -- Interrupt
303
      Addr     : in  Std_Logic;  -- Register Select
304
      DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
305
      DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
306
      RxC      : in  Std_Logic;  -- Receive Baud Clock
307
      TxC      : in  Std_Logic;  -- Transmit Baud Clock
308
      RxD      : in  Std_Logic;  -- Receive Data
309
      TxD      : out Std_Logic;  -- Transmit Data
310
      DCD_n    : in  Std_Logic;  -- Data Carrier Detect
311
      CTS_n    : in  Std_Logic;  -- Clear To Send
312
      RTS_n    : out Std_Logic   -- Request To send
313
      );
314
  end component;
315
 
316
-----------------------------------------------------------------
317
--
318
-- ACIA Clock divider
319
--
320
-----------------------------------------------------------------
321
 
322
  component ACIA_Clock
323
    generic (
324
      SYS_Clock_Frequency  : integer :=  VGA_Clock_Frequency;
325
      ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
326
      );
327
    port (
328
      clk      : in  Std_Logic;  -- System Clock Input
329
      ACIA_clk : out Std_logic   -- ACIA Clock output
330
      );
331
  end component;
332
 
333
 
334
----------------------------------------
335
--
336
-- PS/2 Keyboard
337
--
338
----------------------------------------
339
 
340
  component keyboard
341
    generic(
342
      KBD_Clock_Frequency : integer := CPU_Clock_Frequency
343
      );
344
    port(
345
      clk             : in    std_logic;
346
      rst             : in    std_logic;
347
      cs              : in    std_logic;
348
      rw              : in    std_logic;
349
      addr            : in    std_logic;
350
      data_in         : in    std_logic_vector(7 downto 0);
351
      data_out        : out   std_logic_vector(7 downto 0);
352
      irq             : out   std_logic;
353
      kbd_clk         : inout std_logic;
354
      kbd_data        : inout std_logic
355
      );
356
  end component;
357
 
358
----------------------------------------
359
--
360
-- Video Display Unit.
361
--
362
----------------------------------------
363
  component vdu8
364
    generic(
365
      VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
366
      VGA_CLOCK_FREQUENCY    : integer := VGA_Clock_Frequency; -- HZ
367
      VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
368
      VGA_VER_CHARS          : integer := 25; -- CHARACTERS
369
      VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
370
      VGA_LINES_PER_CHAR     : integer := 16; -- LINES
371
      VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
372
      VGA_HOR_SYNC           : integer := 96; -- PIXELS
373
      VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
374
      VGA_VER_BACK_PORCH     : integer := 13; -- LINES
375
      VGA_VER_SYNC           : integer := 1;  -- LINES
376
      VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
377
      );
378
    port(
379
      -- control register interface
380
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
381
      vdu_rst      : in  std_logic;
382
      vdu_cs       : in  std_logic;
383
      vdu_rw       : in  std_logic;
384
      vdu_addr     : in  std_logic_vector(2 downto 0);
385
      vdu_data_in  : in  std_logic_vector(7 downto 0);
386
      vdu_data_out : out std_logic_vector(7 downto 0);
387
 
388
      -- vga port connections
389
      vga_clk      : in  std_logic;     -- VGA Pixel Clock - 25 MHz
390
      vga_red_o    : out std_logic;
391
      vga_green_o  : out std_logic;
392
      vga_blue_o   : out std_logic;
393
      vga_hsync_o  : out std_logic;
394
      vga_vsync_o  : out std_logic
395
      );
396
  end component;
397
 
398
begin
399
 
400
  -----------------------------------------------------------------
401
  --
402
  -- ChipsScope Pro cores
403
  --
404
  -----------------------------------------------------------------
405
 
406
--  i_icon : icon
407
--    port map(control0  => chipscope_control);
408
--
409
--  i_ila : ila
410
--    port map(control => chipscope_control,
411
--             clk => ila_clock,
412
--             trig0(15 downto 8) => cpu_data_in,
413
--             trig0(23 downto 16) => cpu_data_out,
414
--             trig0(39 downto 24) => cpu_addr,
415
--             trig0(0) => cpu_clk,
416
--             trig0(1) => cpu_vma,
417
--             trig0(2) => ram_bhenx,
418
--             trig0(3) => ram_blenx,
419
--             trig0(4) => ram_cenx,
420
--             trig0(5) => ram_oenx,
421
--             trig0(6) => ram_wenx,
422
--             trig0(7) => vdu_clk);
423
 
424
  -----------------------------------------------------------------
425
  --
426
  -- CPU09 CPU core
427
  --
428
  -----------------------------------------------------------------
429
 
430
  my_cpu : entity cpu09 port map (
431
    clk       => cpu_clk,
432
    rst       => reset,
433
    rw        => cpu_rw,
434
    vma       => cpu_vma,
435
    address   => cpu_addr,
436
    data_in   => cpu_data_in,
437
    data_out  => cpu_data_out,
438
    halt      => cpu_halt,
439
    hold      => cpu_hold,
440
    irq       => cpu_irq,
441
    nmi       => cpu_nmi,
442
    firq      => cpu_firq
443
    );
444
 
445
  ----------------------------------------
446
  --
447
  -- Maisforth ROM (Xilinx Block RAM, 16k)
448
  --
449
  ----------------------------------------
450
 
451
  my_maisforth_rom_16k : entity maisforth_rom_16k port map (
452
    clk   => cpu_clk,
453
    rst   => reset,
454
    cs    => rom_cs,
455
    rw    => '1',
456
    addr  => cpu_addr(13 downto 0),
457
    rdata => rom_data_out,
458
    wdata => cpu_data_out
459
    );
460
 
461
  -----------------------------------------------------------------------------
462
  --
463
  -- Internal RAM (Xilinx Block RAM, 4k)
464
  --
465
  -----------------------------------------------------------------------------
466
 
467
  my_user_ram0_2k : entity ram_2k port map (
468
    clk   => cpu_clk,
469
    rst   => reset,
470
    cs    => user_ram0_cs,
471
    rw    => cpu_rw,
472
    addr  => cpu_addr(10 downto 0),
473
    rdata => user_ram0_dout,
474
    wdata => cpu_data_out
475
    );
476
 
477
  my_user_ram1_2k : entity ram_2k port map (
478
    clk   => cpu_clk,
479
    rst   => reset,
480
    cs    => user_ram1_cs,
481
    rw    => cpu_rw,
482
    addr  => cpu_addr(10 downto 0),
483
    rdata => user_ram1_dout,
484
    wdata => cpu_data_out
485
    );
486
 
487
  -----------------------------------------------------------------
488
  --
489
  -- 6850 ACIA
490
  --
491
  -----------------------------------------------------------------
492
 
493
  my_uart  : entity acia_6850 port map (
494
    clk      => cpu_clk,
495
    rst       => reset,
496
    cs        => uart_cs,
497
    rw        => cpu_rw,
498
    irq       => uart_irq,
499
    Addr      => cpu_addr(0),
500
    Datain    => cpu_data_out,
501
    DataOut   => uart_data_out,
502
    RxC       => baudclk,
503
    TxC       => baudclk,
504
    RxD       => fpga_rxd,
505
    TxD       => fpga_txd,
506
    DCD_n     => dcd_n,
507
    CTS_n     => fpga_cts,
508
    RTS_n     => fpga_rts
509
    );
510
 
511
 
512
----------------------------------------
513
--
514
-- PS/2 Keyboard Interface
515
--
516
----------------------------------------
517
  my_keyboard : keyboard
518
    generic map (
519
      KBD_Clock_Frequency => CPU_Clock_frequency
520
      )
521
    port map(
522
      clk          => cpu_clk,
523
      rst          => reset,
524
      cs           => keyboard_cs,
525
      rw           => cpu_rw,
526
      addr         => cpu_addr(0),
527
      data_in      => cpu_data_out(7 downto 0),
528
      data_out     => keyboard_data_out(7 downto 0),
529
      irq          => keyboard_irq,
530
      kbd_clk      => ps2_clk1,
531
      kbd_data     => ps2_data1
532
      );
533
 
534
----------------------------------------
535
--
536
-- Video Display Unit instantiation
537
--
538
----------------------------------------
539
  my_vdu : vdu8
540
    generic map(
541
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
542
      VGA_CLOCK_FREQUENCY    => VGA_Clock_Frequency, -- HZ
543
      VGA_HOR_CHARS          => 80, -- CHARACTERS
544
      VGA_VER_CHARS          => 25, -- CHARACTERS
545
      VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
546
      VGA_LINES_PER_CHAR     => 16, -- LINES
547
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
548
      VGA_HOR_SYNC           => 96, -- PIXELS
549
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
550
      VGA_VER_BACK_PORCH     => 13, -- LINES
551
      VGA_VER_SYNC           => 1,  -- LINES
552
      VGA_VER_FRONT_PORCH    => 36  -- LINES
553
      )
554
    port map(
555
 
556
      -- Control Registers
557
      vdu_clk       => cpu_clk,                                  -- 12.5 MHz System Clock in
558
      vdu_rst       => reset,
559
      vdu_cs        => vdu_cs,
560
      vdu_rw        => cpu_rw,
561
      vdu_addr      => cpu_addr(2 downto 0),
562
      vdu_data_in   => cpu_data_out,
563
      vdu_data_out  => vdu_data_out,
564
 
565
      -- vga port connections
566
      vga_clk       => vdu_clk,                                  -- 25 MHz VDU pixel clock
567
      vga_red_o     => red,
568
      vga_green_o   => green,
569
      vga_blue_o    => blue,
570
      vga_hsync_o   => hsync_b,
571
      vga_vsync_o   => vsync_b
572
      );
573
 
574
  ----------------------------------------
575
  --
576
  -- Clock Synthesis instantiation
577
  --
578
  ----------------------------------------
579
 
580
  my_clock_synthesis : entity clock_synthesis port map (
581
    clk_30mhz       => utmi_clkout,
582
    vdu_clk         => vdu_clk,
583
    cpu_clk         => cpu_clk,
584
    locked          => clock_locked );
585
--    clk_60mhz       => ila_clock);
586
 
587
--make_secd: if fep_only /= '1' generate
588
--  ----------------------------------------
589
--  --
590
--  -- SECD CPU instantiation
591
--  --
592
--  ----------------------------------------
593
--
594
--  my_secd_system : entity secd_system port map (
595
--    clk         => cpu_clk,
596
--    reset       => reset,
597
--    button      => secd_button,
598
--    ram_read    => secd_ram_read32,
599
--    ram_in      => secd_ram_dout32,
600
--    ram_write   => secd_ram_write32,
601
--    ram_out     => secd_ram_din32,
602
--    ram_a       => secd_ram_addr32,
603
--    ram_busy    => secd_ram_busy,
604
--    stop_input  => secd_stop,
605
--    stopped     => secd_stopped,
606
--    state       => secd_state
607
--    );
608
--end generate;
609
 
610
  ----------------------------------------
611
  --
612
  -- SECD RAM Controller instantiation
613
  --
614
  ----------------------------------------
615
 
616
  my_secd_ram : entity secd_ram_controller port map (
617
    clk                 => vdu_clk,
618
    reset               => reset,
619
    secd_stopped        => secd_stopped,
620
 
621
    -- SECD interface
622
    din32               => secd_ram_din32,
623
    dout32              => secd_ram_dout32,
624
    addr32              => secd_ram_addr32,
625
    read32_enable       => secd_ram_read32,
626
    write32_enable      => secd_ram_write32,
627
    busy32              => secd_ram_busy,
628
 
629
    -- 6809 interface
630
    clk8                => cpu_clk,
631
    din8                => cpu_data_out,
632
    dout8               => secd_ram_dout8,
633
    addr8(15 downto 8)  => secd_ram_addr_hi,
634
    addr8(7 downto 0)   => cpu_addr(7 downto 0),
635
    cs8_ram             => secd_ram_cs,
636
    rw8                 => cpu_rw,
637
    hold8               => secd_ram_hold,
638
 
639
    -- Compact Flash interface
640
    cs8_cf              => cf_cs,
641
 
642
    -- external interface
643
    ram_oen             => ram_oenx,
644
    ram_cen             => ram_cenx,
645
    ram_wen             => ram_wenx,
646
    ram_io        => ram_io,
647
    ram_a         => ram_a,
648
    ram_bhen            => ram_bhenx,
649
    ram_blen            => ram_blenx
650
    );
651
 
652
 
653
----------------------------------------
654
--
655
-- ACIA Clock
656
--
657
----------------------------------------
658
  my_ACIA_Clock : ACIA_Clock
659
    generic map(
660
      SYS_Clock_Frequency  => VGA_Clock_Frequency,
661
      ACIA_Clock_Frequency => ACIA_Clock_Frequency
662
      )
663
    port map(
664
      clk        => vdu_clk,
665
      acia_clk   => baudclk
666
      );
667
 
668
  ----------------------------------------------------------------------
669
  --
670
  -- Process to decode memory map
671
  --
672
  ----------------------------------------------------------------------
673
 
674
  mem_decode : process( cpu_addr, cpu_rw, cpu_vma,
675
                        rom_data_out,
676
                        user_ram0_dout,
677
                        user_ram1_dout,
678
                        uart_data_out,
679
                        keyboard_data_out,
680
                        joystick,
681
                        vdu_data_out,
682
                        cf_data_out,
683
                        cpu_data_out,
684
                        secd_state, secd_stopped, secd_ram_dout8, secd_ram_addr_hi )
685
 
686
  begin
687
    user_ram0_cs     <= '0';
688
    user_ram1_cs     <= '0';
689
    rom_cs           <= '0';
690
    uart_cs          <= '0';
691
    keyboard_cs      <= '0';
692
    vdu_cs           <= '0';
693
    cf_cs            <= '0';
694
    lcd_cs           <= '0';
695
    led_cs           <= '0';
696
    cpu_data_in      <= X"00";
697
 
698
    secd_control_cs       <= '0';
699
    secd_ram_cs           <= '0';
700
    secd_ram_addr_high_cs <= '0';
701
 
702
    case cpu_addr(15 downto 14) is
703
 
704
      -- Maisforth ROM - $C000 - $FFFF
705
      when "11" =>
706
        cpu_data_in     <= rom_data_out;
707
        rom_cs          <= cpu_vma;              -- read  ROM
708
 
709
        -- RAM - $0000-$3FFF
710
      when "00" =>
711
        case cpu_addr(13 downto 11) is
712
          when "000" =>
713
            cpu_data_in <= user_ram0_dout;
714
            user_ram0_cs <= cpu_vma;
715
 
716
          when "001" =>
717
            cpu_data_in <= user_ram1_dout;
718
            user_ram1_cs <= cpu_vma;
719
 
720
          when others =>
721
            cpu_data_in <= (others => '0');
722
 
723
        end case;
724
 
725
        -- Unmapped - $4000-$7FFF, read as FF
726
      when "01" =>
727
        cpu_data_in <= X"FF";
728
 
729
        -- I/O - $8000-$BFFF - Do additional decoding
730
      when "10" =>
731
        case cpu_addr(13 downto 8) is
732
 
733
          -- Real I/O $B000 - $B0FF
734
          when "110000" =>
735
            case cpu_addr(7 downto 4) is
736
 
737
              -- UART / ACIA $B000
738
              when X"0" =>
739
                cpu_data_in <= uart_data_out;
740
                uart_cs     <= cpu_vma;
741
 
742
                -- Keyboard port $B010 - $B01F
743
                -- Note in latest System09
744
                -- I have moved the Keyboard
745
                -- to $E020 to make way for the
746
                -- Floppy Disk Controller at $E01X
747
                -- JK. 10th Aug 07
748
              when X"1" =>
749
                cpu_data_in <= keyboard_data_out;
750
                keyboard_cs <= cpu_vma;
751
 
752
                -- VDU port $B020 - $B02F
753
                -- Note in latest System09
754
                -- I have moved the VDU to
755
                -- $E030 - JK. 10th Aug 07
756
              when X"2" =>
757
                cpu_data_in <= vdu_data_out;
758
                vdu_cs      <= cpu_vma;
759
 
760
                -- CF port $B040 - $B05F
761
                -- Note in latest System09
762
                -- I have moved the CF to
763
                -- $E040 - JK. 10th Aug 07
764
                                         -- However the Trenz TE0141
765
                                         -- must map the CF on 16 bit 
766
                                         -- word boundaries, so it has 
767
                                         -- to take 2 I/O slots
768
              when X"4" | X"5" =>
769
                cpu_data_in <= secd_ram_dout8;
770
                cf_cs       <= cpu_vma;
771
 
772
                -- Joystick $B0D0 (read only)
773
              when X"D" =>
774
                if cpu_addr(3 downto 0) = "0000" then
775
                  cpu_data_in <= joystick;
776
                end if;
777
 
778
                -- LED $B0E0 (write only)
779
              when X"E" =>
780
                if cpu_addr(3 downto 0) = "0000" then
781
                  led_cs <= cpu_vma;
782
                  cpu_data_in <= led_reg;
783
                end if;
784
 
785
                -- LCD Display $B0F0 (write only)
786
              when X"F" =>
787
                if cpu_addr(3 downto 0) = "0000" then
788
                  lcd_cs <= cpu_vma;
789
                end if;
790
 
791
              when others =>
792
                null;
793
            end case;
794
 
795
            -- SECD Control registers - $B100
796
          when "110001" =>
797
 
798
            case cpu_addr(7 downto 0) is
799
 
800
              -- $B140 -> SECD Status
801
              when X"40" =>
802
                secd_control_cs         <= cpu_vma;
803
                cpu_data_in(0)          <= secd_stopped;
804
                cpu_data_in(2 downto 1) <= secd_state;
805
 
806
                -- $B141 -> SECD Address High
807
              when X"41" =>
808
                secd_ram_addr_high_cs   <= cpu_vma;
809
                cpu_data_in             <= secd_ram_addr_hi;
810
 
811
              when others =>
812
                null;
813
 
814
            end case;
815
 
816
            -- SECD mapped memory page - $B200
817
          when "110010" =>
818
            cpu_data_in                 <= secd_ram_dout8;
819
            secd_ram_cs                 <= cpu_vma;
820
 
821
          when others =>
822
            null;
823
 
824
        end case;
825
 
826
      when others =>
827
        null;
828
 
829
    end case;
830
  end process;
831
 
832
--
833
-- Compact Flash Control
834
--
835
  compact_flash: process( reset_sw,
836
                          cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
837
                          cf_cs, cf_rd, cf_wr )
838
  begin
839
    cf_reset  <= reset_sw;
840
    cf_cs0    <= not( cf_cs ) or cpu_addr(4);
841
    cf_cs1    <= not( cf_cs and cpu_addr(4));
842
    cf_wr     <= cf_cs and (not cpu_rw);
843
    cf_rd     <= cf_cs and cpu_rw;
844
    cf_iowr   <= not cf_wr;
845
    cf_iord   <= not cf_rd;
846
    cf_pwr_en <= '0';
847
  end process;
848
 
849
 
850
--
851
-- Interrupts and other bus control signals
852
--
853
  interrupts : process( reset_sw, uart_irq, keyboard_irq, reset, joy_up, secd_ram_hold, secd_ram_cs )
854
  begin
855
    cpu_irq   <= keyboard_irq;
856
    cpu_nmi   <= not joy_up;
857
    cpu_firq  <= uart_irq;
858
    cpu_halt  <= '0';
859
    cpu_hold  <= secd_ram_hold;
860
  end process;
861
 
862
  --
863
  -- LCD write register
864
  --
865
  lcd_control : process(lcd_cs, cpu_clk, cpu_data_out)
866
  begin
867
    if falling_edge(cpu_clk) then
868
      if lcd_cs = '1' and cpu_rw = '0' then
869
        lcd_d     <= cpu_data_out(3 downto 0);
870
        lcd_e     <= cpu_data_out(4);
871
        lcd_rw    <= cpu_data_out(5);
872
        lcd_rs    <= cpu_data_out(6);
873
      end if;
874
    end if;
875
  end process;
876
 
877
  --
878
  -- LED write register
879
  --
880
  led_control : process(led_reg, led_cs, cpu_clk, cpu_data_out)
881
  begin
882
    if reset = '1' then
883
      led_reg <= (others => '1');
884
    elsif falling_edge(cpu_clk) then
885
      if led_cs = '1' and cpu_rw = '0' then
886
        led_reg <= cpu_data_out;
887
      end if;
888
    end if;
889
 
890
  end process;
891
 
892
  led <= led_reg(3 downto 0);
893
 
894
  -- SECD control register
895
  --
896
  secd_control : process(secd_control_cs, cpu_clk, cpu_data_out)
897
  begin
898
    if falling_edge(cpu_clk) then
899
      if secd_control_cs = '1' and cpu_rw = '0' then
900
        secd_stop   <= cpu_data_out(0);
901
        secd_button <= cpu_data_out(1);
902
      end if;
903
    end if;
904
  end process;
905
 
906
  --
907
  -- SECD RAM Adressing
908
  --
909
 
910
  secd_ram_addressing_high : process(cpu_clk, cpu_rw, cpu_data_out, secd_ram_addr_high_cs)
911
  begin
912
    if falling_edge(cpu_clk) then
913
      if cpu_rw = '0' and secd_ram_addr_high_cs = '1' then
914
        secd_ram_addr_hi <= cpu_data_out;
915
      end if;
916
    end if;
917
  end process;
918
 
919
  --
920
  -- Joystick register
921
  --
922
  read_joystick : process(cpu_clk, joy_up, joy_right, joy_down, joy_left, joy_fire)
923
  begin
924
    if rising_edge(cpu_clk) then
925
      joystick(0) <= joy_up;
926
      joystick(1) <= joy_right;
927
      joystick(2) <= joy_down;
928
      joystick(3) <= joy_left;
929
      joystick(4) <= joy_fire;
930
      joystick(7 downto 5) <= (others => '0');
931
    end if;
932
  end process;
933
 
934
--
935
-- LED Flasher
936
--
937
  my_led_flasher: process(vdu_clk, reset, blink_count)
938
  begin
939
    if reset = '1' then
940
      blink_count <= (others => '0');
941
    elsif rising_edge(vdu_clk) then
942
      blink_count <= blink_count + 1;
943
    end if;
944
 
945
    mm_led <= blink_count(25);
946
 
947
  end process;
948
 
949
-- Set UART DCD to always true
950
  DCD_n <= '0';
951
 
952
--
953
-- Feed RGB DAC
954
--
955
  fpga_r(0) <= red;
956
  fpga_r(1) <= red;
957
  fpga_r(2) <= red;
958
  fpga_g(0) <= green;
959
  fpga_g(1) <= green;
960
  fpga_g(2) <= green;
961
  fpga_b(0) <= blue;
962
  fpga_b(1) <= blue;
963
  fpga_b(2) <= blue;
964
 
965
  -- set USB PHY to 16 bit mode so that it generates a 30 Mhz Clock
966
  utmi_databus16_8 <= '1';
967
 
968
  -- Hold system in reset until the clock is locked or when the reset
969
  -- key is pressed.
970
  reset     <= not reset_sw or not clock_locked;
971
 
972
  aud_out <= (others => '0');
973
 
974
  ram_bhen <= ram_bhenx;
975
  ram_blen <= ram_blenx;
976
  ram_cen <= ram_cenx;
977
  ram_oen <= ram_oenx;
978
  ram_wen <= ram_wenx;
979
 
980
  secd_ram_din32 <= (others => '0');
981
  secd_ram_addr32       <= (others => '0');
982
  secd_ram_read32 <= '0';
983
  secd_ram_write32 <= '0';
984
 
985
end;
986
 

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