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[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [ram_controller.vhd] - Blame information for rev 118

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Line No. Rev Author Line
1 105 davidgb
--
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-- ram_controller.vhd
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity ram_controller is
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  port(
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    reset      : in std_logic;
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         clk        : in std_logic;
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    cs_ram     : in std_logic;
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    rw         : in std_logic;
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    din        : in std_logic_vector(7 downto 0);
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    dout       : out std_logic_vector(7 downto 0);
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    addr       : in std_logic_vector(19 downto 0);
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    -- External interface
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    ram_oen    : out   std_logic;
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    ram_cen    : out   std_logic;
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    ram_wen    : out   std_logic;
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    ram_io     : inout std_logic_vector(15 downto 0);
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    ram_a      : out   std_logic_vector(20 downto 1);
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    ram_bhen   : out   std_logic;
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    ram_blen   : out   std_logic
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  );
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end;
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architecture external_ram of ram_controller is
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signal we : std_logic;
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begin
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--
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-- 1M byte SRAM Control
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-- Processes to read and write memory based on bus signals
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-- Uses bhe/ble controlled write 
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-- so that clock stretching can be performed on the CF
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--
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ram_process: process( clk, addr, rw,
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                                               cs_ram, ram_io, din )
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begin
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         ram_wen  <=     rw;
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         ram_oen  <= not rw;
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    ram_cen  <= not cs_ram;
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    ram_bhen <= not( (not addr(0)) and clk );
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    ram_blen <= not(      addr(0)  and clk );
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         ram_a(20) <= '0';
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         ram_a(19 downto 1) <= addr(19 downto 1);
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    if (rw = '0') and (addr(0) = '0') then
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                ram_io(15 downto 8) <= din;
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         else
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      ram_io(15 downto 8)  <= "ZZZZZZZZ";
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         end if;
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    if (rw = '0') and (addr(0) = '1') then
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                ram_io(7 downto 0) <= din;
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         else
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      ram_io(7 downto 0)  <= "ZZZZZZZZ";
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         end if;
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         if addr(0) = '0' then
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      dout <= ram_io(15 downto 8);
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    else
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      dout <= ram_io(7 downto 0);
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    end if;
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end process;
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end;

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