OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Trenz_TE0141/] [ram_controller.vhd] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 105 davidgb
--
2
-- ram_controller.vhd
3
--
4
 
5
library ieee;
6
 
7
use ieee.std_logic_1164.all;
8
use ieee.numeric_std.all;
9
use ieee.std_logic_unsigned.all;
10
 
11
entity ram_controller is
12
  port(
13
    reset      : in std_logic;
14
         clk        : in std_logic;
15
    cs_ram     : in std_logic;
16
    rw         : in std_logic;
17
    din        : in std_logic_vector(7 downto 0);
18
    dout       : out std_logic_vector(7 downto 0);
19
    addr       : in std_logic_vector(19 downto 0);
20
 
21
    -- External interface
22
    ram_oen    : out   std_logic;
23
    ram_cen    : out   std_logic;
24
    ram_wen    : out   std_logic;
25
    ram_io     : inout std_logic_vector(15 downto 0);
26
    ram_a      : out   std_logic_vector(20 downto 1);
27
    ram_bhen   : out   std_logic;
28
    ram_blen   : out   std_logic
29
  );
30
end;
31
 
32
architecture external_ram of ram_controller is
33
 
34
signal we : std_logic;
35
 
36
begin
37
 
38
--
39
-- 1M byte SRAM Control
40
-- Processes to read and write memory based on bus signals
41
-- Uses bhe/ble controlled write 
42
-- so that clock stretching can be performed on the CF
43
--
44
ram_process: process( clk, addr, rw,
45
                                               cs_ram, ram_io, din )
46
begin
47
         ram_wen  <=     rw;
48
         ram_oen  <= not rw;
49
    ram_cen  <= not cs_ram;
50
    ram_bhen <= not( (not addr(0)) and clk );
51
    ram_blen <= not(      addr(0)  and clk );
52
 
53
         ram_a(20) <= '0';
54
         ram_a(19 downto 1) <= addr(19 downto 1);
55
 
56
    if (rw = '0') and (addr(0) = '0') then
57
                ram_io(15 downto 8) <= din;
58
         else
59
      ram_io(15 downto 8)  <= "ZZZZZZZZ";
60
         end if;
61
 
62
    if (rw = '0') and (addr(0) = '1') then
63
                ram_io(7 downto 0) <= din;
64
         else
65
      ram_io(7 downto 0)  <= "ZZZZZZZZ";
66
         end if;
67
 
68
         if addr(0) = '0' then
69
      dout <= ram_io(15 downto 8);
70
    else
71
      dout <= ram_io(7 downto 0);
72
    end if;
73
end process;
74
 
75
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.