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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XSA-3S1000/] [sdramcntl.vhd] - Blame information for rev 59

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1 59 davidgb
library IEEE, UNISIM;
2
use IEEE.std_logic_1164.all;
3
 
4
package sdram is
5
 
6
  -- SDRAM controller
7
  component sdramCntl
8
    generic(
9
      FREQ                 :     natural := 100_000;  -- operating frequency in KHz
10
      IN_PHASE             :     boolean := true;  -- SDRAM and controller work on same or opposite clock edge
11
      PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
12
      MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
13
      MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
14
      DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
15
      NROWS                :     natural := 8192;  -- number of rows in SDRAM array
16
      NCOLS                :     natural := 512;  -- number of columns in SDRAM array
17
      HADDR_WIDTH          :     natural := 24;  -- host-side address width
18
      SADDR_WIDTH          :     natural := 13  -- SDRAM-side address width
19
      );
20
    port(
21
      -- host side
22
      clk                  : in  std_logic;  -- master clock
23
      lock                 : in  std_logic;  -- true if clock is stable
24
      rst                  : in  std_logic;  -- reset
25
      rd                   : in  std_logic;  -- initiate read operation
26
      wr                   : in  std_logic;  -- initiate write operation
27
      earlyOpBegun         : out std_logic;  -- read/write/self-refresh op has begun (async)
28
      opBegun              : out std_logic;  -- read/write/self-refresh op has begun (clocked)
29
      rdPending            : out std_logic;  -- true if read operation(s) are still in the pipeline
30
      done                 : out std_logic;  -- read or write operation is done
31
      rdDone               : out std_logic;  -- read operation is done and data is available
32
      hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host to SDRAM
33
      hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host       to SDRAM
34
      hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from SDRAM to host
35
      status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
36
      -- SDRAM side
37
      cke                  : out std_logic;  -- clock-enable to SDRAM
38
      ce_n                 : out std_logic;  -- chip-select to SDRAM
39
      ras_n                : out std_logic;  -- SDRAM row address strobe
40
      cas_n                : out std_logic;  -- SDRAM column address strobe
41
      we_n                 : out std_logic;  -- SDRAM write enable
42
      ba                   : out std_logic_vector(1 downto 0);  -- SDRAM bank address
43
      sAddr                : out std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
44
      sDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from SDRAM
45
      sDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to SDRAM
46
      sDOutEn              : out std_logic;  -- true if data is output to SDRAM on sDOut
47
      dqmh                 : out std_logic;  -- enable upper-byte of SDRAM databus if true
48
      dqml                 : out std_logic  -- enable lower-byte of SDRAM databus if true
49
      );
50
  end component;
51
 
52
  -- dual-port interface to the SDRAM controller
53
  component dualport
54
    generic(
55
      PIPE_EN         :    boolean                       := false;  -- enable pipelined read operations
56
      PORT_TIME_SLOTS :    std_logic_vector(15 downto 0) := "1111000011110000";
57
      DATA_WIDTH      :    natural                       := 16;  -- host & SDRAM data width
58
      HADDR_WIDTH     :    natural                       := 23  -- host-side address width
59
      );
60
    port(
61
      clk             : in std_logic;   -- master clock
62
 
63
      -- host-side port 0
64
      rst0          : in  std_logic;    -- reset
65
      rd0           : in  std_logic;    -- initiate read operation
66
      wr0           : in  std_logic;    -- initiate write operation
67
      earlyOpBegun0 : out std_logic;    -- read/write op has begun (async)
68
      opBegun0      : out std_logic;    -- read/write op has begun (clocked)
69
      rdPending0    : out std_logic;    -- true if read operation(s) are still in the pipeline
70
      done0         : out std_logic;    -- read or write operation is done
71
      rdDone0       : out std_logic;    -- read operation is done and data is available
72
      hAddr0        : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host to SDRAM
73
      hDIn0         : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host to SDRAM
74
      hDOut0        : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from SDRAM to host
75
      status0       : out std_logic_vector(3 downto 0);  -- diagnostic status of the SDRAM controller FSM         
76
 
77
      -- host-side port 1
78
      rst1          : in  std_logic;
79
      rd1           : in  std_logic;
80
      wr1           : in  std_logic;
81
      earlyOpBegun1 : out std_logic;
82
      opBegun1      : out std_logic;
83
      rdPending1    : out std_logic;
84
      done1         : out std_logic;
85
      rdDone1       : out std_logic;
86
      hAddr1        : in  std_logic_vector(HADDR_WIDTH-1 downto 0);
87
      hDIn1         : in  std_logic_vector(DATA_WIDTH-1 downto 0);
88
      hDOut1        : out std_logic_vector(DATA_WIDTH-1 downto 0);
89
      status1       : out std_logic_vector(3 downto 0);
90
 
91
      -- SDRAM controller port
92
      rst          : out std_logic;
93
      rd           : out std_logic;
94
      wr           : out std_logic;
95
      earlyOpBegun : in  std_logic;
96
      opBegun      : in  std_logic;
97
      rdPending    : in  std_logic;
98
      done         : in  std_logic;
99
      rdDone       : in  std_logic;
100
      hAddr        : out std_logic_vector(HADDR_WIDTH-1 downto 0);
101
      hDIn         : out std_logic_vector(DATA_WIDTH-1 downto 0);
102
      hDOut        : in  std_logic_vector(DATA_WIDTH-1 downto 0);
103
      status       : in  std_logic_vector(3 downto 0)
104
      );
105
  end component;
106
 
107
end package sdram;
108
 
109
 
110
 
111
 
112
--------------------------------------------------------------------
113
-- Company : XESS Corp.
114
-- Engineer : Dave Vanden Bout
115
-- Creation Date : 05/17/2005
116
-- Copyright : 2005, XESS Corp
117
-- Tool Versions : WebPACK 6.3.03i
118
--
119
-- Description:
120
-- SDRAM controller
121
--
122
-- Revision:
123
-- 1.4.0
124
--
125
-- Additional Comments:
126
-- 1.4.0:
127
-- Added generic parameter to enable/disable independent active rows in each bank.
128
-- 1.3.0:
129
-- Modified to allow independently active rows in each bank.
130
-- 1.2.0:
131
-- Modified to allow pipelining of read/write operations.
132
-- 1.1.0:
133
-- Initial release.
134
--
135
-- License:
136
-- This code can be freely distributed and modified as long as
137
-- this header is not removed.
138
--------------------------------------------------------------------
139
 
140
library IEEE, UNISIM;
141
use IEEE.std_logic_1164.all;
142
use IEEE.std_logic_unsigned.all;
143
use IEEE.numeric_std.all;
144
use WORK.common.all;
145
 
146
entity sdramCntl is
147
  generic(
148
    FREQ                 :     natural := 100_000;  -- operating frequency in KHz
149
    IN_PHASE             :     boolean := true;  -- SDRAM and controller work on same or opposite clock edge
150
    PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
151
    MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
152
    MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
153
    DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
154
    NROWS                :     natural := 8192;  -- number of rows in SDRAM array
155
    NCOLS                :     natural := 512;  -- number of columns in SDRAM array
156
    HADDR_WIDTH          :     natural := 24;  -- host-side address width
157
    SADDR_WIDTH          :     natural := 13  -- SDRAM-side address width
158
    );
159
  port(
160
    -- host side
161
    clk                  : in  std_logic;  -- master clock
162
    lock                 : in  std_logic;  -- true if clock is stable
163
    rst                  : in  std_logic;  -- reset
164
    rd                   : in  std_logic;  -- initiate read operation
165
    wr                   : in  std_logic;  -- initiate write operation
166
    earlyOpBegun         : out std_logic;  -- read/write/self-refresh op has begun (async)
167
    opBegun              : out std_logic;  -- read/write/self-refresh op has begun (clocked)
168
    rdPending            : out std_logic;  -- true if read operation(s) are still in the pipeline
169
    done                 : out std_logic;  -- read or write operation is done
170
    rdDone               : out std_logic;  -- read operation is done and data is available
171
    hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host to SDRAM
172
    hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host       to SDRAM
173
    hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from SDRAM to host
174
    status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
175
 
176
    -- SDRAM side
177
    cke     : out std_logic;            -- clock-enable to SDRAM
178
    ce_n    : out std_logic;            -- chip-select to SDRAM
179
    ras_n   : out std_logic;            -- SDRAM row address strobe
180
    cas_n   : out std_logic;            -- SDRAM column address strobe
181
    we_n    : out std_logic;            -- SDRAM write enable
182
    ba      : out std_logic_vector(1 downto 0);  -- SDRAM bank address
183
    sAddr   : out std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
184
    sDIn    : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from SDRAM
185
    sDOut   : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to SDRAM
186
    sDOutEn : out std_logic;            -- true if data is output to SDRAM on sDOut
187
    dqmh    : out std_logic;            -- enable upper-byte of SDRAM databus if true
188
    dqml    : out std_logic             -- enable lower-byte of SDRAM databus if true
189
    );
190
end sdramCntl;
191
 
192
 
193
 
194
architecture arch of sdramCntl is
195
 
196
  constant OUTPUT : std_logic := '1';   -- direction of dataflow w.r.t. this controller
197
  constant INPUT  : std_logic := '0';
198
  constant NOP    : std_logic := '0';   -- no operation
199
  constant READ   : std_logic := '1';   -- read operation
200
  constant WRITE  : std_logic := '1';   -- write operation
201
 
202
  -- SDRAM timing parameters
203
  constant Tinit : natural := 200;      -- min initialization interval (us)
204
  constant Tras  : natural := 45;       -- min interval between active to precharge commands (ns)
205
  constant Trcd  : natural := 20;       -- min interval between active and R/W commands (ns)
206
  constant Tref  : natural := 64_000_000;  -- maximum refresh interval (ns)
207
  constant Trfc  : natural := 66;       -- duration of refresh operation (ns)
208
  constant Trp   : natural := 20;       -- min precharge command duration (ns)
209
  constant Twr   : natural := 15;       -- write recovery time (ns)
210
  constant Txsr  : natural := 75;       -- exit self-refresh time (ns)
211
 
212
  -- SDRAM timing parameters converted into clock cycles (based on FREQ)
213
  constant NORM        : natural := 1_000_000;  -- normalize ns * KHz
214
  constant INIT_CYCLES : natural := 1+((Tinit*FREQ)/1000);  -- SDRAM power-on initialization interval
215
  constant RAS_CYCLES  : natural := 1+((Tras*FREQ)/NORM);  -- active-to-precharge interval
216
  constant RCD_CYCLES  : natural := 1+((Trcd*FREQ)/NORM);  -- active-to-R/W interval
217
  constant REF_CYCLES  : natural := 1+(((Tref/NROWS)*FREQ)/NORM);  -- interval between row refreshes
218
  constant RFC_CYCLES  : natural := 1+((Trfc*FREQ)/NORM);  -- refresh operation interval
219
  constant RP_CYCLES   : natural := 1+((Trp*FREQ)/NORM);  -- precharge operation interval
220
  constant WR_CYCLES   : natural := 1+((Twr*FREQ)/NORM);  -- write recovery time
221
  constant XSR_CYCLES  : natural := 1+((Txsr*FREQ)/NORM);  -- exit self-refresh time
222
  constant MODE_CYCLES : natural := 2;  -- mode register setup time
223
  constant CAS_CYCLES  : natural := 3;  -- CAS latency
224
  constant RFSH_OPS    : natural := 8;  -- number of refresh operations needed to init SDRAM
225
 
226
  -- timer registers that count down times for various SDRAM operations
227
  signal timer_r, timer_x       : natural range 0 to INIT_CYCLES;  -- current SDRAM op time
228
  signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES;  -- active-to-precharge time
229
  signal wrTimer_r, wrTimer_x   : natural range 0 to WR_CYCLES;  -- write-to-precharge time
230
  signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES;  -- time between row refreshes
231
  signal rfshCntr_r, rfshCntr_x : natural range 0 to NROWS;  -- counts refreshes that are neede
232
  signal nopCntr_r, nopCntr_x   : natural range 0 to MAX_NOP;  -- counts consecutive NOP operations
233
 
234
  signal doSelfRfsh : std_logic;        -- active when the NOP counter hits zero and self-refresh can start
235
 
236
  -- states of the SDRAM controller state machine
237
  type cntlState is (
238
    INITWAIT,                           -- initialization - waiting for power-on initialization to complete
239
    INITPCHG,                           -- initialization - initial precharge of SDRAM banks
240
    INITSETMODE,                        -- initialization - set SDRAM mode
241
    INITRFSH,                           -- initialization - do initial refreshes
242
    RW,                                 -- read/write/refresh the SDRAM
243
    ACTIVATE,                           -- open a row of the SDRAM for reading/writing
244
    REFRESHROW,                         -- refresh a row of the SDRAM
245
    SELFREFRESH                         -- keep SDRAM in self-refresh mode with CKE low
246
    );
247
  signal state_r, state_x : cntlState;  -- state register and next state
248
 
249
  -- commands that are sent to the SDRAM to make it perform certain operations
250
  -- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml)
251
  subtype sdramCmd is unsigned(5 downto 0);
252
  constant NOP_CMD    : sdramCmd := "011100";
253
  constant ACTIVE_CMD : sdramCmd := "001100";
254
  constant READ_CMD   : sdramCmd := "010100";
255
  constant WRITE_CMD  : sdramCmd := "010000";
256
  constant PCHG_CMD   : sdramCmd := "001011";
257
  constant MODE_CMD   : sdramCmd := "000011";
258
  constant RFSH_CMD   : sdramCmd := "000111";
259
 
260
  -- SDRAM mode register
261
  -- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS
262
  subtype sdramMode is std_logic_vector(12 downto 0);
263
  constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000";
264
 
265
  -- the host address is decomposed into these sets of SDRAM address components
266
  constant ROW_LEN : natural := log2(NROWS);  -- number of row address bits
267
  constant COL_LEN : natural := log2(NCOLS);  -- number of column address bits
268
  signal   bank    : std_logic_vector(ba'range);  -- bank address bits
269
  signal   row     : std_logic_vector(ROW_LEN - 1 downto 0);  -- row address within bank
270
  signal   col     : std_logic_vector(sAddr'range);  -- column address within row
271
 
272
  -- registers that store the currently active row in each bank of the SDRAM
273
  constant NUM_ACTIVE_ROWS            : integer := int_select(MULTIPLE_ACTIVE_ROWS = false, 1, 2**ba'length);
274
  type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range);
275
  signal   activeRow_r, activeRow_x   : activeRowType;
276
  signal   activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1);  -- indicates that some row in a bank is active
277
  signal   bankIndex                  : natural range 0 to NUM_ACTIVE_ROWS-1;  -- bank address bits
278
  signal   activeBank_r, activeBank_x : std_logic_vector(ba'range);  -- indicates the bank with the active row
279
  signal   doActivate                 : std_logic;  -- indicates when a new row in a bank needs to be activated
280
 
281
  -- there is a command bit embedded within the SDRAM column address
282
  constant CMDBIT_POS    : natural   := 10;  -- position of command bit
283
  constant AUTO_PCHG_ON  : std_logic := '1';  -- CMDBIT value to auto-precharge the bank
284
  constant AUTO_PCHG_OFF : std_logic := '0';  -- CMDBIT value to disable auto-precharge
285
  constant ONE_BANK      : std_logic := '0';  -- CMDBIT value to select one bank
286
  constant ALL_BANKS     : std_logic := '1';  -- CMDBIT value to select all banks
287
 
288
  -- status signals that indicate when certain operations are in progress
289
  signal wrInProgress       : std_logic;  -- write operation in progress
290
  signal rdInProgress       : std_logic;  -- read operation in progress
291
  signal activateInProgress : std_logic;  -- row activation is in progress
292
 
293
  -- these registers track the progress of read and write operations
294
  signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0);  -- pipeline of read ops in progress
295
  signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0);  -- pipeline of write ops (only need 1 cycle)
296
 
297
  -- registered outputs to host
298
  signal opBegun_r, opBegun_x             : std_logic;  -- true when SDRAM read or write operation is started
299
  signal hDOut_r, hDOut_x                 : std_logic_vector(hDOut'range);  -- holds data read from SDRAM and sent to the host
300
  signal hDOutOppPhase_r, hDOutOppPhase_x : std_logic_vector(hDOut'range);  -- holds data read from SDRAM   on opposite clock edge
301
 
302
  -- registered outputs to SDRAM
303
  signal cke_r, cke_x           : std_logic;  -- clock enable 
304
  signal cmd_r, cmd_x           : sdramCmd;  -- SDRAM command bits
305
  signal ba_r, ba_x             : std_logic_vector(ba'range);  -- SDRAM bank address bits
306
  signal sAddr_r, sAddr_x       : std_logic_vector(sAddr'range);  -- SDRAM row/column address
307
  signal sData_r, sData_x       : std_logic_vector(sDOut'range);  -- SDRAM out databus
308
  signal sDataDir_r, sDataDir_x : std_logic;  -- SDRAM databus direction control bit
309
 
310
begin
311
 
312
  -----------------------------------------------------------
313
  -- attach some internal signals to the I/O ports 
314
  -----------------------------------------------------------
315
 
316
  -- attach registered SDRAM control signals to SDRAM input pins
317
  (ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r;  -- SDRAM operation control bits
318
  cke                                    <= cke_r;  -- SDRAM clock enable
319
  ba                                     <= ba_r;  -- SDRAM bank address
320
  sAddr                                  <= sAddr_r;  -- SDRAM address
321
  sDOut                                  <= sData_r;  -- SDRAM output data bus
322
  sDOutEn                                <= YES when sDataDir_r = OUTPUT else NO;  -- output databus enable
323
 
324
  -- attach some port signals
325
  hDOut   <= hDOut_r;                   -- data back to host
326
  opBegun <= opBegun_r;                 -- true if requested operation has begun
327
 
328
 
329
  -----------------------------------------------------------
330
  -- compute the next state and outputs 
331
  -----------------------------------------------------------
332
 
333
  combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r, opBegun_x,
334
                          activeFlag_r, activeRow_r, rdPipeline_r, wrPipeline_r,
335
                          hDOutOppPhase_r, nopCntr_r, lock, rfshCntr_r, timer_r, rasTimer_r,
336
                          wrTimer_r, refTimer_r, cmd_r, cke_r, activeBank_r, ba_r )
337
  begin
338
 
339
    -----------------------------------------------------------
340
    -- setup default values for signals 
341
    -----------------------------------------------------------
342
 
343
    opBegun_x    <= NO;                 -- no operations have begun
344
    earlyOpBegun <= opBegun_x;
345
    cke_x        <= YES;                -- enable SDRAM clock
346
    cmd_x        <= NOP_CMD;            -- set SDRAM command to no-operation
347
    sDataDir_x   <= INPUT;              -- accept data from the SDRAM
348
    sData_x      <= hDIn(sData_x'range);  -- output data from host to SDRAM
349
    state_x      <= state_r;            -- reload these registers and flags
350
    activeFlag_x <= activeFlag_r;       --              with their existing values
351
    activeRow_x  <= activeRow_r;
352
    activeBank_x <= activeBank_r;
353
    rfshCntr_x   <= rfshCntr_r;
354
 
355
    -----------------------------------------------------------
356
    -- setup default value for the SDRAM address 
357
    -----------------------------------------------------------
358
 
359
    -- extract bank field from host address
360
    ba_x                    <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN);
361
    if MULTIPLE_ACTIVE_ROWS = true then
362
      bank                  <= (others => '0');
363
      bankIndex             <= CONV_INTEGER(ba_x);
364
    else
365
      bank                  <= ba_x;
366
      bankIndex             <= 0;
367
    end if;
368
    -- extract row, column fields from host address
369
    row                     <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN);
370
    -- extend column (if needed) until it is as large as the (SDRAM address bus - 1)
371
    col                     <= (others => '0');  -- set it to all zeroes
372
    col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0);
373
    -- by default, set SDRAM address to the column address with interspersed
374
    -- command bit set to disable auto-precharge
375
    sAddr_x                 <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF
376
                               & col(CMDBIT_POS-1 downto 0);
377
 
378
    -----------------------------------------------------------
379
    -- manage the read and write operation pipelines
380
    -----------------------------------------------------------
381
 
382
    -- determine if read operations are in progress by the presence of
383
    -- READ flags in the read pipeline 
384
    if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then
385
      rdInProgress <= YES;
386
    else
387
      rdInProgress <= NO;
388
    end if;
389
    rdPending      <= rdInProgress;     -- tell the host if read operations are in progress
390
 
391
    -- enter NOPs into the read and write pipeline shift registers by default
392
    rdPipeline_x    <= NOP & rdPipeline_r(rdPipeline_r'high downto 1);
393
    wrPipeline_x(0) <= NOP;
394
 
395
    -- transfer data from SDRAM to the host data register if a read flag has exited the pipeline
396
    -- (the transfer occurs 1 cycle before we tell the host the read operation is done)
397
    if rdPipeline_r(1) = READ then
398
      hDOutOppPhase_x <= sDIn(hDOut'range);  -- gets value on the SDRAM databus on the opposite phase
399
      if IN_PHASE then
400
        -- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase
401
        hDOut_x       <= sDIn(hDOut'range);
402
      else
403
        -- otherwise get the SDRAM data that was gathered on the previous opposite clock edge
404
        hDOut_x       <= hDOutOppPhase_r(hDOut'range);
405
      end if;
406
    else
407
      -- retain contents of host data registers if no data from the SDRAM has arrived yet
408
      hDOutOppPhase_x <= hDOutOppPhase_r;
409
      hDOut_x         <= hDOut_r;
410
    end if;
411
 
412
    done   <= rdPipeline_r(0) or wrPipeline_r(0);  -- a read or write operation is done
413
    rdDone <= rdPipeline_r(0);          -- SDRAM data available when a READ flag exits the pipeline 
414
 
415
    -----------------------------------------------------------
416
    -- manage row activation
417
    -----------------------------------------------------------
418
 
419
    -- request a row activation operation if the row of the current address
420
    -- does not match the currently active row in the bank, or if no row
421
    -- in the bank is currently active
422
    if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then
423
      doActivate <= YES;
424
    else
425
      doActivate <= NO;
426
    end if;
427
 
428
    -----------------------------------------------------------
429
    -- manage self-refresh
430
    -----------------------------------------------------------
431
 
432
    -- enter self-refresh if neither a read or write is requested for MAX_NOP consecutive cycles.
433
    if (rd = YES) or (wr = YES) then
434
      -- any read or write resets NOP counter and exits self-refresh state
435
      nopCntr_x  <= 0;
436
      doSelfRfsh <= NO;
437
    elsif nopCntr_r /= MAX_NOP then
438
      -- increment NOP counter whenever there is no read or write operation 
439
      nopCntr_x  <= nopCntr_r + 1;
440
      doSelfRfsh <= NO;
441
    else
442
      -- start self-refresh when counter hits maximum NOP count and leave counter unchanged
443
      nopCntr_x  <= nopCntr_r;
444
      doSelfRfsh <= YES;
445
    end if;
446
 
447
    -----------------------------------------------------------
448
    -- update the timers 
449
    -----------------------------------------------------------
450
 
451
    -- row activation timer
452
    if rasTimer_r /= 0 then
453
      -- decrement a non-zero timer and set the flag
454
      -- to indicate the row activation is still inprogress
455
      rasTimer_x         <= rasTimer_r - 1;
456
      activateInProgress <= YES;
457
    else
458
      -- on timeout, keep the timer at zero     and reset the flag
459
      -- to indicate the row activation operation is done
460
      rasTimer_x         <= rasTimer_r;
461
      activateInProgress <= NO;
462
    end if;
463
 
464
    -- write operation timer            
465
    if wrTimer_r /= 0 then
466
      -- decrement a non-zero timer and set the flag
467
      -- to indicate the write operation is still inprogress
468
      wrTimer_x    <= wrTimer_r - 1;
469
      wrInPRogress <= YES;
470
    else
471
      -- on timeout, keep the timer at zero and reset the flag that
472
      -- indicates a write operation is in progress
473
      wrTimer_x    <= wrTimer_r;
474
      wrInPRogress <= NO;
475
    end if;
476
 
477
    -- refresh timer            
478
    if refTimer_r /= 0 then
479
      refTimer_x <= refTimer_r - 1;
480
    else
481
      -- on timeout, reload the timer with the interval between row refreshes
482
      -- and increment the counter for the number of row refreshes that are needed
483
      refTimer_x <= REF_CYCLES;
484
      rfshCntr_x <= rfshCntr_r + 1;
485
    end if;
486
 
487
    -- main timer for sequencing SDRAM operations               
488
    if timer_r /= 0 then
489
      -- decrement the timer and do nothing else since the previous operation has not completed yet.
490
      timer_x <= timer_r - 1;
491
      status  <= "0000";
492
    else
493
      -- the previous operation has completed once the timer hits zero
494
      timer_x <= timer_r;               -- by default, leave the timer at zero
495
 
496
      -----------------------------------------------------------
497
      -- compute the next state and outputs 
498
      -----------------------------------------------------------
499
      case state_r is
500
 
501
        -----------------------------------------------------------
502
        -- let clock stabilize and then wait for the SDRAM to initialize 
503
        -----------------------------------------------------------
504
        when INITWAIT =>
505
          if lock = YES then
506
                                        -- wait for SDRAM power-on initialization once the clock is stable
507
            timer_x <= INIT_CYCLES;     -- set timer for initialization duration
508
            state_x <= INITPCHG;
509
          else
510
                                        -- disable SDRAM clock and return to this state if the clock is not stable
511
                                        -- this insures the clock is stable before enabling the SDRAM
512
                                        -- it also insures a clean startup if the SDRAM is currently in self-refresh mode
513
            cke_x   <= NO;
514
          end if;
515
          status    <= "0001";
516
 
517
          -----------------------------------------------------------
518
          -- precharge all SDRAM banks after power-on initialization 
519
          -----------------------------------------------------------
520
        when INITPCHG =>
521
          cmd_x               <= PCHG_CMD;
522
          sAddr_x(CMDBIT_POS) <= ALL_BANKS;  -- precharge all banks
523
          timer_x             <= RP_CYCLES;  -- set timer for precharge operation duration
524
          rfshCntr_x          <= RFSH_OPS;  -- set counter for refresh ops needed after precharge
525
          state_x             <= INITRFSH;
526
          status              <= "0010";
527
 
528
          -----------------------------------------------------------
529
          -- refresh the SDRAM a number of times after initial precharge 
530
          -----------------------------------------------------------
531
        when INITRFSH =>
532
          cmd_x      <= RFSH_CMD;
533
          timer_x    <= RFC_CYCLES;     -- set timer to refresh operation duration
534
          rfshCntr_x <= rfshCntr_r - 1;  -- decrement refresh operation counter
535
          if rfshCntr_r = 1 then
536
            state_x  <= INITSETMODE;    -- set the SDRAM mode once all refresh ops are done
537
          end if;
538
          status     <= "0011";
539
 
540
          -----------------------------------------------------------
541
          -- set the mode register of the SDRAM 
542
          -----------------------------------------------------------
543
        when INITSETMODE =>
544
          cmd_x   <= MODE_CMD;
545
          sAddr_x <= MODE;              -- output mode register bits on the SDRAM address bits
546
          timer_x <= MODE_CYCLES;       -- set timer for mode setting operation duration
547
          state_x <= RW;
548
          status  <= "0100";
549
 
550
          -----------------------------------------------------------
551
          -- process read/write/refresh operations after initialization is done 
552
          -----------------------------------------------------------
553
        when RW                                      =>
554
          -----------------------------------------------------------
555
          -- highest priority operation: row refresh 
556
          -- do a refresh operation if the refresh counter is non-zero
557
          -----------------------------------------------------------
558
          if rfshCntr_r /= 0 then
559
                                        -- wait for any row activations, writes or reads to finish before doing a precharge
560
            if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
561
              cmd_x                       <= PCHG_CMD;  -- initiate precharge of the SDRAM
562
              sAddr_x(CMDBIT_POS)         <= ALL_BANKS;  -- precharge all banks
563
              timer_x                     <= RP_CYCLES;  -- set timer for this operation
564
              activeFlag_x                <= (others => NO);  -- all rows are inactive after a precharge operation
565
              state_x                     <= REFRESHROW;  -- refresh the SDRAM after the precharge
566
            end if;
567
            status                        <= "0101";
568
            -----------------------------------------------------------
569
            -- do a host-initiated read operation 
570
            -----------------------------------------------------------
571
          elsif rd = YES then
572
                                          -- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
573
            -- This gives extra time for the row activation circuitry.
574
            if (ba_x = ba_r) or (MULTIPLE_ACTIVE_ROWS=false) then
575
                                        -- activate a new row if the current read is outside the active row or bank
576
              if doActivate = YES then
577
                                        -- activate new row only if all previous activations, writes, reads are done
578
                if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
579
                  cmd_x                   <= PCHG_CMD;  -- initiate precharge of the SDRAM
580
                  sAddr_x(CMDBIT_POS)     <= ONE_BANK;  -- precharge this bank
581
                  timer_x                 <= RP_CYCLES;  -- set timer for this operation
582
                  activeFlag_x(bankIndex) <= NO;  -- rows in this bank are inactive after a precharge operation
583
                  state_x                 <= ACTIVATE;  -- activate the new row after the precharge is done
584
                end if;
585
                                        -- read from the currently active row if no previous read operation
586
                                        -- is in progress or if pipeline reads are enabled
587
                                        -- we can always initiate a read even if a write is already in progress
588
              elsif (rdInProgress = NO) or PIPE_EN then
589
                cmd_x                     <= READ_CMD;  -- initiate a read of the SDRAM
590
                                        -- insert a flag into the pipeline shift register that will exit the end
591
                                        -- of the shift register when the data from the SDRAM is available
592
                rdPipeline_x              <= READ & rdPipeline_r(rdPipeline_r'high downto 1);
593
                opBegun_x                 <= YES;  -- tell the host the requested operation has begun
594
              end if;
595
            end if;
596
            status                        <= "0110";
597
            -----------------------------------------------------------
598
            -- do a host-initiated write operation 
599
            -----------------------------------------------------------
600
          elsif wr = YES then
601
                                          -- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
602
            -- This gives extra time for the row activation circuitry.
603
            if (ba_x = ba_r) or (MULTIPLE_ACTIVE_ROWS=false) then
604
                                        -- activate a new row if the current write is outside the active row or bank
605
              if doActivate = YES then
606
                                        -- activate new row only if all previous activations, writes, reads are done
607
                if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
608
                  cmd_x                   <= PCHG_CMD;  -- initiate precharge of the SDRAM
609
                  sAddr_x(CMDBIT_POS)     <= ONE_BANK;  -- precharge this bank
610
                  timer_x                 <= RP_CYCLES;  -- set timer for this operation
611
                  activeFlag_x(bankIndex) <= NO;  -- rows in this bank are inactive after a precharge operation
612
                  state_x                 <= ACTIVATE;  -- activate the new row after the precharge is done
613
                end if;
614
                                        -- write to the currently active row if no previous read operations are in progress
615
              elsif rdInProgress = NO then
616
                cmd_x                     <= WRITE_CMD;  -- initiate the write operation
617
                sDataDir_x                <= OUTPUT;  -- turn on drivers to send data to SDRAM
618
                                        -- set timer so precharge doesn't occur too soon after write operation
619
                wrTimer_x                 <= WR_CYCLES;
620
                                        -- insert a flag into the 1-bit pipeline shift register that will exit on the
621
                                        -- next cycle.  The write into SDRAM is not actually done by that time, but
622
                                        -- this doesn't matter to the host
623
                wrPipeline_x(0)           <= WRITE;
624
                opBegun_x                 <= YES;  -- tell the host the requested operation has begun
625
              end if;
626
            end if;
627
            status                        <= "0111";
628
            -----------------------------------------------------------
629
            -- do a host-initiated self-refresh operation 
630
            -----------------------------------------------------------
631
          elsif doSelfRfsh = YES then
632
                                        -- wait until all previous activations, writes, reads are done
633
            if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
634
              cmd_x                       <= PCHG_CMD;  -- initiate precharge of the SDRAM
635
              sAddr_x(CMDBIT_POS)         <= ALL_BANKS;  -- precharge all banks
636
              timer_x                     <= RP_CYCLES;  -- set timer for this operation
637
              activeFlag_x                <= (others => NO);  -- all rows are inactive after a precharge operation
638
              state_x                     <= SELFREFRESH;  -- self-refresh the SDRAM after the precharge
639
            end if;
640
            status                        <= "1000";
641
            -----------------------------------------------------------
642
            -- no operation
643
            -----------------------------------------------------------
644
          else
645
            state_x                       <= RW;  -- continue to look for SDRAM operations to execute
646
            status                        <= "1001";
647
          end if;
648
 
649
          -----------------------------------------------------------
650
          -- activate a row of the SDRAM 
651
          -----------------------------------------------------------
652
        when ACTIVATE                        =>
653
          cmd_x                   <= ACTIVE_CMD;
654
          sAddr_x                 <= (others => '0');  -- output the address for the row to be activated
655
          sAddr_x(row'range)      <= row;
656
          activeBank_x            <= bank;
657
          activeRow_x(bankIndex)  <= row;  -- store the new active SDRAM row address
658
          activeFlag_x(bankIndex) <= YES;  -- the SDRAM is now active
659
          rasTimer_x              <= RAS_CYCLES;  -- minimum time before another precharge can occur 
660
          timer_x                 <= RCD_CYCLES;  -- minimum time before a read/write operation can occur
661
          state_x                 <= RW;  -- return to do read/write operation that initiated this activation
662
          status                  <= "1010";
663
 
664
          -----------------------------------------------------------
665
          -- refresh a row of the SDRAM         
666
          -----------------------------------------------------------
667
        when REFRESHROW =>
668
          cmd_x      <= RFSH_CMD;
669
          timer_x    <= RFC_CYCLES;     -- refresh operation interval
670
          rfshCntr_x <= rfshCntr_r - 1;  -- decrement the number of needed row refreshes
671
          state_x    <= RW;             -- process more SDRAM operations after refresh is done
672
          status     <= "1011";
673
 
674
          -----------------------------------------------------------
675
          -- place the SDRAM into self-refresh and keep it there until further notice           
676
          -----------------------------------------------------------
677
        when SELFREFRESH            =>
678
          if (doSelfRfsh = YES) or (lock = NO) then
679
                                        -- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock
680
            cmd_x        <= RFSH_CMD;   -- output the refresh command; this is only needed on the first clock cycle
681
            cke_x        <= NO;         -- disable the SDRAM clock
682
          else
683
                                        -- else exit self-refresh mode and start processing read and write operations
684
            cke_x        <= YES;        -- restart the SDRAM clock
685
            rfshCntr_x   <= 0;          -- no refreshes are needed immediately after leaving self-refresh
686
            activeFlag_x <= (others => NO);  -- self-refresh deactivates all rows
687
            timer_x      <= XSR_CYCLES;  -- wait this long until read and write operations can resume
688
            state_x      <= RW;
689
          end if;
690
          status         <= "1100";
691
 
692
          -----------------------------------------------------------
693
          -- unknown state
694
          -----------------------------------------------------------
695
        when others =>
696
          state_x <= INITWAIT;          -- reset state if in erroneous state
697
          status  <= "1101";
698
 
699
      end case;
700
    end if;
701
  end process combinatorial;
702
 
703
 
704
  -----------------------------------------------------------
705
  -- update registers on the appropriate clock edge     
706
  -----------------------------------------------------------
707
 
708
  update : process(rst, clk)
709
  begin
710
 
711
    if rst = YES then
712
      -- asynchronous reset
713
      state_r      <= INITWAIT;
714
      activeFlag_r <= (others => NO);
715
      rfshCntr_r   <= 0;
716
      timer_r      <= 0;
717
      refTimer_r   <= REF_CYCLES;
718
      rasTimer_r   <= 0;
719
      wrTimer_r    <= 0;
720
      nopCntr_r    <= 0;
721
      opBegun_r    <= NO;
722
      rdPipeline_r <= (others => '0');
723
      wrPipeline_r <= (others => '0');
724
      cke_r        <= NO;
725
      cmd_r        <= NOP_CMD;
726
      ba_r         <= (others => '0');
727
      sAddr_r      <= (others => '0');
728
      sData_r      <= (others => '0');
729
      sDataDir_r   <= INPUT;
730
      hDOut_r      <= (others => '0');
731
    elsif rising_edge(clk) then
732
      state_r      <= state_x;
733
      activeBank_r <= activeBank_x;
734
      activeRow_r  <= activeRow_x;
735
      activeFlag_r <= activeFlag_x;
736
      rfshCntr_r   <= rfshCntr_x;
737
      timer_r      <= timer_x;
738
      refTimer_r   <= refTimer_x;
739
      rasTimer_r   <= rasTimer_x;
740
      wrTimer_r    <= wrTimer_x;
741
      nopCntr_r    <= nopCntr_x;
742
      opBegun_r    <= opBegun_x;
743
      rdPipeline_r <= rdPipeline_x;
744
      wrPipeline_r <= wrPipeline_x;
745
      cke_r        <= cke_x;
746
      cmd_r        <= cmd_x;
747
      ba_r         <= ba_x;
748
      sAddr_r      <= sAddr_x;
749
      sData_r      <= sData_x;
750
      sDataDir_r   <= sDataDir_x;
751
      hDOut_r      <= hDOut_x;
752
    end if;
753
 
754
    -- the register that gets data from the SDRAM and holds it for the host
755
    -- is clocked on the opposite edge.  We don't use this register if IN_PHASE=TRUE.
756
    if rst = YES then
757
      hDOutOppPhase_r <= (others => '0');
758
    elsif falling_edge(clk) then
759
      hDOutOppPhase_r <= hDOutOppPhase_x;
760
    end if;
761
 
762
  end process update;
763
 
764
end arch;
765
 
766
 
767
 
768
 
769
--------------------------------------------------------------------
770
-- Company : XESS Corp.
771
-- Engineer : Dave Vanden Bout
772
-- Creation Date : 06/01/2005
773
-- Copyright : 2005, XESS Corp
774
-- Tool Versions : WebPACK 6.3.03i
775
--
776
-- Description:
777
-- Dual-port front-end for SDRAM controller. Supports two
778
-- independent I/O ports to the SDRAM.
779
--
780
-- Revision:
781
-- 1.0.0
782
--
783
-- Additional Comments:
784
--
785
-- License:
786
-- This code can be freely distributed and modified as long as
787
-- this header is not removed.
788
--------------------------------------------------------------------
789
 
790
library IEEE, UNISIM;
791
use IEEE.std_logic_1164.all;
792
use IEEE.std_logic_unsigned.all;
793
use IEEE.numeric_std.all;
794
use WORK.common.all;
795
 
796
entity dualport is
797
  generic(
798
    PIPE_EN         :    boolean                       := false;  -- enable pipelined read operations
799
    PORT_TIME_SLOTS :    std_logic_vector(15 downto 0) := "1111000011110000";
800
    DATA_WIDTH      :    natural                       := 16;  -- host & SDRAM data width
801
    HADDR_WIDTH     :    natural                       := 23  -- host-side address width
802
    );
803
  port(
804
    clk             : in std_logic;     -- master clock
805
 
806
    -- host-side port 0
807
    rst0          : in  std_logic;      -- reset
808
    rd0           : in  std_logic;      -- initiate read operation
809
    wr0           : in  std_logic;      -- initiate write operation
810
    earlyOpBegun0 : out std_logic;      -- read/write op has begun (async)
811
    opBegun0      : out std_logic;      -- read/write op has begun (clocked)
812
    rdPending0    : out std_logic;      -- true if read operation(s) are still in the pipeline
813
    done0         : out std_logic;      -- read or write operation is done
814
    rdDone0       : out std_logic;      -- read operation is done and data is available
815
    hAddr0        : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host to SDRAM
816
    hDIn0         : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host to SDRAM
817
    hDOut0        : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from SDRAM to host
818
    status0       : out std_logic_vector(3 downto 0);  -- diagnostic status of the SDRAM controller FSM         
819
 
820
    -- host-side port 1
821
    rst1          : in  std_logic;
822
    rd1           : in  std_logic;
823
    wr1           : in  std_logic;
824
    earlyOpBegun1 : out std_logic;
825
    opBegun1      : out std_logic;
826
    rdPending1    : out std_logic;
827
    done1         : out std_logic;
828
    rdDone1       : out std_logic;
829
    hAddr1        : in  std_logic_vector(HADDR_WIDTH-1 downto 0);
830
    hDIn1         : in  std_logic_vector(DATA_WIDTH-1 downto 0);
831
    hDOut1        : out std_logic_vector(DATA_WIDTH-1 downto 0);
832
    status1       : out std_logic_vector(3 downto 0);
833
 
834
    -- SDRAM controller port
835
    rst          : out std_logic;
836
    rd           : out std_logic;
837
    wr           : out std_logic;
838
    earlyOpBegun : in  std_logic;
839
    opBegun      : in  std_logic;
840
    rdPending    : in  std_logic;
841
    done         : in  std_logic;
842
    rdDone       : in  std_logic;
843
    hAddr        : out std_logic_vector(HADDR_WIDTH-1 downto 0);
844
    hDIn         : out std_logic_vector(DATA_WIDTH-1 downto 0);
845
    hDOut        : in  std_logic_vector(DATA_WIDTH-1 downto 0);
846
    status       : in  std_logic_vector(3 downto 0)
847
    );
848
end dualport;
849
 
850
 
851
 
852
architecture arch of dualport is
853
  -- The door signal controls whether the read/write signal from the active port
854
  -- is allowed through to the read/write inputs of the SDRAM controller.
855
  type doorState is (OPENED, CLOSED);
856
  signal door_r, door_x : doorState;
857
 
858
  -- The port signal indicates which port is connected to the SDRAM controller.
859
  type portState is (PORT0, PORT1);
860
  signal port_r, port_x : portState;
861
 
862
  signal switch                           : std_logic;  -- indicates that the active port should be switched
863
  signal inProgress                       : std_logic;  -- the active port has a read/write op in-progress
864
  signal rd_i                             : std_logic;  -- read signal to the SDRAM controller (internal copy)
865
  signal wr_i                             : std_logic;  -- write signal to the SDRAM controller (internal copy)
866
  signal earlyOpBegun0_i, earlyOpBegun1_i : std_logic;  -- (internal copies)
867
  signal slot_r, slot_x                   : std_logic_vector(PORT_TIME_SLOTS'range);  -- time-slot allocation shift-register
868
begin
869
 
870
  ----------------------------------------------------------------------------
871
  -- multiplex the SDRAM controller port signals to/from the dual host-side ports  
872
  ----------------------------------------------------------------------------
873
 
874
  -- send the SDRAM controller the address and data from the currently active port
875
  hAddr <= hAddr0 when port_r = PORT0 else hAddr1;
876
  hDIn  <= hDIn0  when port_r = PORT0 else hDIn1;
877
 
878
  -- both ports get the data from the SDRAM but only the active port will use it
879
  hDOut0 <= hDOut;
880
  hDOut1 <= hDOut;
881
 
882
  -- send the SDRAM controller status to the active port and give the inactive port an inactive status code
883
  status0 <= status when port_r = PORT0 else "1111";
884
  status1 <= status when port_r = PORT1 else "1111";
885
 
886
  -- either port can reset the SDRAM controller
887
  rst <= rst0 or rst1;
888
 
889
  -- apply the read signal from the active port to the SDRAM controller only if the door is open.
890
  rd_i <= rd0 when (port_r = PORT0) and (door_r = OPENED) else
891
          rd1 when (port_r = PORT1) and (door_r = OPENED) else
892
          NO;
893
  rd   <= rd_i;
894
 
895
  -- apply the write signal from the active port to the SDRAM controller only if the door is open.
896
  wr_i <= wr0 when (port_r = PORT0) and (door_r = OPENED) else
897
          wr1 when (port_r = PORT1) and (door_r = OPENED) else
898
          NO;
899
  wr   <= wr_i;
900
 
901
  -- send the status signals for various SDRAM controller operations back to the active port
902
  earlyOpBegun0_i <= earlyOpBegun when port_r = PORT0 else NO;
903
  earlyOpBegun0   <= earlyOpBegun0_i;
904
  earlyOpBegun1_i <= earlyOpBegun when port_r = PORT1 else NO;
905
  earlyOpBegun1   <= earlyOpBegun1_i;
906
  rdPending0      <= rdPending    when port_r = PORT0 else NO;
907
  rdPending1      <= rdPending    when port_r = PORT1 else NO;
908
  done0           <= done         when port_r = PORT0 else NO;
909
  done1           <= done         when port_r = PORT1 else NO;
910
  rdDone0         <= rdDone       when port_r = PORT0 else NO;
911
  rdDone1         <= rdDone       when port_r = PORT1 else NO;
912
 
913
  ----------------------------------------------------------------------------
914
  -- Indicate when the active port needs to be switched.  A switch occurs if
915
  -- a read or write operation is requested on the port that is not currently active and:
916
  -- 1) no R/W operation is being performed on the active port or 
917
  -- 2) a R/W operation is in progress on the active port, but the time-slot allocation 
918
  --    register is giving precedence to the inactive port.  (The R/W operation on the
919
  --    active port will be completed before the switch is made.)
920
  -- This rule keeps the active port from hogging all the bandwidth.
921
  ----------------------------------------------------------------------------
922
  switch <= (rd0 or wr0) when (port_r = PORT1) and (((rd1 = NO) and (wr1 = NO)) or (slot_r(0) = '0')) else
923
            (rd1 or wr1) when (port_r = PORT0) and (((rd0 = NO) and (wr0 = NO)) or (slot_r(0) = '1')) else
924
            NO;
925
 
926
  ----------------------------------------------------------------------------
927
  -- Indicate when an operation on the active port is in-progress and
928
  -- can't be interrupted by a switch to the other port.  (Only read operations
929
  -- are looked at since write operations always complete in one cycle once they
930
  -- are initiated.)
931
  ----------------------------------------------------------------------------
932
  inProgress <= rdPending or (rd_i and earlyOpBegun);
933
 
934
  ----------------------------------------------------------------------------
935
  -- Update the time-slot allocation shift-register.  The port with priority is indicated by the
936
  -- least-significant bit of the register.  The register is rotated right if:
937
  -- 1) the current R/W operation has started, and
938
  -- 2) both ports are requesting R/W operations (indicating contention), and
939
  -- 3) the currently active port matches the port that currently has priority.
940
  -- Under these conditions, the current time slot port allocation has been used so
941
  -- the shift register is rotated right to bring the next port time-slot allocation
942
  -- bit into play.
943
  ----------------------------------------------------------------------------
944
  slot_x <= slot_r(0) & slot_r(slot_r'high downto 1) when (earlyOpBegun = YES) and
945
            ( ((rd0 = YES) or (wr0 = YES)) and ((rd1 = YES) or (wr1 = YES)) ) and
946
            ( ((port_r = PORT0) and (slot_r(0) = '0')) or ((port_r = PORT1) and (slot_r(0) = '1')) )
947
            else slot_r;
948
 
949
  ----------------------------------------------------------------------------
950
  -- Determine which port will be active on the next cycle.  The active port is switched if:
951
  -- 1) the currently active port has finished its current R/W operation, and
952
  -- 2) there are no pending operations in progress, and
953
  -- 3) the port switch indicator is active.
954
  ----------------------------------------------------------------------------
955
  port_process : process(port_r, inProgress, switch, done)
956
  begin
957
    port_x       <= port_r;             -- by default, the active port is not changed
958
    case port_r is
959
      when PORT0  =>
960
        if (inProgress = NO) and (switch = YES) and (PIPE_EN or (done = YES)) then
961
          port_x <= PORT1;
962
        end if;
963
      when PORT1  =>
964
        if (inProgress = NO) and (switch = YES) and (PIPE_EN or (done = YES)) then
965
          port_x <= PORT0;
966
        end if;
967
      when others =>
968
        port_x   <= port_r;
969
    end case;
970
  end process port_process;
971
 
972
  -----------------------------------------------------------
973
  -- Determine if the door is open for the active port to initiate new R/W operations to
974
  -- the SDRAM controller.  If the door is open and R/W operations are in progress but
975
  -- a switch to the other port is indicated, then the door is closed to prevent any
976
  -- further R/W operations from the active port.  The door is re-opened once all
977
  -- in-progress operations are completed, at which time the switch to the other port
978
  -- is also completed so it can issue its own R/W commands.
979
  -----------------------------------------------------------
980
  door_process : process(door_r, inProgress, switch)
981
  begin
982
    door_x       <= door_r;             -- by default, the door remains as it is
983
    case door_r is
984
      when OPENED =>
985
        if (inProgress = YES) and (switch = YES) then
986
          door_x <= CLOSED;
987
        end if;
988
      when CLOSED =>
989
        if inProgress = NO then
990
          door_x <= OPENED;
991
        end if;
992
      when others =>
993
        door_x   <= door_r;
994
    end case;
995
  end process door_process;
996
 
997
  -----------------------------------------------------------
998
  -- update registers on the appropriate clock edge     
999
  -----------------------------------------------------------
1000
  update : process(rst0, rst1, clk)
1001
  begin
1002
    if (rst0 = YES) or (rst1 = YES) then
1003
      -- asynchronous reset
1004
      door_r   <= CLOSED;
1005
      port_r   <= PORT0;
1006
      slot_r   <= PORT_TIME_SLOTS;
1007
      opBegun0 <= NO;
1008
      opBegun1 <= NO;
1009
    elsif rising_edge(clk) then
1010
      door_r   <= door_x;
1011
      port_r   <= port_x;
1012
      slot_r   <= slot_x;
1013
      -- opBegun signals are cycle-delayed versions of earlyOpBegun signals.
1014
      -- We can't use the actual opBegun signal from the SDRAM controller
1015
      -- because it would be turned off if the active port was switched on the
1016
      -- cycle immediately after earlyOpBegun went active.
1017
      opBegun0 <= earlyOpBegun0_i;
1018
      opBegun1 <= earlyOpBegun1_i;
1019
    end if;
1020
  end process update;
1021
 
1022
end arch;

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