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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [XuLA_clk.vhd] - Blame information for rev 205

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Line No. Rev Author Line
1 122 dilbert57
--=============================================================================--
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--                                                                             --
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--  System09 - Synthesizable System On a Chip - XuLA System Clock DCM          --
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--                                                                             --
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--=============================================================================--
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--
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--
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-- File name      : XuLA_clk.vhd
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--
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-- Entity name    : XuLA_clk
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--
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-- Purpose        : Clock module to generate 48MHz SDRAM clock
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--                  and 24MHz CPU and VDU pixel clock 
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--                  from the 12MHz PIC FPGA Clock
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--                  ieee.std_logic_arith
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--                  ieee.numeric_std
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--
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-- Uses           : 
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--
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-- Author         : John E. Kent      
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--                  dilbert57@opencores.org      
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--
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--  Copyright (C) 2011 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--
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--                              Revision History:
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--
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--===========================================================================--
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--
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-- Version 0.1 - 30 April 2011 - John Kent
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-- Initial version
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--
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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library unisim;
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   use unisim.vcomponents.all;
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Entity XuLA_clk is
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  generic(
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        FPGA_CLK_FREQ          : integer := 12000000; -- HZ
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             CPU_CLK_FREQ           : integer := 24000000; -- Hz
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             VDU_CLK_FREQ           : integer := 24000000; -- Hz
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                  RAM_CLK_FREQ           : integer := 48000000 -- Hz
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  );
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  port(
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    fpga_clk     : in  std_logic;      -- 12MHz FPGA Clock
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    cpu_clk      : out std_logic;      -- 24MHz CPU clock
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    vdu_clk      : out std_logic;      -- 24MHz VDU clock
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         ram_clk      : out std_logic       -- 48MHz RAM clock
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    );
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end XuLA_clk;
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Architecture RTL of XuLA_clk is
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signal clk12_dcm : std_logic;
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signal clk24_dcm : std_logic;
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signal clk48_dcm : std_logic;
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component BUFG
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  port (
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    I : in  std_logic;
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    O : out std_logic
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  );
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end component;
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begin
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  DCM_XuLA_inst : DCM
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   generic map (
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     DLL_FREQUENCY_MODE    => "LOW", -- "LOW" or "HIGH" 
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     CLKIN_PERIOD          => 83.3,  -- in nsec 
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     CLKFX_DIVIDE          => 1,
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     CLKFX_MULTIPLY        => 4,
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          CLKDV_DIVIDE          => 2,
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     CLKIN_DIVIDE_BY_2     => FALSE,
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     CLKOUT_PHASE_SHIFT    => "NONE",
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     CLK_FEEDBACK          => "1X",
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     DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
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     DFS_FREQUENCY_MODE    => "LOW",
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     DUTY_CYCLE_CORRECTION => TRUE,
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     FACTORY_JF            => X"8080",
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     PHASE_SHIFT           => 0,
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     STARTUP_WAIT          => FALSE)
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   port map (
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     CLKIN      => fpga_clk,     -- input 12MHz
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     CLKFB      => clk12_dcm,    -- feedback input 
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     CLK0       => clk12_dcm,    -- Feedback output (phase, freq = input) 
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     CLK90      => open,         -- Feedback output +  90deg
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     CLK180     => open,         -- Feedback output + 180deg 
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     CLK270     => open,         -- Feedback output + 270deg
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     CLK2X      => clk24_dcm,    -- 2 x input Freq Output 
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     CLK2X180   => open,         -- 2 x input Freq Output + 180 deg
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     CLKDV      => open,         -- Fclkdv = Fclkin/CLKDV_DIVIDE 
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     CLKFX      => clk48_dcm,    -- Fclkfx = Fclkin*CLKFX_MULIPLY/CLKFX_DIVIDE 
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     CLKFX180   => open,         -- CLKFX180 = CLKFX + 180 degrees 
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     LOCKED     => open,         -- DCM in lock 
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     PSDONE     => open,
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     STATUS     => open,
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     PSCLK      => open,         -- Clock input to dynamic phase shifter 
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     PSEN       => open,
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     PSINCDEC   => open,
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     RST        => '0'
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   );
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  bufram : BUFG port map(
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               I => clk48_dcm,
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               O => ram_clk
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              );
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  bufcpu : BUFG port map (
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               I => clk24_dcm,
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               O => cpu_clk
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              );
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  bufvdu : BUFG port map (
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               I => clk24_dcm,
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               O => vdu_clk
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              );
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end RTL;

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