OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [xsasdramcntl.vhd] - Blame information for rev 128

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 122 dilbert57
--------------------------------------------------------------------
2
-- Company       : XESS Corp.
3
-- Engineer      : Dave Vanden Bout
4
-- Creation Date : 05/17/2005
5
-- Copyright     : 2005, XESS Corp
6
-- Tool Versions : WebPACK 6.3.03i
7
--
8
-- Description:
9
--    Customizes the generic SDRAM controller module for the XSA Board.
10
--
11
-- Revision:
12
--    1.2.0
13
--
14
-- Additional Comments:
15
--    1.2.0:
16
--        added upper and lower data strobe signals
17
--        John Kent 2008-03-23
18
--    1.1.0:
19
--        Added CLK_DIV generic parameter to allow stepping-down the clock frequency.
20
--        Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank.
21
--    1.0.0:
22
--        Initial release.
23
--
24
-- License:
25
--    This code can be freely distributed and modified as long as
26
--    this header is not removed.
27
--------------------------------------------------------------------
28
 
29
 
30
 
31
library IEEE, UNISIM;
32
use IEEE.std_logic_1164.all;
33
use IEEE.numeric_std.all;
34
use UNISIM.VComponents.all;
35
use WORK.common.all;
36
use WORK.sdram.all;
37
 
38
 
39
package XSASDRAM is
40
 
41
  component XSASDRAMCntl
42
    generic(
43
      FREQ                 :     natural := 100_000;  -- operating frequency in KHz
44
      CLK_DIV              :     real    := 2.0;  -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
45
      PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
46
      MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
47
      MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
48
      DATA_WIDTH           :     natural := 16;  -- host & SDRAM data width
49
      NROWS                :     natural := 4096;  -- number of rows in SDRAM array
50
      NCOLS                :     natural := 512;  -- number of columns in SDRAM array
51
      HADDR_WIDTH          :     natural := 24;  -- host-side address width
52
      SADDR_WIDTH          :     natural := 12  -- SDRAM-side address width
53
      );
54
    port(
55
      -- host side
56
      clk                  : in  std_logic;  -- master clock
57
      bufclk               : out std_logic;  -- buffered master clock
58
      clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
59
      clk2x                : out std_logic;  -- double-speed host clock
60
      lock                 : out std_logic;  -- true when host clock is locked to master clock
61
      rst                  : in  std_logic;  -- reset
62
      rd                   : in  std_logic;  -- initiate read operation
63
      wr                   : in  std_logic;  -- initiate write operation
64
      earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
65
      opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
66
      rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
67
      done                 : out std_logic;  -- read or write operation is done
68
      rdDone               : out std_logic;  -- read done and data is available
69
      hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
70
      hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
71
      hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
72
      status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
73
 
74
      -- SDRAM side
75
      sclkfb : in    std_logic;         -- clock from SDRAM after PCB delays
76
      sclk   : out   std_logic;         -- SDRAM clock sync'ed to master clock
77
      cke    : out   std_logic;         -- clock-enable to SDRAM
78
      cs_n   : out   std_logic;         -- chip-select to SDRAM
79
      ras_n  : out   std_logic;         -- SDRAM row address strobe
80
      cas_n  : out   std_logic;         -- SDRAM column address strobe
81
      we_n   : out   std_logic;         -- SDRAM write enable
82
      ba     : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
83
      sAddr  : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
84
      sData  : inout std_logic_vector(DATA_WIDTH-1 downto 0)  -- SDRAM in/out databus
85
      );
86
  end component;
87
 
88
end package XSASDRAM;
89
 
90
 
91
 
92
library IEEE, UNISIM;
93
use IEEE.std_logic_1164.all;
94
use IEEE.numeric_std.all;
95
use UNISIM.VComponents.all;
96
use WORK.common.all;
97
use WORK.sdram.all;
98
 
99
entity XSASDRAMCntl is
100
  generic(
101
    FREQ                 :     natural := 100_000; -- operating frequency in KHz
102
    CLK_DIV              :     real    := 2.0;     -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
103
    PIPE_EN              :     boolean := false;   -- if true, enable pipelined read operations
104
    MAX_NOP              :     natural := 10000;   -- number of NOPs before entering self-refresh
105
    MULTIPLE_ACTIVE_ROWS :     boolean := false;   -- if true, allow an active row in each bank
106
    DATA_WIDTH           :     natural := 16;      -- host & SDRAM data width
107
    NROWS                :     natural := 8192;    -- number of rows in SDRAM array
108
    NCOLS                :     natural := 512;     -- number of columns in SDRAM array
109
    HADDR_WIDTH          :     natural := 24;      -- host-side address width
110
    SADDR_WIDTH          :     natural := 13       -- SDRAM-side address width
111
    );
112
  port(
113
    -- host side
114
    clk                  : in  std_logic;  -- master clock
115
    bufclk               : out std_logic;  -- buffered master clock
116
    clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
117
    clk2x                : out std_logic;  -- double-speed host clock
118
    lock                 : out std_logic;  -- true when host clock is locked to master clock
119
    rst                  : in  std_logic;  -- reset
120
    rd                   : in  std_logic;  -- initiate read operation
121
    wr                   : in  std_logic;  -- initiate write operation
122
    earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
123
    opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
124
    rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
125
    done                 : out std_logic;  -- read or write operation is done
126
    rdDone               : out std_logic;  -- read done and data is available
127
    hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
128
    hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
129
    hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
130
    status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
131
 
132
    -- SDRAM side
133
    sclkfb : in    std_logic;           -- clock from SDRAM after PCB delays
134
    sclk   : out   std_logic;           -- SDRAM clock sync'ed to master clock
135
    cke    : out   std_logic;           -- clock-enable to SDRAM
136
    cs_n   : out   std_logic;           -- chip-select to SDRAM
137
    ras_n  : out   std_logic;           -- SDRAM row address strobe
138
    cas_n  : out   std_logic;           -- SDRAM column address strobe
139
    we_n   : out   std_logic;           -- SDRAM write enable
140
    ba     : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
141
    sAddr  : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
142
    sData  : inout std_logic_vector(DATA_WIDTH-1 downto 0)  -- SDRAM in/out databus
143
    );
144
end XSASDRAMCntl;
145
 
146
 
147
 
148
architecture arch of XSASDRAMCntl is
149
 
150
  -- The SDRAM controller and external SDRAM chip will clock on the same edge
151
  -- if the frequency and divided frequency are both greater than the minimum DLL lock frequency.
152
  -- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
153
  -- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
154
  constant MIN_LOCK_FREQ : real    := 25_000.0;
155
  constant IN_PHASE      : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ;
156
  -- Calculate the frequency of the clock for the SDRAM.
157
--  constant SDRAM_FREQ    : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ);
158
  constant SDRAM_FREQ    : natural := int_select(IN_PHASE, FREQ/integer(CLK_DIV), FREQ);
159
  -- Compute the CLKDV_DIVIDE generic paramter for the DLL modules.  It defaults to 2 when CLK_DIV=1
160
  -- because the DLL does not support a divisor of 1 on the CLKDV output.  We use the CLK0 output
161
  -- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL.
162
  constant CLKDV_DIVIDE  : real    := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV);
163
 
164
  signal int_clkin,                     -- signals for internal logic clock DLL
165
    int_clk1x, int_clk1x_b,
166
    int_clk2x, int_clk2x_b,
167
    int_clkdv, int_clkdv_b              : std_logic;
168
  signal ext_clkin, sclkfb_b, ext_clk1x : std_logic;  -- signals for external logic clock DLL
169
  signal dllext_rst, dllext_rst_n       : std_logic;  -- external DLL reset signal
170
  signal clk_i                          : std_logic;  -- clock for SDRAM controller logic
171
  signal int_lock, ext_lock, lock_i     : std_logic;  -- DLL lock signals
172
 
173
  -- bus for holding output data from SDRAM
174
  signal sDOut   : std_logic_vector(sData'range);
175
  signal sDOutEn : std_logic;
176
 
177
begin
178
 
179
  -----------------------------------------------------------
180
  -- setup the DLLs for clock generation 
181
  -----------------------------------------------------------
182
 
183
  -- master clock must come from a dedicated clock pin
184
  clkin_buf : BUFG port map (I => clk, O => int_clkin);
185
 
186
  -- The external DLL is driven from the same source as the internal DLL
187
  -- if the clock divisor is 1.  If CLK_DIV is greater than 1, then the external DLL 
188
  -- is driven by the divided clock from the internal DLL.  Otherwise, the SDRAM will be
189
  -- clocked on the opposite edge if the internal and external logic are not in-phase.
190
  ext_clkin <= int_clkin    when (IN_PHASE and (CLK_DIV = 1.0)) else
191
                int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0))  else
192
                not int_clkin;
193
 
194
  -- Generate the DLLs for sync'ing the clocks as long as the clocks
195
  -- have a frequency high enough for the DLLs to lock
196
  gen_dlls : if IN_PHASE generate
197
 
198
    -- generate an internal clock sync'ed to the master clock
199
    dllint : CLKDLL
200
      generic map(
201
        CLKDV_DIVIDE => CLKDV_DIVIDE
202
        )
203
      port map(
204
        CLKIN        => int_clkin,
205
        CLKFB        => int_clk1x_b,
206
        CLK0         => int_clk1x,
207
        RST          => ZERO,
208
        CLK90        => open,
209
        CLK180       => open,
210
        CLK270       => open,
211
        CLK2X        => int_clk2x,
212
        CLKDV        => int_clkdv,
213
        LOCKED       => int_lock
214
        );
215
 
216
    -- sync'ed single, doubled and divided clocks for use by internal logic
217
    int_clk1x_buf : BUFG port map(I => int_clk1x, O => int_clk1x_b);
218
    int_clk2x_buf : BUFG port map(I => int_clk2x, O => int_clk2x_b);
219
    int_clkdv_buf : BUFG port map(I => int_clkdv, O => int_clkdv_b);
220
 
221
    -- The external DLL is held in a reset state until the internal DLL locks.
222
    -- Then the external DLL reset is released after a delay set by this shift register.
223
    -- This keeps the external DLL from locking onto the internal DLL clock signal
224
    -- until it is stable.
225
    SRL16_inst : SRL16
226
      generic map (
227
        INIT => X"0000"
228
        )
229
      port map (
230
        CLK  => clk_i,
231
        A0   => '1',
232
        A1   => '1',
233
        A2   => '1',
234
        A3   => '1',
235
        D    => int_lock,
236
        Q    => dllext_rst_n
237
        );
238
--    Error ???
239
--    dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO;
240
    dllext_rst <= not dllext_rst_n when CLK_DIV/=1.0 else ZERO;
241
 
242
    -- generate an external SDRAM clock sync'ed to the master clock
243
    sclkfb_buf : IBUF port map(I => sclkfb, O => sclkfb_b);  -- SDRAM clock with PCB delays
244
 
245
    dllext     : CLKDLL port map(
246
      CLKIN                       => ext_clkin,  -- this is either the master clock or the divided clock from the internal DLL
247
      CLKFB                       => sclkfb_b,
248
      CLK0                        => ext_clk1x,
249
      RST                         => dllext_rst,
250
      CLK90                       => open,
251
      CLK180                      => open,
252
      CLK270                      => open,
253
      CLK2X                       => open,
254
      CLKDV                       => open,
255
      LOCKED                      => ext_lock
256
      );
257
 
258
  end generate;
259
 
260
  -- The buffered clock is just a buffered version of the master clock.
261
  bufclk_bufg : BUFG port map (I => int_clkin, O => bufclk);
262
  -- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1.
263
  -- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1.
264
  -- Otherwise it is just a copy of the master clock if the DLLs aren't being used.
265
  clk_i  <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else
266
            int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0))  else
267
            int_clkin;
268
  clk1x  <= clk_i;                      -- This is the output of the host-side clock
269
  clk2x  <= int_clk2x_b when IN_PHASE                       else int_clkin;  -- this is the doubled master clock
270
  sclk   <= ext_clk1x   when IN_PHASE                       else ext_clkin;  -- this is the clock for the external SDRAM
271
 
272
  -- indicate the lock status of the internal and external DLL
273
  lock_i <= int_lock and ext_lock when IN_PHASE else YES;
274
  lock   <= lock_i;                     -- lock signal for the host logic
275
 
276
  -- SDRAM memory controller module
277
  u1 : sdramCntl
278
    generic map(
279
      FREQ                 => SDRAM_FREQ,
280
      IN_PHASE             => IN_PHASE,
281
      PIPE_EN              => PIPE_EN,
282
      MAX_NOP              => MAX_NOP,
283
      MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
284
      DATA_WIDTH           => DATA_WIDTH,
285
      NROWS                => NROWS,
286
      NCOLS                => NCOLS,
287
      HADDR_WIDTH          => HADDR_WIDTH,
288
      SADDR_WIDTH          => SADDR_WIDTH
289
      )
290
    port map(
291
      clk                  => clk_i,    -- master clock from external clock source (unbuffered)
292
      lock                 => lock_i,   -- valid synchronized clocks indicator
293
      rst                  => rst,      -- reset
294
      rd                   => rd,       -- host-side SDRAM read control from memory tester
295
      wr                   => wr,       -- host-side SDRAM write control from memory tester
296
      rdPending            => rdPending,
297
      opBegun              => opBegun,  -- SDRAM memory read/write done indicator
298
      earlyOpBegun         => earlyOpBegun,  -- SDRAM memory read/write done indicator
299
      rdDone               => rdDone,   -- SDRAM memory read/write done indicator
300
      done                 => done,
301
      hAddr                => hAddr,    -- host-side address from memory tester
302
      hDIn                 => hDIn,     -- test data pattern from memory tester
303
      hDOut                => hDOut,    -- SDRAM data output to memory tester
304
      status               => status,   -- SDRAM controller state (for diagnostics)
305
      cke                  => cke,      -- SDRAM clock enable
306
      ce_n                 => cs_n,     -- SDRAM chip-select
307
      ras_n                => ras_n,    -- SDRAM RAS
308
      cas_n                => cas_n,    -- SDRAM CAS
309
      we_n                 => we_n,     -- SDRAM write-enable
310
      ba                   => ba,       -- SDRAM bank address
311
      sAddr                => sAddr,    -- SDRAM address
312
      sDIn                 => sData,    -- input data from SDRAM
313
      sDOut                => sDOut,    -- output data to SDRAM
314
      sDOutEn              => sDOutEn  -- enable drivers to send data to SDRAM
315
      );
316
 
317
  sData <= sDOut when sDOutEn = YES else (others => 'Z');
318
 
319
end arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.