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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [xula_iobus.vhd] - Blame information for rev 210

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1 122 dilbert57
--===========================================================================--
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--                                                                           --
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--  xula_iobus.vhd - Synthesizable Dual Bidirectionsal I/O Port             --
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--                                                                           --
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--===========================================================================--
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--
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--  File name      : xula_iobusi.vhd
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--
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--  Purpose        : Implements a dual 8 bit bidirectional I/O bus
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--                   for the XuLA implementation of System09
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--                   Allows the XuLA System09 port to talk to
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-- 
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--  Dependencies   : ieee.std_logic_1164
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--                   ieee.std_logic_unsigned
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--                   unisim.vcomponents
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--
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--  Author         : John E. Kent
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--
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--  Email          : dilbert57@opencores.org      
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--
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--  Web            : http://opencores.org/project,system09
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--
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-- Description
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--
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--  system09 clk  /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\
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--
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--  system09 cs   ---\_______________________________/--------------------
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--
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--  bus release   ______________________________/-------------------------
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--
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--  system09 hold ____/---------------------------\_______________________
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--
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--  bus cs_n      ----\______________________________/--------------------
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--
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--  bus rd_n      ---------------------\_____________/--------------------
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--
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--  bus ds        _____________________/-------------\____________________
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--
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--
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--  Copyright (C) 2002 - 2011 John Kent
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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--                                                                           --
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--                              Revision  History                            --
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--                                                                           --
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--===========================================================================--
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--
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-- Version  Author        Date               Description
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-- 0.1      John E. Kent  1 May 2011         Initial version 
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--===========================================================================
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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--library unisim;
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--  use unisim.vcomponents.all;
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entity xula_iobus is
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  port (
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    clk        : in    std_logic;
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    rst        : in    std_logic;
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    cs         : in    std_logic;
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    rw         : in    std_logic;
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    addr       : in    std_logic_vector(4 downto 0);
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    data_in    : in    std_logic_vector(7 downto 0);
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    data_out   : out   std_logic_vector(7 downto 0);
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         hold       : out   std_logic;
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    irq        : out   std_logic;
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         bus_cs     : out   std_logic;
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    bus_ds_rdn : out   std_logic;
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    bus_rw_wrn : out   std_logic;
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    bus_addr   : out   std_logic_vector(3 downto 0);
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    bus_data   : inout std_logic_vector(7 downto 0);
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         bus_irq    : in    std_logic;
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  );
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end;
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architecture rtl of xula_iobus is
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begin
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--------------------------------
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--
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-- read I/O bus control registers
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--
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--------------------------------
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iobus_read : process( addr, bus_data, bus_reg )
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begin
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  if addr(4) = '0' then
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    data_out <= bus_data;
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  else
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    data_out <= bus_reg;
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  end if;
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end process;
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---------------------------------
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--
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-- Write bus data / register
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--
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---------------------------------
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iobus_write : process( clk, rst, addr, cs, rw, data_in )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      bus_data <= (others=>'Z');
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      bus_reg <= (others=>'0');
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    else
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      if cs = '1' then
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                  if addr(4) = '0' then
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                    if bus_release = '0' and bus_hold = '0' then
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                           bus_hold <= '1';
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            if rw = '0' then
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              bus_data <= data_in;
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            else
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              bus_data <= (other=>'Z');
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            end if;
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          else
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                           if bus_release = '1' and bus_hold = '1' then
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                                  bus_hold <= '0';
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                                end if;
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                         end if;
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        else
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                    if rw = '0' then
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             bus_reg <= data_in;
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          end if;
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        end if;
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      end if;
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    end if;
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  end if;
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end process;
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---------------------------------
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--
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-- Write bus register
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--
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---------------------------------
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iobus_reg_write : process( clk, rst, addr, cs, rw, data_in )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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    else
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      if cs = '1' and addr(4) = '1' then
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                  if rw = '0' then
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           bus_reg <= data_in;
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        else
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           bus_data <= (other=>'Z');
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        end if;
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      end if;
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    end if;
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  end if;
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end process;
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---------------------------------
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--
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-- direction control port a
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--
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---------------------------------
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iobus_ctrl : process ( clk, rst,  )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      bus_data <= (others=>'0');
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      bus_reg  <= (others=>'0');
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    else
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end process;
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---------------------------------
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--
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-- hold CPU for one external bus cycle
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--
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---------------------------------
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iobus_hold : process ( portb_data, portb_ddr, portb_io )
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begin
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end process;
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---------------------------------
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----------------------------------------------------------
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--
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-- Generate a bus clock with half cycle period
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-- equal to the cpu clock cycle count
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-- in the bus register bits 6 downto 0.
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--
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-- Generate a time out signal for one cpu clock cycle
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-- when the bus timer reaches zero
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--
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----------------------------------------------------------
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iobus_clk : process ( clk, rst )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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           bus_timer <= (others=>'0');
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                bus_clk   <= '0';
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                bus_to    <= '0';
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    else
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           if bus_timer = "0000000" then
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                  bus_timer <= bus_reg(6 downto 0);
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                  bus_clk   <= not bus_clk;
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                  bus_to    <= '1';
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                else
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                  bus_timer <= bus_timer - "0000001";
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                  bus_to    <= '0';
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                end if;
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         end if;
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  end if;
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end process;
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----------------------------------------------------------
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--
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--  Bus Request
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--
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--  Synchronize I/O bus cycle request to the start of the bus clock
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--
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--  The start of the io bus cycle is defined as there being
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--  a bus timer timeout and the bus clock is low.
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--
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--  If there is a bus request wait for the start of the
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--  io bus cycle before acknowledging
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--
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--  If the bus request is removed, wait for the start of the
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--  io bus cycle before removing the acknowledge.
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--
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----------------------------------------------------------
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iobus_req : process ( clk, rst, bus_req, bus_ack, bus_clk, bus_to )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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           bus_ack <= '0';
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    else
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           if bus_req = '1' and bus_ack = '0' then
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                  if bus_clk = '0' and bus_to = '1' then
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                    bus_ack <= '1';
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                  end if;
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      elsif bus_req = '0' and bus_ack = '1' then
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                  if bus_clk = '0' and bus_to = '1' then
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                    bus_ack <= '0';
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                  end if;
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                end if;
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         end if;
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  end if;
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end process;
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end rtl;
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