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[/] [System09/] [trunk/] [rtl/] [System09_Xilinx_ML506/] [System09_Xilinx_ML506.vhd] - Blame information for rev 171

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1 121 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xilinx_ML506.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx Virtex-5.
12
--                  Implemented With Xilinx ML506 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  This configuration also lacks a DAT so cannot use
17
--                  the RAM Disk features of SYS09BUG.
18
--
19
-- Dependencies   : ieee.Std_Logic_1164
20
--                  ieee.std_logic_unsigned
21
--                  ieee.std_logic_arith
22
--                  ieee.numeric_std
23
--                  unisim.vcomponents
24
--
25
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
26
--                  cpu09      (cpu09.vhd)          CPU core
27
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
28
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
29
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
30
--                             (ps2_keyboard.vhd)
31
--                             (keymap_rom_slice.vhd) Key map table 
32
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
33
--                             (char_rom2k_b16.vhd)
34
--                             (ram2k_b16.vhd)
35
--                  timer      (timer.vhd)            Interrupt timer
36
--                  trap       (trap.vhd)             Bus condition trap logic
37
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
38
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
39
--                  
40
-- 
41
-- Author         : John E. Kent      
42
--                  dilbert57@opencores.org      
43
--
44
-- Memory Map     :
45
--
46
-- $0000 - User program RAM (32K Bytes)
47
-- $C000 - Flex Operating System memory (8K Bytes)
48
-- $E000 - ACIA (SWTPc)
49
-- $E010 - Reserved for FD1771 FDC (SWTPc)
50
-- $E020 - Keyboard
51
-- $E030 - VDU
52
-- $E040 - IDE / Compact Flash interface
53
-- $E050 - Timer
54
-- $E060 - Bus trap
55
-- $E070 - Reserced for Parallel I/O (B5-X300)
56
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
57
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
58
-- $F000 - Sys09Bug monitor Program (4K Bytes)
59
--
60
--===========================================================================----
61
--
62
-- Revision History:
63
--===========================================================================--
64
-- Version 0.1 - 20 March 2003
65
-- Version 0.2 - 30 March 2003
66
-- Version 0.3 - 29 April 2003
67
-- Version 0.4 - 29 June 2003
68
--
69
-- Version 0.5 - 19 July 2003
70
-- prints out "Hello World"
71
--
72
-- Version 0.6 - 5 September 2003
73
-- Runs SBUG
74
--
75
-- Version 1.0- 6 Sep 2003 - John Kent
76
-- Inverted SysClk
77
-- Initial release to Open Cores
78
--
79
-- Version 1.1 - 17 Jan 2004 - John Kent
80
-- Updated miniUart.
81
--
82
-- Version 1.2 - 25 Jan 2004 - John Kent
83
-- removed signals "test_alu" and "test_cc" 
84
-- Trap hardware re-instated.
85
--
86
-- Version 1.3 - 11 Feb 2004 - John Kent
87
-- Designed forked off to produce System09_VDU
88
-- Added VDU component
89
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
90
-- UART Runs at 57.6 Kbps
91
--
92
-- Version 2.0 - 2 September 2004 - John Kent
93
-- ported to Digilent Xilinx Spartan3 starter board
94
--      removed Compact Flash and Trap Logic.
95
-- Replaced SBUG with KBug9s
96
--
97
-- Version 3.0 - 29th August 2006 - John Kent
98
-- Adapted to XSA-3S1000 board.
99
-- Removed DAT and miniUART.
100
-- Used 32KBytes of Block RAM.
101
--
102
-- Version 3.1 - 15th January 2007 - John Kent
103
-- Modified vdu8 interface
104
-- Added a clock divider
105
--
106
-- Version 3.2 - 25th February 2007 - John Kent
107
-- reinstated ACIA_6850 and ACIA_Clock
108
-- Updated VDU8 & Keyboard with generic parameters
109
-- Defined Constants for clock speed calculations
110
--
111
-- Version 3.3 - 1st July 2007 - John Kent
112
-- Made VDU mono to save on one RAMB16
113
-- Used distributed memory for Key Map ROM to save one RAMB16
114
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
115
-- Added timer and trap logic
116
-- Added IDE Interface for Compact Flash
117
-- Replaced KBug9s and stack with Sys09Bug.
118
--
119
-- Version 4.0 - 1st February 2008 - John kent
120
-- Replaced Block RAM with SDRAM Interface
121
-- Modified Hold timing for SDRAM
122
-- Added CF and Ethernet interface 
123
-- via the 16 bit peripheral bus at $E100
124
--
125
--===========================================================================--
126
library ieee;
127
   use ieee.std_logic_1164.all;
128
   use IEEE.STD_LOGIC_ARITH.ALL;
129
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
130
   use ieee.numeric_std.all;
131
library unisim;
132
   use unisim.vcomponents.all;
133
 
134
entity system09 is
135
  port(
136
    clk_i         : in  Std_Logic;  -- 100MHz Clock input
137
--    CLKB         : in  Std_Logic;  -- 50MHz Clock input
138
         SW2_N        : in  Std_logic;  -- Master Reset input (active low)
139
         SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
140
 
141
         -- PS/2 Keyboard
142
--       ps2_clk      : inout Std_logic;
143
--       ps2_dat      : inout Std_Logic;
144
 
145
         -- CRTC output signals
146
--       vga_vsync_n  : out Std_Logic;
147
--    vga_hsync_n  : out Std_Logic;
148
--    vga_blue     : out std_logic_vector(2 downto 0);
149
--    vga_green    : out std_logic_vector(2 downto 0);
150
--    vga_red      : out std_logic_vector(2 downto 0);
151
 
152
    -- RS232 Port
153
         RS232_RXD    : in  Std_Logic;
154
         RS232_TXD    : out Std_Logic;
155
--    RS232_CTS    : in  Std_Logic;
156
--    RS232_RTS    : out Std_Logic;
157
 
158
 
159
 
160
    -- SDRAM side
161
--    SDRAM_clkfb  : in  std_logic;            -- feedback SDRAM clock after PCB delays
162
--    SDRAM_clkout : out std_logic;            -- clock to SDRAM
163
--    SDRAM_CKE    : out std_logic;            -- clock-enable to SDRAM
164
--    SDRAM_CS_N   : out std_logic;            -- chip-select to SDRAM
165
--    SDRAM_RAS_N  : out std_logic;            -- SDRAM row address strobe
166
--    SDRAM_CAS_N  : out std_logic;            -- SDRAM column address strobe
167
--    SDRAM_WE_N   : out std_logic;            -- SDRAM write enable
168
--    SDRAM_BA     : out std_logic_vector(1 downto 0);  -- SDRAM bank address
169
--    SDRAM_A      : out std_logic_vector(12 downto 0);  -- SDRAM row/column address
170
--    SDRAM_D      : inout  std_logic_vector(15 downto 0);  -- data from SDRAM
171
--    SDRAM_DQMH   : out std_logic;            -- enable upper-byte of SDRAM databus if true
172
--    SDRAM_DQML   : out std_logic;            -- enable lower-byte of SDRAM databus if true
173
 
174
         -- Peripheral I/O bus $E100 - $E1FF
175
--    PB_RD_N      : out std_logic;
176
--    PB_WR_N      : out std_logic;
177
--    PB_A         : out std_logic_vector(4 downto 0);
178
--    PB_D         : inout std_logic_vector(15 downto 0);
179
 
180
    -- IDE Compact Flash $E100 - $E13F
181
--    ide_dmack_n  : out std_logic;
182
--       ide_cs0_n    : out std_logic;
183
--       ide_cs1_n    : out std_logic;
184
 
185
    -- Ethernet $E140 - $E17F
186
--    ether_cs_n   : out std_logic;
187
--    ether_aen    : out std_logic; -- Ethernet address enable not 
188
--    ether_bhe_n  : out std_logic; -- Ethernet bus high enable 
189
--    ether_clk    : in  std_logic; -- Ethernet clock 
190
--    ether_rdy    : in  std_logic; -- Ethernet ready
191
--    ether_irq    : in  std_logic; -- Ethernet irq - Shared with BAR6
192
 
193
    -- Slot 1 $E180 - $E1BF
194
--       slot1_cs_n   : out std_logic;
195
--       slot1_irq    : in  std_logic;
196
 
197
    -- Slot 2 $E1C0 - $E1FF
198
--       slot2_cs_n   : out std_logic;
199
--       slot2_irq    : in  std_logic;
200
 
201
-- CPU Debug Interface signals
202
--    cpu_reset_o     : out Std_Logic;
203
--    cpu_clk_o       : out Std_Logic;
204
--    cpu_rw_o        : out std_logic;
205
--    cpu_vma_o       : out std_logic;
206
--    cpu_halt_o      : out std_logic;
207
--    cpu_hold_o      : out std_logic;
208
--    cpu_firq_o      : out std_logic;
209
--    cpu_irq_o       : out std_logic;
210
--    cpu_nmi_o       : out std_logic;
211
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
212
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
213
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
214
 
215
         -- Disable Flash
216
--       FLASH_CE_N   : out std_logic
217
         -- Status 7 segment LED
218
         S            : out std_logic_vector(7 downto 0)
219
         );
220
end system09;
221
 
222
-------------------------------------------------------------------------------
223
-- Architecture for System09
224
-------------------------------------------------------------------------------
225
architecture rtl of system09 is
226
 
227
  -----------------------------------------------------------------------------
228
  -- constants
229
  -----------------------------------------------------------------------------
230
 
231
  -- SDRAM
232
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
233
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
234
  constant PIPE_EN              : boolean := false;  -- if true, enable pipelined read operations
235
  constant MAX_NOP              : natural := 10000;  -- number of NOPs before entering self-refresh
236
  constant MULTIPLE_ACTIVE_ROWS : boolean := false;  -- if true, allow an active row in each bank
237
  constant DATA_WIDTH           : natural := 16;     -- host & SDRAM data width
238
  constant NROWS                : natural := 8192;   -- number of rows in SDRAM array
239
  constant NCOLS                : natural := 512;    -- number of columns in SDRAM array
240
  constant HADDR_WIDTH          : natural := 24;     -- host-side address width
241
  constant SADDR_WIDTH          : natural := 13;     -- SDRAM-side address width
242
 
243
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock
244
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
245
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
246
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
247
  constant VGA_CLK_DIV          : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
248
  constant BAUD_RATE            : integer := 57600;       -- Baud Rate
249
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
250
 
251
  constant TRESET               : natural := 300;      -- min initialization interval (us)
252
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
253
 
254
  type hold_state_type is ( hold_release_state, hold_request_state );
255
 
256
 
257
-- Dummy signals to replace unused ports
258
signal   FLASH_CE_N   : std_logic;
259
signal ps2_clk, ps2_dat : std_logic;
260
signal ether_cs_n, ether_aen, ether_bhe_n, ether_clk, ether_rdy, ether_irq : std_logic;
261
signal slot1_cs_n, slot1_irq, slot2_cs_n, slot2_irq : std_logic;
262
signal SDRAM_clkfb, SDRAM_clkout, SDRAM_CKE, SDRAM_CS_N, SDRAM_RAS_N, SDRAM_WE_N, SDRAM_DQMH, SDRAM_DQML : std_logic;
263
signal SDRAM_BA : std_logic_vector(1 downto 0);
264
signal SDRAM_A : std_logic_vector(12 downto 0);
265
signal SDRAM_D : std_logic_vector(15 downto 0);
266
signal PB_RD_N, PB_WR_N : std_logic;
267
signal PB_A : std_logic_vector(4 downto 0);
268
signal PB_D : std_logic_vector(15 downto 0);
269
signal ide_dmack_n, ide_cs0_n, ide_cs1_n: std_logic;
270
signal vga_vsync_n, vga_hsync_n : std_logic;
271
signal vga_blue, vga_green, vga_red : std_logic_vector(2 downto 0);
272
signal RS232_CTS, RS232_RTS : std_logic;
273
 
274
  -----------------------------------------------------------------------------
275
  -- Signals
276
  -----------------------------------------------------------------------------
277
  -- BOOT ROM
278
  signal rom_cs         : Std_logic;
279
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
280
 
281
  -- Flex Memory & Monitor Stack
282
  signal flex_cs        : Std_logic;
283
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
284
 
285
  -- ACIA/UART Interface signals
286
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
287
  signal acia_cs        : Std_Logic;
288
  signal acia_irq       : Std_Logic;
289
  signal acia_clk       : Std_Logic;
290
  signal rxd            : Std_Logic;
291
  signal txd            : Std_Logic;
292
  signal DCD_n          : Std_Logic;
293
  signal RTS_n          : Std_Logic;
294
  signal CTS_n          : Std_Logic;
295
 
296
  -- keyboard port
297
  signal keyboard_data_out : std_logic_vector(7 downto 0);
298
  signal keyboard_cs       : std_logic;
299
  signal keyboard_irq      : std_logic;
300
 
301
  -- RAM
302
  signal ram_cs         : std_logic; -- memory chip select
303
  signal ram_data_out   : std_logic_vector(7 downto 0);
304
  signal ram_rd_req     : std_logic; -- ram read request        (asynch set on ram read, cleared falling CPU clock edge)
305
  signal ram_wr_req     : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge) 
306
  signal ram_hold       : std_logic; -- hold off slow accesses
307
  signal ram_release    : std_logic; -- Release ram hold
308
 
309
  -- CPU Interface signals
310
  signal cpu_reset      : Std_Logic;
311
  signal cpu_clk        : Std_Logic;
312
  signal cpu_rw         : std_logic;
313
  signal cpu_vma        : std_logic;
314
  signal cpu_halt       : std_logic;
315
  signal cpu_hold       : std_logic;
316
  signal cpu_firq       : std_logic;
317
  signal cpu_irq        : std_logic;
318
  signal cpu_nmi        : std_logic;
319
  signal cpu_addr       : std_logic_vector(15 downto 0);
320
  signal cpu_data_in    : std_logic_vector(7 downto 0);
321
  signal cpu_data_out   : std_logic_vector(7 downto 0);
322
 
323
  -- Dynamic Address Translation
324
  signal dat_cs       : std_logic;
325
  signal dat_addr     : std_logic_vector(7 downto 0);
326
 
327
  -- Video Display Unit
328
  signal vdu_cs         : std_logic;
329
  signal vdu_data_out   : std_logic_vector(7 downto 0);
330
  signal vga_red_o      : std_logic;
331
  signal vga_green_o    : std_logic;
332
  signal vga_blue_o     : std_logic;
333
 
334
  -- timer
335
  signal timer_data_out : std_logic_vector(7 downto 0);
336
  signal timer_cs       : std_logic;
337
  signal timer_irq      : std_logic;
338
 
339
  -- trap
340
  signal trap_cs        : std_logic;
341
  signal trap_data_out  : std_logic_vector(7 downto 0);
342
  signal trap_irq       : std_logic;
343
 
344
  -- Peripheral Bus port
345
  signal pb_data_out   : std_logic_vector(7 downto 0);
346
  signal pb_cs         : std_logic;       -- peripheral bus chip select
347
  signal pb_wru        : std_logic;       -- upper byte write strobe
348
  signal pb_wrl        : std_logic;       -- lower byte write strobe
349
  signal pb_rdu        : std_logic;       -- upper byte read strobe
350
  signal pb_rdl        : std_logic;       -- lower byte read strobe
351
  signal pb_hold       : std_logic;       -- hold peripheral bus access
352
  signal pb_release    : std_logic;       -- release hold of peripheral bus
353
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
354
  signal pb_hold_state : hold_state_type;
355
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
356
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
357
 
358
  -- Peripheral chip selects on Peripheral Bus
359
  signal ide_cs        : std_logic; -- IDE CF interface
360
  signal ether_cs      : std_logic;     -- Ethernet interface
361
  signal slot1_cs      : std_logic;     -- Expansion slot 1
362
  signal slot2_cs      : std_logic;     -- Expansion slot 2
363
 
364
  signal rst_i         : std_logic;     -- internal reset signal
365
--  signal clk_i         : std_logic;     -- internal master clock signal
366
  signal lock          : std_logic;     -- SDRAM clock DLL lock indicator
367
 
368
  -- signals that go through the SDRAM host-side interface
369
  signal opBegun       : std_logic;        -- SDRAM operation started indicator
370
  signal earlyBegun    : std_logic;        -- SDRAM operation started indicator
371
  signal ramDone       : std_logic;        -- SDRAM operation complete indicator
372
  signal rdDone        : std_logic;        -- SDRAM read operation complete indicator
373
  signal wrDone        : std_logic;        -- SDRAM write operation complete indicator
374
  signal hAddr         : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
375
  signal hDIn          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
376
  signal hDOut         : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
377
  signal hRd           : std_logic;        -- host-side read control signal
378
  signal hWr           : std_logic;        -- host-side write control signal
379
  signal hUds          : std_logic;        -- host-side upper data strobe
380
  signal hLds          : std_logic;        -- host-side lower data strobe
381
  signal rdPending     : std_logic;        -- read operation pending in SDRAM pipeline
382
  type ram_type is (ram_state_0,
383
                    ram_state_rd1, ram_state_rd2,
384
                    ram_state_wr1,
385
                                                  ram_state_3 );
386
  signal ram_state     : ram_type;
387
 
388
 
389
--  signal BaudCount   : std_logic_vector(5 downto 0);
390
  signal CountL        : std_logic_vector(23 downto 0);
391
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
392
  signal Clk25         : std_logic;
393
  signal vga_clk       : std_logic;
394
 
395
-----------------------------------------------------------------
396
--
397
-- CPU09 CPU core
398
--
399
-----------------------------------------------------------------
400
 
401
component cpu09
402
  port (
403
         clk:        in std_logic;
404
    rst:      in        std_logic;
405
    vma:             out        std_logic;
406
    addr:     out       std_logic_vector(15 downto 0);
407
    rw:      out        std_logic;              -- Asynchronous memory interface
408
         data_out: out std_logic_vector(7 downto 0);
409
    data_in:  in        std_logic_vector(7 downto 0);
410
         irq:      in  std_logic;
411
         firq:     in  std_logic;
412
         nmi:      in  std_logic;
413
         halt:     in  std_logic;
414
         hold:     in  std_logic
415
  );
416
end component;
417
 
418
 
419
----------------------------------------
420
--
421
-- 4K Block RAM Monitor ROM
422
--
423
----------------------------------------
424
component mon_rom
425
    Port (
426
       clk   : in  std_logic;
427
                 rst   : in  std_logic;
428
                 cs    : in  std_logic;
429
                 rw    : in  std_logic;
430
       addr  : in  std_logic_vector (11 downto 0);
431
       data_out : out std_logic_vector (7 downto 0);
432
       data_in : in  std_logic_vector (7 downto 0)
433
    );
434
end component;
435
 
436
 
437
----------------------------------------
438
--
439
-- 8KBytes Block RAM for FLEX9
440
-- $C000 - $DFFF
441
--
442
----------------------------------------
443
component flex_ram
444
  Port (
445
    clk      : in  std_logic;
446
    rst      : in  std_logic;
447
    cs       : in  std_logic;
448
    rw       : in  std_logic;
449
    addr     : in  std_logic_vector (12 downto 0);
450
    data_out    : out std_logic_vector (7 downto 0);
451
    data_in    : in  std_logic_vector (7 downto 0)
452
    );
453
end component;
454
 
455
-----------------------------------------------------------------
456
--
457
-- 6850 Compatible ACIA / UART
458
--
459
-----------------------------------------------------------------
460
 
461
component acia6850
462
  port (
463
     clk      : in  Std_Logic;  -- System Clock
464
     rst      : in  Std_Logic;  -- Reset input (active high)
465
     cs       : in  Std_Logic;  -- miniUART Chip Select
466
     rw       : in  Std_Logic;  -- Read / Not Write
467
     addr     : in  Std_Logic;  -- Register Select
468
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
469
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
470
     irq      : out Std_Logic;  -- Interrupt
471
     RxC      : in  Std_Logic;  -- Receive Baud Clock
472
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
473
     RxD      : in  Std_Logic;  -- Receive Data
474
     TxD      : out Std_Logic;  -- Transmit Data
475
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
476
     CTS_n    : in  Std_Logic;  -- Clear To Send
477
     RTS_n    : out Std_Logic );  -- Request To send
478
end component;
479
 
480
 
481
-----------------------------------------------------------------
482
--
483
-- ACIA Clock divider
484
--
485
-----------------------------------------------------------------
486
 
487
component ACIA_Clock
488
  generic (
489
     SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
490
          ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
491
  );
492
  port (
493
     clk      : in  Std_Logic;  -- System Clock Input
494
          ACIA_clk : out Std_logic   -- ACIA Clock output
495
  );
496
end component;
497
 
498
 
499
----------------------------------------
500
--
501
-- PS/2 Keyboard
502
--
503
----------------------------------------
504
 
505
component keyboard
506
  generic(
507
  KBD_CLK_FREQ : integer := CPU_CLK_FREQ
508
  );
509
  port(
510
  clk             : in    std_logic;
511
  rst             : in    std_logic;
512
  cs              : in    std_logic;
513
  rw              : in    std_logic;
514
  addr            : in    std_logic;
515
  data_in         : in    std_logic_vector(7 downto 0);
516
  data_out        : out   std_logic_vector(7 downto 0);
517
  irq             : out   std_logic;
518
  kbd_clk         : inout std_logic;
519
  kbd_data        : inout std_logic
520
  );
521
end component;
522
 
523
----------------------------------------
524
--
525
-- Video Display Unit.
526
--
527
----------------------------------------
528
component vdu8
529
      generic(
530
        VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
531
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
532
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
533
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
534
             VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
535
             VGA_LIN_PER_CHAR       : integer := 16; -- LINES
536
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
537
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
538
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
539
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
540
             VGA_VER_SYNC           : integer := 2;  -- LINES
541
             VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
542
      );
543
      port(
544
                -- control register interface
545
      vdu_clk      : in  std_logic;      -- CPU Clock - 25MHz
546
      vdu_rst      : in  std_logic;
547
                vdu_cs       : in  std_logic;
548
                vdu_rw       : in  std_logic;
549
                vdu_addr     : in  std_logic_vector(2 downto 0);
550
      vdu_data_in  : in  std_logic_vector(7 downto 0);
551
      vdu_data_out : out std_logic_vector(7 downto 0);
552
 
553
      -- vga port connections
554
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
555
      vga_red_o    : out std_logic;
556
      vga_green_o  : out std_logic;
557
      vga_blue_o   : out std_logic;
558
      vga_hsync_o  : out std_logic;
559
      vga_vsync_o  : out std_logic
560
   );
561
end component;
562
 
563
 
564
----------------------------------------
565
--
566
-- Timer module
567
--
568
----------------------------------------
569
 
570
component timer
571
  port (
572
     clk       : in std_logic;
573
     rst       : in std_logic;
574
     cs        : in std_logic;
575
     rw        : in std_logic;
576
     addr      : in std_logic;
577
     data_in   : in std_logic_vector(7 downto 0);
578
          data_out  : out std_logic_vector(7 downto 0);
579
          irq       : out std_logic
580
          );
581
end component;
582
 
583
------------------------------------------------------------
584
--
585
-- Bus Trap logic
586
--
587
------------------------------------------------------------
588
 
589
component trap
590
        port (
591
         clk        : in  std_logic;
592
    rst        : in  std_logic;
593
    cs         : in  std_logic;
594
    rw         : in  std_logic;
595
    vma        : in  std_logic;
596
    addr       : in  std_logic_vector(15 downto 0);
597
    data_in    : in  std_logic_vector(7 downto 0);
598
         data_out   : out std_logic_vector(7 downto 0);
599
         irq        : out std_logic
600
  );
601
end component;
602
 
603
 
604
----------------------------------------
605
--
606
-- Dynamic Address Translation Registers
607
--
608
----------------------------------------
609
component dat_ram
610
  port (
611
    clk      : in  std_logic;
612
         rst      : in  std_logic;
613
         cs       : in  std_logic;
614
         rw       : in  std_logic;
615
         addr_lo  : in  std_logic_vector(3 downto 0);
616
         addr_hi  : in  std_logic_vector(3 downto 0);
617
    data_in  : in  std_logic_vector(7 downto 0);
618
         data_out : out std_logic_vector(7 downto 0)
619
  );
620
end component;
621
 
622
 
623
 
624
--
625
-- Clock buffer
626
--
627
component BUFG
628
   Port (
629
     i: in std_logic;
630
          o: out std_logic
631
  );
632
end component;
633
 
634
begin
635
  -----------------------------------------------------------------------------
636
  -- Instantiation of internal components
637
  -----------------------------------------------------------------------------
638
 
639
my_cpu : cpu09  port map (
640
         clk         => cpu_clk,
641
    rst       => cpu_reset,
642
    vma       => cpu_vma,
643
    addr      => cpu_addr(15 downto 0),
644
    rw       => cpu_rw,
645
         data_out  => cpu_data_out,
646
    data_in   => cpu_data_in,
647
         irq       => cpu_irq,
648
         firq      => cpu_firq,
649
         nmi       => cpu_nmi,
650
         halt      => cpu_halt,
651
         hold      => cpu_hold
652
  );
653
 
654
my_rom : mon_rom port map (
655
       clk   => cpu_clk,
656
                 rst   => cpu_reset,
657
                 cs    => rom_cs,
658
                 rw    => '1',
659
       addr  => cpu_addr(11 downto 0),
660
       data_in => cpu_data_out,
661
       data_out => rom_data_out
662
    );
663
 
664
--my_flex : flex_ram port map (
665
--    clk       => cpu_clk,
666
--    rst       => cpu_reset,
667
--       cs        => flex_cs,
668
--       rw        => cpu_rw,
669
--    addr      => cpu_addr(12 downto 0),
670
--    data_out     => flex_data_out,
671
--    data_in     => cpu_data_out
672
--    );
673
 
674
my_acia  : acia6850 port map (
675
         clk         => cpu_clk,
676
         rst       => cpu_reset,
677
    cs        => acia_cs,
678
         rw        => cpu_rw,
679
    addr      => cpu_addr(0),
680
         data_in   => cpu_data_out,
681
         data_out  => acia_data_out,
682
    irq       => acia_irq,
683
         RxC       => acia_clk,
684
         TxC       => acia_clk,
685
         RxD       => rxd,
686
         TxD       => txd,
687
         DCD_n     => dcd_n,
688
         CTS_n     => cts_n,
689
         RTS_n     => rts_n
690
         );
691
 
692
 
693
my_ACIA_Clock : ACIA_Clock
694
  generic map(
695
    SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
696
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
697
  )
698
  port map(
699
    clk        => Clk_i,
700
    acia_clk   => acia_clk
701
  );
702
 
703
----------------------------------------
704
--
705
-- PS/2 Keyboard Interface
706
--
707
----------------------------------------
708
--my_keyboard : keyboard
709
--   generic map (
710
--      KBD_CLK_FREQ => CPU_CLK_FREQ
711
--      ) 
712
--   port map(
713
--      clk          => cpu_clk,
714
--      rst          => cpu_reset,
715
--      cs           => keyboard_cs,
716
--      rw           => cpu_rw,
717
--      addr         => cpu_addr(0),
718
--      data_in      => cpu_data_out(7 downto 0),
719
--      data_out     => keyboard_data_out(7 downto 0),
720
--      irq          => keyboard_irq,
721
--      kbd_clk      => ps2_clk,
722
--      kbd_data     => ps2_dat
723
--      );
724
 
725
----------------------------------------
726
--
727
-- Video Display Unit instantiation
728
--
729
----------------------------------------
730
--my_vdu : vdu8 
731
--  generic map(
732
--      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
733
--      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
734
--         VGA_HOR_CHARS          => 80, -- CHARACTERS
735
--         VGA_VER_CHARS          => 25, -- CHARACTERS
736
--         VGA_PIX_PER_CHAR       => 8,  -- PIXELS
737
--         VGA_LIN_PER_CHAR       => 16, -- LINES
738
--         VGA_HOR_BACK_PORCH     => 40, -- PIXELS
739
--         VGA_HOR_SYNC           => 96, -- PIXELS
740
--         VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
741
--         VGA_VER_BACK_PORCH     => 13, -- LINES
742
--         VGA_VER_SYNC           => 2,  -- LINES
743
--         VGA_VER_FRONT_PORCH    => 35  -- LINES
744
--  )
745
--  port map(
746
--
747
--              -- Control Registers
748
--              vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
749
--      vdu_rst       => cpu_reset,
750
--              vdu_cs        => vdu_cs,
751
--              vdu_rw        => cpu_rw,
752
--              vdu_addr      => cpu_addr(2 downto 0),
753
--              vdu_data_in   => cpu_data_out,
754
--              vdu_data_out  => vdu_data_out,
755
--
756
--      -- vga port connections
757
--      vga_clk       => vga_clk,                                        -- 25 MHz VDU pixel clock
758
--      vga_red_o     => vga_red_o,
759
--      vga_green_o   => vga_green_o,
760
--      vga_blue_o    => vga_blue_o,
761
--      vga_hsync_o   => vga_hsync_n,
762
--      vga_vsync_o   => vga_vsync_n
763
--   );
764
 
765
----------------------------------------
766
--
767
-- Timer Module
768
--
769
----------------------------------------
770
my_timer  : timer port map (
771
    clk       => cpu_clk,
772
         rst       => cpu_reset,
773
    cs        => timer_cs,
774
         rw        => cpu_rw,
775
    addr      => cpu_addr(0),
776
         data_in   => cpu_data_out,
777
         data_out  => timer_data_out,
778
    irq       => timer_irq
779
    );
780
 
781
----------------------------------------
782
--
783
-- Bus Trap Interrupt logic
784
--
785
----------------------------------------
786
my_trap : trap port map (
787
         clk        => cpu_clk,
788
    rst        => cpu_reset,
789
    cs         => trap_cs,
790
    rw         => cpu_rw,
791
         vma        => cpu_vma,
792
    addr       => cpu_addr,
793
    data_in    => cpu_data_out,
794
         data_out   => trap_data_out,
795
         irq        => trap_irq
796
    );
797
 
798
 
799
my_dat : dat_ram port map (
800
    clk       => cpu_clk,
801
         rst       => cpu_reset,
802
         cs        => dat_cs,
803
         rw        => cpu_rw,
804
         addr_hi   => cpu_addr(15 downto 12),
805
         addr_lo   => cpu_addr(3 downto 0),
806
    data_in   => cpu_data_out,
807
         data_out  => dat_addr(7 downto 0)
808
         );
809
 
810
cpu_clk_buffer : BUFG port map(
811
    i => Clk25,
812
         o => cpu_clk
813
    );
814
 
815
vga_clk_buffer : BUFG port map(
816
    i => Clk25,
817
         o => vga_clk
818
    );
819
 
820
----------------------------------------------------------------------
821
--
822
-- Process to decode memory map
823
--
824
----------------------------------------------------------------------
825
 
826
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
827
                                                        dat_addr,
828
                                              rom_data_out,
829
                                                        flex_data_out,
830
                                                   acia_data_out,
831
                                                        keyboard_data_out,
832
                                                        vdu_data_out,
833
                                                        pb_data_out,
834
                                                        timer_data_out,
835
                                                        trap_data_out,
836
                                                        ram_data_out
837
                                                        )
838
begin
839
      cpu_data_in <= (others=>'0');
840
      dat_cs      <= '0';
841
      rom_cs      <= '0';
842
      flex_cs     <= '0';
843
           acia_cs     <= '0';
844
           keyboard_cs <= '0';
845
           vdu_cs      <= '0';
846
           timer_cs    <= '0';
847
           trap_cs     <= '0';
848
           pb_cs       <= '0';
849
           ide_cs      <= '0';
850
           ether_cs    <= '0';
851
           slot1_cs    <= '0';
852
           slot2_cs    <= '0';
853
           ram_cs      <= '0';
854
      if cpu_addr( 15 downto 8 ) = "11111111" then
855
              cpu_data_in <= rom_data_out;
856
         dat_cs      <= cpu_vma;              -- write DAT
857
         rom_cs      <= cpu_vma;              -- read  ROM
858
           --
859
                -- Sys09Bug Monitor ROM $F000 - $FFFF
860
                --
861
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
862
                   cpu_data_in <= rom_data_out;
863
                        rom_cs      <= cpu_vma;
864
 
865
      --
866
                -- IO Devices $E000 - $E7FF
867
                --
868
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
869
                        case cpu_addr(11 downto 8) is
870
                        --
871
                        -- SWTPC peripherals from $E000 to $E0FF
872
                        --
873
                        when "0000" =>
874
                     case cpu_addr(7 downto 4) is
875
                          --
876
                          -- Console Port ACIA $E000 - $E00F
877
                          --
878
                          when "0000" => -- $E000
879
                       cpu_data_in <= acia_data_out;
880
                            acia_cs     <= cpu_vma;
881
 
882
           --
883
           -- Reserved
884
                          -- Floppy Disk Controller port $E010 - $E01F
885
                          --
886
 
887
           --
888
           -- Keyboard port $E020 - $E02F
889
                          --
890
                          when "0010" => -- $E020
891
             cpu_data_in <= keyboard_data_out;
892
                            keyboard_cs <= cpu_vma;
893
 
894
           --
895
           -- VDU port $E030 - $E03F
896
                          --
897
                          when "0011" => -- $E030
898
             cpu_data_in <= vdu_data_out;
899
                            vdu_cs      <= cpu_vma;
900
 
901
           --
902
                          -- Reserved SWTPc MP-T Timer $E040 - $E04F
903
                          --
904
                          when "0100" => -- $E040
905
             cpu_data_in <= (others=> '0');
906
 
907
           --
908
           -- Timer $E050 - $E05F
909
                          --
910
                          when "0101" => -- $E050
911
             cpu_data_in <= timer_data_out;
912
             timer_cs    <= cpu_vma;
913
 
914
           --
915
           -- Bus Trap Logic $E060 - $E06F
916
                          --
917
                          when "0110" => -- $E060
918
             cpu_data_in <= trap_data_out;
919
                            trap_cs     <= cpu_vma;
920
 
921
           --
922
                          -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
923
                          --
924
 
925
           --
926
                          -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
927
                          --
928
 
929
                          --
930
                          -- Remaining 6 slots reserved for non SWTPc Peripherals
931
                          --
932
                          when others => -- $E0A0 to $E0FF
933
                            null;
934
                     end case;
935
                        --
936
                        -- XST-3.0 Peripheral Bus goes here
937
                        --      $E100 to $E1FF
938
                        --      Four devices
939
                        -- IDE, Ethernet, Slot1, Slot2
940
                        --
941
                        when "0001" =>
942
                          cpu_data_in <= pb_data_out;
943
                          pb_cs       <= cpu_vma;
944
                     case cpu_addr(7 downto 6) is
945
                          --
946
                          -- IDE Interface $E100 to $E13F
947
                          --
948
                          when "00" =>
949
                            ide_cs   <= cpu_vma;
950
                          --
951
                          -- Ethernet Interface $E140 to $E17F
952
                          --
953
                          when "01" =>
954
                            ether_cs <= cpu_vma;
955
                          --
956
                          -- Slot 1 Interface $E180 to $E1BF
957
                          --
958
                          when "10" =>
959
                            slot1_cs <= cpu_vma;
960
                          --
961
                          -- Slot 2 Interface $E1C0 to $E1FF
962
                          --
963
                          when "11" =>
964
                            slot2_cs <= cpu_vma;
965
           --
966
                          -- Nothing else
967
                          --
968
           when others =>
969
                            null;
970
           end case;
971
         --
972
                        --      $E200 to $EFFF reserved for future use
973
                        --
974
                when others =>
975
                          null;
976
         end case;
977
                --
978
                -- Flex RAM $0C000 - $0DFFF
979
                --
980
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
981
                   cpu_data_in <= flex_data_out;
982
                        flex_cs     <= cpu_vma;
983
                --
984
                -- Everything else is RAM
985
                --
986
                else
987
                   cpu_data_in <= ram_data_out;
988
                   ram_cs      <= cpu_vma;
989
          end if;
990
end process;
991
 
992
 
993
--
994
-- 16-bit Peripheral Bus
995
-- 6809 Big endian
996
-- ISA bus little endian
997
-- Not sure about IDE interface
998
--
999
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out,
1000
                         pb_cs, pb_wreg, pb_rreg )
1001
begin
1002
  pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
1003
  pb_wrl <= pb_cs and (not cpu_rw) and      cpu_addr(0) ;
1004
  pb_rdu <= pb_cs and      cpu_rw  and (not cpu_addr(0));
1005
  pb_rdl <= pb_cs and      cpu_rw  and      cpu_addr(0) ;
1006
  pb_a   <= cpu_addr(5 downto 1);
1007
 
1008
  --
1009
  -- Register upper byte from CPU on first CPU write
1010
  -- and lower byte from the peripheral bus on first CPU read
1011
  --
1012
  if cpu_reset = '1' then
1013
    pb_wreg <= (others => '0');
1014
    pb_rreg <= (others => '0');
1015
  elsif clk_i'event and clk_i ='1' then
1016
    if pb_wru = '1' then
1017
           pb_wreg <= cpu_data_out;
1018
    end if;
1019
    if pb_rdu = '1' then
1020
           pb_rreg <= pb_d(7 downto 0);
1021
    end if;
1022
   end if;
1023
  --
1024
  -- Peripheral bus read and write strobes are
1025
  -- Syncronized with the 50 MHz clock
1026
  -- and are asserted until the peripheral bus hold is released
1027
  --
1028
  if cpu_reset = '1' then
1029
    pb_wr_n <= '1';
1030
    pb_rd_n <= '1';
1031
  elsif clk_i'event and clk_i ='1' then
1032
         if pb_hold = '1' then
1033
           pb_wr_n  <= not pb_wrl;
1034
           pb_rd_n  <= not pb_rdu;
1035
    else
1036
      pb_wr_n <= '1';
1037
      pb_rd_n <= '1';
1038
    end if;
1039
  end if;
1040
  --
1041
  -- The peripheral bus will be an output 
1042
  -- the registered even byte on data(15 downto 8)
1043
  -- and the CPU odd bytes on data(7 downto 0)
1044
  -- on odd byte writes
1045
  --
1046
  if pb_wrl = '1' then
1047
    pb_d <= pb_wreg & cpu_data_out;
1048
  else
1049
    pb_d <= (others => 'Z');
1050
  end if;
1051
 
1052
  --
1053
  -- On even byte reads,
1054
  -- the CPU reads the low (even) byte of the peripheral bus
1055
  -- On odd byte reads,
1056
  -- the CPU reads the registered (odd byte) input from the peripheral bus
1057
  --
1058
  if pb_rdu = '1' then
1059
    pb_data_out <= pb_d(15 downto 8);
1060
  elsif pb_rdl = '1' then
1061
    pb_data_out <= pb_rreg;
1062
  else
1063
    pb_data_out <= (others => '0');
1064
  end if;
1065
 
1066
end process;
1067
 
1068
--
1069
-- Hold Peripheral bus accesses for a few cycles
1070
--
1071
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl ) --, ether_rdy )
1072
begin
1073
    if cpu_reset = '1' then
1074
                 pb_release    <= '0';
1075
                 pb_count      <= "0000";
1076
            pb_hold_state <= hold_release_state;
1077
         elsif rising_edge(cpu_clk) then
1078
  --
1079
  -- The perpheral bus hold signal should be generated on 
1080
  -- 16 bit bus read which will be on even byte reads or 
1081
  -- 16 bit bus write which will be on odd byte writes.
1082
  -- 
1083
            case pb_hold_state is
1084
                 when hold_release_state =>
1085
          pb_release <= '0';
1086
                    if (pb_rdu = '1') or (pb_wrl = '1') then
1087
                            pb_count      <= "0100";
1088
                                 pb_hold_state <= hold_request_state;
1089
          elsif (pb_rdl = '1') or (pb_wru = '1') then
1090
             pb_release    <= '1';
1091
                                 pb_hold_state <= hold_release_state;
1092
                         end if;
1093
 
1094
                 when hold_request_state =>
1095
                         if pb_count = "0000" then
1096
--            if ether_rdy = '1' then
1097
              pb_release    <= '1';
1098
                                  pb_hold_state <= hold_release_state;
1099
--            end if;
1100
          else
1101
                       pb_count <= pb_count - "0001";
1102
                         end if;
1103
       when others =>
1104
                    null;
1105
       end case;
1106
         end if;
1107
end process;
1108
 
1109
--
1110
-- Compact Flash Control
1111
--
1112
compact_flash: process( ide_cs, cpu_addr )
1113
begin
1114
         ide_cs0_n  <= not( ide_cs ) or cpu_addr(4);
1115
         ide_cs1_n  <= not( ide_cs and cpu_addr(4));
1116
         ide_dmack_n  <= '1';
1117
end process;
1118
 
1119
--
1120
-- Interrupts and other bus control signals
1121
--
1122
interrupts : process( SW3_N,
1123
                                                         pb_cs, pb_hold, pb_release, ram_hold,
1124
--                                                       ether_irq, 
1125
                      acia_irq,
1126
                                                         keyboard_irq,
1127
                                                         trap_irq,
1128
                                                         timer_irq
1129
                                                         )
1130
begin
1131
    pb_hold    <= pb_cs and (not pb_release);
1132
    cpu_irq    <= acia_irq or keyboard_irq;
1133
         cpu_nmi    <= trap_irq or not( SW3_N );
1134
         cpu_firq   <= timer_irq;
1135
         cpu_halt   <= '0';
1136
         cpu_hold   <= pb_hold or ram_hold;
1137
    FLASH_CE_N <= '1';
1138
end process;
1139
 
1140
 
1141
--
1142
-- Flash 7 segment LEDS
1143
--
1144
my_led_flasher: process( clk_i, rst_i, CountL )
1145
begin
1146
    if rst_i = '1' then
1147
                   CountL <= "000000000000000000000000";
1148
    elsif rising_edge(clk_i) then
1149
                   CountL <= CountL + 1;
1150
    end if;
1151
--       S(7 downto 0) <= CountL(23 downto 16);
1152
end process;
1153
 
1154
--
1155
-- Generate CPU & Pixel Clock from Memory Clock
1156
--
1157
my_prescaler : process( clk_i, clk_count )
1158
begin
1159
  if rising_edge( clk_i ) then
1160
 
1161
    if clk_count = 0 then
1162
           clk_count <= CPU_CLK_DIV-1;
1163
         else
1164
      clk_count <= clk_count - 1;
1165
         end if;
1166
 
1167
    if clk_count = 0 then
1168
            clk25 <= '0';
1169
    elsif clk_count = (CPU_CLK_DIV/2) then
1170
            clk25 <= '1';
1171
    end if;
1172
 
1173
  end if;
1174
end process;
1175
 
1176
--
1177
-- Reset button and reset timer
1178
--
1179
my_switch_assignments : process( rst_i, SW2_N, lock )
1180
begin
1181
  rst_i <= not SW2_N;
1182
  cpu_reset <= rst_i or (not lock);
1183
end process;
1184
 
1185
--
1186
-- RS232 signals:
1187
--
1188
my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
1189
begin
1190
  rxd       <= RS232_RXD;
1191
  cts_n     <= RS232_CTS;
1192
  dcd_n     <= '0';
1193
  RS232_TXD <= txd;
1194
  RS232_RTS <= rts_n;
1195
end process;
1196
 
1197
--
1198
-- Pin assignments for ethernet controller
1199
--
1200
my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
1201
begin
1202
    ether_cs_n  <= not ether_cs;
1203
    ether_aen   <= not ether_cs; -- Ethernet address enable not 
1204
    ether_bhe_n <= '1';          -- Ethernet bus high enable - 8 bit access only
1205
end process;
1206
 
1207
--
1208
-- I/O expansion slot assignments
1209
--
1210
my_slot_assignments : process( slot1_cs, slot2_cs)
1211
begin
1212
    slot1_cs_n <= not slot1_cs;
1213
    slot2_cs_n <= not slot2_cs;
1214
end process;
1215
 
1216
--
1217
-- VGA ouputs
1218
--
1219
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
1220
begin
1221
  VGA_red(0)   <= vga_red_o;
1222
  VGA_red(1)   <= vga_red_o;
1223
  VGA_red(2)   <= vga_red_o;
1224
  VGA_green(0) <= vga_green_o;
1225
  VGA_green(1) <= vga_green_o;
1226
  VGA_green(2) <= vga_green_o;
1227
  VGA_blue(0)  <= vga_blue_o;
1228
  VGA_blue(1)  <= vga_blue_o;
1229
  VGA_blue(2)  <= vga_blue_o;
1230
end process;
1231
 
1232
--
1233
-- SDRAM read write control
1234
--
1235
my_sdram_rw : process( clk_i, cpu_reset,
1236
                       opBegun, ramDone,
1237
                                                          ram_state,
1238
                       ram_rd_req, ram_wr_req )
1239
begin
1240
  if( cpu_reset = '1' ) then
1241
         hRd        <= '0';
1242
    hWr        <= '0';
1243
         ram_hold   <= '0';
1244
         ram_state  <= ram_state_0;
1245
 
1246
  elsif( falling_edge(clk_i) ) then
1247
    --
1248
         -- ram state machine
1249
         --
1250
    case ram_state is
1251
 
1252
    when ram_state_0 =>
1253
                if ram_rd_req = '1' then
1254
        ram_hold   <= '1';
1255
             hRd        <= '1';
1256
                  ram_state  <= ram_state_rd1;
1257
      elsif ram_wr_req = '1' then
1258
             ram_hold   <= '1';
1259
        hWr        <= '1';
1260
             ram_state  <= ram_state_wr1;
1261
      end if;
1262
 
1263
    when ram_state_rd1 =>
1264
           if opBegun = '1' then
1265
                  hRd        <= '0';
1266
                  ram_state  <= ram_state_rd2;
1267
      end if;
1268
 
1269
    when ram_state_rd2 =>
1270
           if ramDone = '1' then
1271
                  ram_hold   <= '0';
1272
                  ram_state  <= ram_state_3;
1273
                end if;
1274
 
1275
    when ram_state_wr1 =>
1276
           if opBegun = '1' then
1277
                  ram_hold   <= '0';
1278
                  hWr        <= '0';
1279
                  ram_state  <= ram_state_3;
1280
      end if;
1281
 
1282
    when ram_state_3 =>
1283
           if ram_release = '1' then
1284
                  ram_state  <= ram_state_0;
1285
      end if;
1286
 
1287
         when others =>
1288
                hRd        <= '0';
1289
                hWr        <= '0';
1290
                ram_hold   <= '0';
1291
                ram_state  <= ram_state_0;
1292
         end case;
1293
 
1294
  end if;
1295
end process;
1296
 
1297
--
1298
-- SDRAM Address and data bus assignments
1299
--
1300
my_sdram_addr_data : process( cpu_addr, dat_addr,
1301
                                cpu_data_out, hDout )
1302
begin
1303
  hAddr(23 downto 19)  <= "00000";
1304
  hAddr(18 downto 11)  <= dat_addr;
1305
  hAddr(10 downto 0)   <= cpu_addr(11 downto 1);
1306
  hUds                 <= not cpu_addr(0);
1307
  hLds                 <=     cpu_addr(0);
1308
  if cpu_addr(0) = '0' then
1309
     hDin( 7 downto 0) <= (others=>'0');
1310
     hDin(15 downto 8) <= cpu_data_out;
1311
     ram_data_out      <= hDout(15 downto 8);
1312
  else
1313
     hDin( 7 downto 0) <= cpu_data_out;
1314
     hDin(15 downto 8) <= (others=>'0');
1315
     ram_data_out      <= hDout( 7 downto 0);
1316
  end if;
1317
end process;
1318
 
1319
--
1320
-- Hold RAM until falling CPU clock edge
1321
--
1322
ram_bus_hold: process( cpu_clk, cpu_reset, ram_hold )
1323
begin
1324
    if ram_hold = '1' then
1325
                 ram_release   <= '0';
1326
         elsif falling_edge(cpu_clk) then
1327
                 ram_release   <= '1';
1328
         end if;
1329
end process;
1330
 
1331
--
1332
-- CPU read data request on rising CPU clock edge
1333
--
1334
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
1335
begin
1336
         if hRd = '1' then
1337
                ram_rd_req   <= '0';
1338
         elsif rising_edge(cpu_clk) then
1339
           if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
1340
                  ram_rd_req   <= '1';
1341
      end if;
1342
         end if;
1343
end process;
1344
 
1345
--
1346
-- CPU write data to RAM valid on rising CPU clock edge
1347
--
1348
ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
1349
begin
1350
    if hWr = '1' then
1351
                 ram_wr_req   <= '0';
1352
         elsif rising_edge(cpu_clk) then
1353
                if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
1354
                  ram_wr_req   <= '1';
1355
      end if;
1356
         end if;
1357
end process;
1358
 
1359
 
1360
 
1361
status_leds : process( rst_i, cpu_reset, lock )
1362
begin
1363
    S(0) <= rst_i;
1364
         S(1) <= cpu_reset;
1365
         S(2) <= lock;
1366
         S(3)   <= countL(23);
1367
         S(7 downto 4) <= "0000";
1368
end process;
1369
 
1370
--debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
1371
--                      cpu_halt, cpu_hold,
1372
--                      cpu_firq, cpu_irq, cpu_nmi,
1373
--                      cpu_addr, cpu_data_out, cpu_data_in )
1374
--begin
1375
--  cpu_reset_o    <= cpu_reset;
1376
--  cpu_clk_o      <= cpu_clk;
1377
--  cpu_rw_o       <= cpu_rw;
1378
--  cpu_vma_o      <= cpu_vma;
1379
--  cpu_halt_o     <= cpu_halt;
1380
--  cpu_hold_o     <= cpu_hold;
1381
--  cpu_firq_o     <= cpu_firq;
1382
--  cpu_irq_o      <= cpu_irq;
1383
--  cpu_nmi_o      <= cpu_nmi;
1384
--  cpu_addr_o     <= cpu_addr;
1385
--  cpu_data_out_o <= cpu_data_out;
1386
--  cpu_data_in_o  <= cpu_data_in;
1387
--end process;
1388
 
1389
 
1390
end rtl; --===================== End of architecture =======================--
1391
 

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